On the Adders with Minimum Tests

Transcription

1 Proceeding of the 5th Ain Tet Sympoium (ATS '97) On the Adder with Minimum Tet Seiji Kjihr nd Tutomu So Dept. of Computer Science nd Electronic, Kyuhu Intitute of Technology Atrct Thi pper conider two type of n-it dder, ripple crry dder nd ccded crry look-hed dder, with minimum tet for tuck-t fult model. In the firt prt, we preent two type of full dder coniting of five gte, nd how their minimlity. We lo prove tht one of the full dder cn e teted y only three tet pttern for ingle tuck-t fult. We lo preent two type of 4-it crry look-hed dder nd their minimum tet. In the econd prt, we conider the tet for the ccded dder, n n-it ripple crry dder nd 4m-it ccded crry look-hed dder. Thee tet re coniderly mller thn previouly pulihed one. In thi pper, we conider two type of n-it dder with minimum tet for tuck-t fult model: Ripple crry dder nd ccded crry look-hed dder. Firt, we how the minimlity of full dder hown in Fig. 1. They contin the minimum numer of gte mong dder coniting of only 2- input gte. We lo how tht the ize of the minimum tet for ingle tuck-t fult in the full dder of Fig. 1A nd 1B re five nd three, repectively. To our knowledge, the full g 1 1. Introduction Adder re ued in lmot ll kind of rithmetic proceing unit. The ic unit in n dder i full dder. Fig. 1A nd 1B how two reliztion of full dder uing EXOR gte. By ccding the full dder, we hve ripple crry dder hown in Fig. 2. Thi kind of network i clled n itertive logic rry [1]. In term of itertive logic rry, ripple crry dder i referred to n rry, nd the full dder i referred to cell. The fult umption in cell of the itertive logic rry i tht fulty cell cn chnge it ehvior in ny ritrry wy, long it remin comintionl circuit. In ingle cell fult model (i.e., t mot one cell my e fulty), ny n-it ripple crry dder cn e teted y eight tet independently of the vlue of n [2]. In multiple cell fult model (i.e., more thn one cell cn e fulty t the me time), ny n-it ripple crry dder cn e teted y 11 tet independently of the vlue of n [2]. The tet for the ccded dder where ech cell i p-it dder h een lo conidered in [2]. In thi ce, the ize of the tet i 3 2 p-1. The ripple crry dder re imple nd ueful when n i mll. For exmple, INTEL 8080 micro-proceor ued ripple crry dder [3]. However, when n i lrge, ripple crry dder re low ince the mximum crry propgtion time i proportionl to n. Thu, crry look-hed dder re often ued for high-peed ddition. Fig. 3A nd 3B how two reliztion of 4-it crry look-hed dder. Becker [4] howed tht 6 (log 2 n) - 4 tet re ufficient to tet the n-it crry look-hed dder, for ingle tuck-t fult in given et of ic cell. Thi reerch i upported in prt y the Minitry of Eduction, Culture, Science nd Sport of Jpn. c 0 Fig. 1A: Full dder uing AND, OR, EXOR gte g 1 Fig. 1B: Full dder uing AND, EXOR gte n n 1 2 g 3 g 4 g 3 g 4 c 1 c 2 c n-1 Fig. 2: Ripple crry dder g 2 g 5 g 2 g 5 n c n n+1

2 Proceeding of the 5th Ain Tet Sympoium (ATS '97) dder in Fig. 1B h the mllet tet ize. Next, we how tht the ize of the minimum tet for ingle tuck-t fult in the 4-it crry look-hed dder hown in Fig. 3A nd 3B re 10 nd 12, repectively. Then, we conider the tet for the ccded dder. In the ce of n n-it ripple crry dder, the ize of the minimum tet for ingle fult re the me tht of the full dder, nd ll multiple tuck-t fult cn e detected y ix tet. In the ce of 4m-it ccded crry look-hed dder, we how tht the ize of the minimum tet re le thn 12 for ingle tuck-t fult. Note tht the ize of the tet i contnt, nd i independent of the vlue of n nd m. Thee tet re coniderly mller thn tht of [2], where =767 tet re necery. 2. Adder nd their tet 2.1 Minimum full dder Firt, we conider two different reliztion of full dder, Fig 1A nd 1B, oth conit of five 2-input gte. Theorem 1. Conider the network coniting of only 2-input gte. The full dder hown in Fig. 1 contin the minimum numer of gte. (Proof) Here, we will how tht there i no full dder with four or fewer 2-input gte. Since we need two gte for um nd crry, the full dder mut hve the tructure hown in Fig. 4. By conidering ll poile network, we cn how tht it i impoile to relize full dder. Thu, the minimum dder conit of t let five 2-input gte. (Q.E.D.) The full dder hown in Fig. 1A i more populr [5] thn one in Fig. 1B tht contin only AND nd EXOR gte. Without uing EXOR (EXNOR) gte, we need more gte to relize full dder. For exmple, full dder uing eight 2- input gte i hown in [6]. 2.2 Tet for the full dder Under the umption of the ingle tuck-t fult model, there i no redundnt fult in oth of the full dder in Fig. 1A c c 4 Fig. 3A: 4-it crry look-hed dder uing AND, OR, EXOR gte

3 Proceeding of the 5th Ain Tet Sympoium (ATS '97) c c 4 Fig. 3B: 4 it crry look-hed dder uing AND, EXOR gte gte A gte C gte B gte D Fig. 4: Proof of minimlity of full dder um crry nd Fig. 1B. All the fult cn e detected y the tet in Tle 1A nd Tle 1B, where x, y {0, 1}. Theorem 2. Tle 1A nd Tle 1B give minimum tet et for ingle tuck-t fult in the full dder in Fig. 1A nd Fig. 1B, repectively. (Proof) For the dder in Fig. 1A, conider the fult et {g 1 _g 3 / 1, _g 4 /1, _g 4 /1, g 4 /1, g 3 /1}, where g 1 _g 3 /1 denote the tuck-t 1 fult on the fnout rnch of gte g 1 to gte g 3. Tle 2 how necery ignment for ech fult which re logic vlue on ignl line necerily to detect the fult. Since necery ignment for ny pir of fult hve conflict, it i impoile to generte tet tht detect them t the me time. Therefore, the fult et i n independent fult et [7], nd t let five tet re necery to detect ll fult. On the other hnd, five tet in Tle 1 detect ll the fult. Thu, the tet et in Tle 1A i the minimum for the circuit in Fig. 1A. For the dder in Fig. 1B, t let three tet re necery to detect ll fult ecue there re 2-input gte. Hence the tet et in Tle 1B i the minimum for the circuit in Fig. 1B. (Q.E.D.) To our et knowledge, Fig. 1B i the full dder with the mllet tet ize. Other full dder uing more gte require more tet. 2.3 Crry Look-Ahed Adder

4 Proceeding of the 5th Ain Tet Sympoium (ATS '97) Vriou crry look-hed dder exit. Among them, one hown in Fig. 3A [3] i populr. However, to invetigte the tetility, we will lo conider two other reliztion. A the firt vrition, conider the circuit where ll the OR gte in the input (i.e., one relizing i i ) re replced y EXOR gte. It lo work n dder [8]. A the econd vrition, conider circuit in Fig. 3B. Thi i otined y replcing ll the OR gte in Fig. 3A y two-input EXOR gte. Note tht it conit of AND nd EXOR. Thi lo work n dder hown elow: Theorem 3. The circuit where ll the OR gte in Fig. 3A re replced y EXOR gte lo work n dder. (Proof i in [12]) One might think of yet nother vrition of the dder: A reliztion derived y replcing the OR gte in the lrge dhed ox in Fig. 3A with EXOR gte (i.e., OR gte in the mll dhed oxe remin), unfortuntely, it doe not work n dder. 2.4 Tet for the Crry Look-Ahed Adder We ued compct tet genertor [9] to generte miniml tet et nd to find mximl independent fult et of the crry look-hed dder. For the dder in Fig. 3A, n independent fult et with 10 fult w found, nd 10 tet to detect ll ingle tuck-t fult hown in Tle 3A were generted. Thu, the 10 tet form minimum tet et for the dder in Fig. 3A. Tle 1A: Tet for the full dder in FIg. 1A In Out tet t t t t x x 1 t 5 y y Tle 1B: Tet for the full dder in FIg. 1B In Out tet t t t Tle 2: Necery Aignment fult g 3 g 4 g 5 g 1 _g 3 / _g 4 / _g 4 / g 3 /1 1 1 x /1 y y g 4 For the dder in Fig. 3B, n independent fult et with 12 fult w found, nd 12 tet hown in Tle 3B cn detect ll ingle fult. Thu, the 12 tet form minimum tet et for the dder in Fig 3B. Thi i lrger thn the ize of the minimum tet for the dder in Fig. 3A. One of the coniderle reon i tht we ued tree of 2-input EXOR gte, inted of multiple-input EXOR gte. For exmple, 2-input EXOR gte require three tet for ingle tuck-t fult, ut 3-input EXOR gte cn e teted y only two tet. Therefore, the ue of multiple-input EXOR gte my reduce the numer of tet. 3. Minimum tet for ccded dder 3.1 Tet for ripple crry dder The ripple crry dder hown in Fig. 2 conit of cell of the full dder, where the primry output,, of the full dder i connected to the primry input,, of the next full dder. In thi ection, we how how to contruct minimum tet for the ripple crry dder n rry of the full dder. In order to ue the tet of the full dder for the ripple crry dder, it i required to tify two condition elow: (1) to pply the tet of the full dder for ech cell. (2) to oerve the output of ech cell where fult effect my e propgted. The following theorem how tht thee condition cn e tified. Theorem 4. Any tet for the full dder cn e pplied to ech cell of the ripple crry dder. (Proof) For the firt cell, the theorem hold. For the ith cell (i 2), the ignl line c i-1 tht connect the (i-1) th cell with the i th cell i controllle uing the primry input, i-1 nd i-1. Hence, the theorem hold. (Q.E.D.) Theorem 5. If tet for the full dder re pplied to ech cell of the ripple crry dder, fult in the ripple crry dder re detected. (Proof) Suppoe tht tet for the full dder re pplied to the ith cell of the ripple crry dder. If effect of fult in the ith cell re propgted to i, the fult cn e detected. Even if fult effect re propgted to c i, it cn e detected t the primry output i+1 independently of the logic vlue of i+1 nd i+1. Thu, ny fult in cell i detected y the tet for the cell, nd the theorem hold. (Q.E.D.) The logic vlue t of the ith cell correpond to the logic vlue t of the (i+1)th cell. For the rry of cell in Fig. 1A, whenever the tet t 2, t 3, or t 5 in Tle 1A re pplied to the ith cell, the me tet cn e pplied to the (i+1)th cell ecue logic vlue required t of the (i+1)th cell nd of the ith cell re identicl. However, when tet t 1 i pplied to the ith cell, to the (i+1)th cell, nother tet which require logic vlue 0 t hould e pplied. We chieve it y igning logic vlue 0 to x of tet t 4. Converely, when tet t 4 i pplied to the ith cell, tet t 1 i pplied to the (i+1)th cell. A reult, y igning logic vlue 0 to x of tet t 4 nd logic vlue 0 to y of tet t 5, we cn otin five tet hown in Tle 4 to detect ll ingle fult in the ripple crry dder

5 Proceeding of the 5th Ain Tet Sympoium (ATS '97) ed on the full dder in Fig. 1A. Similrly, we cn otin three tet for the ripple crry dder ed on the full dder in Fig. 1B ecue logic vlue t nd re identicl for every tet. Thee tet otined for the rry re minimum ecue their ize re the me thoe of the minimum tet for ech cell. 3.2 Tet for multiple tuck-t fult in ripple crry dder Under the umption of the multiple tuck-t fult model, tuck-t fult re tken into ccount only t fnout rnche nd the primry input which re clled checkpoint. Thi i ecue every multiple tuck-t fult cn e repreented y Tle 3A: Tet for the crry look-hed dder in FIg. 3A In Out tet c 0 c 4 t t t t t t t t t t Tle 3B: Tet for the crry look-hed dder in FIg. 3B In Out tet c 0 c 4 t t t t t t t t t t t t Tle 4: Minimum tet for the ripple crry dder tet 1 1 c T T T T T comintion of tuck-t fult on checkpoint [10]. Both of the full dder in Fig. 1A nd 1B hve 11 checkpoint, i.e.,,,, fnin line of gte g 1, g 2, g 3, nd g 4. If we tret multiple tuck-t fult in the ripple crry dder, we mut ume fult on every checkpoint in ech cell. The tet in Tle 1A cn detect ll multiple tuck-t fult in the full dder of Fig. 1A. Any multiple fult which contin tuck-t fult on line etween the primry input,,, nd the primry output re detected t. And ny multiple fult which contin tuck-t fult on fnin line of gte g 3 nd g 4 re detected t. For the ripple crry dder, however, the five tet in Tle 4 cnnot detect ll multiple fult. For exmple, multiple fult ( 2 /1, 2 /0, g 1 _g 3 /1, _g 4 /0, _g 4 /1) remin undetected. Although we cn produce other 5 tet to detect ll ingle fult y igning logic vlue 1 to y in Tle 1A, the multiple fult cnnot e detected. A ny other five tet cnnot detect ll ingle fult, t let ix tet re required for detecting ll multiple fult. By dding tet uch tht the logic vlue of every primry input i 1 to the tet in Tle 4, ll multiple fult cn e detected. It i proven uing n ide of the fult nlyi method in [11]. Theorem 6. Six tet in Tle 5 detect ll multiple tuck-t fult of the ripple crry dder coniting of the full dder in Fig. 1A. (Proof i in [12]) Since it i impoile to detect ll multiple fult y five tet, the tet in Tle 5 re minimum. Alo, they detect ll multiple fult in the ripple crry dder uing the full dder in Fig 1B. But they my not e minimum tet for the circuit. 3.3 Tet for ingle tuck-t fult in 4m-it crry look-hed dder By ccding the 4-it crry look-hed dder in Fig. 3A or Fig. 3B, we cn relize 4m-it dder. We conider the ize of tet for ingle fult in the ccded crry look-hed dder. A hown in Section 2.4, the ize of the minimum tet for the dder in Fig. 3A i 10. However, we could not produce tet et whoe ize i 10 uing the tet in Tle 3A. The numer of tet which require logic vlue 1 t i ix (i.e., t 1, t 2, t 3, t 6, t 7 nd t 9 ), ut the numer of tet which produce Tle 5: Minimum tet for multiple fult of the ripple crry dder tet 1 1 c T T T T T T

6 Tle 6: Tet for the 4m-it ccded look-hed dder tet c T T T T T T T T T T T logic vlue 1 t i five (i.e., t 4, t 5, t 6, t 8 nd t 9 ). Accordingly, if we ue the tet in Tle 3A without repeting me one, one of the ix tet cnnot e pplied. In order to void miing ny tet, we dd n dditionl tet uch tht logic vlue 0 i igned to input nd logic vlue 1 t output i produced. A reult, we otin 11 tet for the ccded look-hed dder. An exmple of uch tet i hown in Tle 6. Note tht we hve not proven the minimlity of the tet in Tle 6. For the 4m-it crry look-hed dder relized y ccding the dder in Fig. 3B, we cn otin 12 tet to detect ingle tuck-t fult. The 12 tet re minimum for the circuit nd it cn e proven y the imilr wy to Theorem 4 nd Concluion nd comment In thi pper, we preented minimum tet for ripple crry dder nd ccded crry look-hed dder. Epecilly, we preented ripple crry dder tht cn e teted y only three tet. Thee tet re coniderly mller thn previouly pulihed one. Thi i due to the compct full dder uing more EXOR gte. Without EXOR gte, dder nd their tet will e more complex. Thu, for the tuck-t fult model, we cn y follow: EXOR ed ripple crry dder re eily tetle. REFERENCES [1] W. H. Kutz, Teting for Fult in Cellulr Logic Arry, 8th Annu. Sympo. Switching nd Automt Theory, pp , [2] W. -T. Cheng, nd J. H. Ptel, A Minimum Tet et for Multiple Fult Detection in Ripple crry Adder, IEEE Trn. Comput., vol. C-36, no. 7, 891-5, July [3] S. Murog, Logic Deign nd Switching Theory, Wiley- Intercience Puliction, pp , [4] B. Becker, Efficient Teting of Optiml Time Adder, IEEE Trn. Comput., vol. 37, no. 9, , Sept [5] F. J. Hill, nd G. R. Peteron, Introduction to Switching Theory nd Logicl Deign (Third Edition), John Wiley & Son, p. 180, [6] Z. Kohvi, Switching nd Automt Theory, McGrw-Hill, p. 116, [7] S. B. Aker, nd B. Krihnmurthy, On the Appliction of Tet Counting to VLSI Teting, Technicl Report No. CR , Computer Reerch Lortory, Tektronix Lortorie, April [8] R. F. Tinder, Digitl Engineering Deign, Prentice-Hll, p. 274, [9] S. Kjihr, I. Pomernz, K. Kinohit nd S. M. Reddy, Cot-Effective Genertion of Miniml Tet Set for Stuckt Fult in Comintionl Logic Circuit IEEE Trn. on CAD., Vol. 14, No. 12, pp , Dec [10] D. C. Boen, nd S. J. Hong, Cue-Effect Anlyi for Multiple Fult Detection in Comintionl Network, IEEE Trn. on Comput., vol. C-20, pp , Nov [11] H. Cox, nd J. Rjki, A Method of Fult Anlyi for Tet Genertion nd Fult Dignoi, IEEE Trn. on CAD., vol. 7, pp , July [12] S. Kjihr, nd T. So, Minimum tet for tuck-t fult of the dder, IEICE Technicl Report, Vol. FTS-96, Oct (to pper) [13] M. J. Btek, nd J. P. Hye, Tet-et Preerving Logic Trnformtion, 29th ACM/IEEE Deign Automtion Conference, pp , [14] B. Becker, R. Drechler, nd P. Molitor, On the Genertion of Are-time Optiml Tetle Adder IEEE Trn. on CAD., vol. 14, no. 9, , Sept [15] B. Becker, R. Drechler, R. Krieger, nd S. M. Reddy, A Ft Optiml Rout Pth Dely Fult Tetle Adder, Europen Deign nd Tet Conference ED&TC 96, pp , [16] T. -K. Liu, K. R. Hohlin, L. -E. Shiu, nd S. Murog, Optiml One-it Full Adder with Different Type of Gte, IEEE Trn. Comput., vol. C-23, No. 1, pp , Jn Proceeding of the 5th Ain Tet Sympoium (ATS '97)