Fixed-Priority Multiprocessor Scheduling with Liu & Layland s Utilization Bound

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1 Fxed-Prorty Multprocessor Schedulng wth Lu & Layland s Utlzaton Bound Nan Guan, Martn Stgge, Wang Y and Ge Yu Department of Informaton Technology, Uppsala Unversty, Sweden Department of Computer Scence and Technology, Northeastern Unversty, Chna Abstract Lu and Layland dscovered the famous utlzaton bound N( N 1 1) for fxed-prorty schedulng on sngleprocessor systems n the 1970 s. Snce then, t has been a long standng open problem to fnd fxed-prorty schedulng algorthms wth the same bound for multprocessor systems. In ths paper, we present a parttonng-based fxed-prorty multprocessor schedulng algorthm wth Lu and Layland s utlzaton bound. Keywords-real-tme systems; utlzaton bound; multprocessor; fxed prorty schedulng I. INTRODUCTION Utlzaton bound s a well-nown concept frst ntroduced by Lu and Layland n ther semnal paper [19]. Utlzaton bound can be used as a smple and practcal way to test the schedulablty of real-tme tas sets, as well as a good metrc to evaluate the qualty of a schedulng algorthm. It was shown that the utlzaton bound of Rate Monotonc Schedulng (RMS) on sngle processors s N( 1 N 1). For smplcty of presentaton we let Θ(N) = N( 1 N 1). Multprocessor schedulng are usually categorzed nto two paradgms [10]: global schedulng, n whch each tas can execute on any avalable processor n the run tme, and parttoned schedulng n whch each tass s assgned to a processor beforehand, and durng the run tme each tas can only execute on ths partcular processor. Although global schedulng on average utlzes computng resource better, the best nown utlzaton bound of global fxed-prorty schedulng s only 38% [3], whch s much lower than the best nown result of parttoned fxed-prorty schedulng 50% [7]. 50% s also nown as the maxmum utlzaton bound for both global and parttoned fxed-prorty schedulng [4], [0]. Although there exst schedulng algorthms, le the pfar famly [], [9], offerng utlzaton bounds of 100%, these schedulng algorthms are not prorty-based and ncur much hgher context-swtch overhead [11]. Recently a number of wors have been done on the semparttoned schedulng, whch can exceed the maxmum utlzaton bound 50% of the parttoned schedulng. In semparttoned schedulng, most tass are statcally assgned to one fxed processor as n parttoned schedulng, whle a Ths wor was partally sponsored by CoDeR-MP, UPMARC, and NSF of Chna under Grant No and Correspondng author: Wang Y, y@t.uu.se. few number of tass are splt nto several subtass, whch are assgned to dfferent processors. A recent wor [18] has shown that the worst-case utlzaton bound of semparttoned fxed-prorty schedulng can acheve 65%, whch s stll lower than 69.3% (the worst-case value of Θ(N) when N s ncreasng to the nfnty). Ths gap s even larger wth a smaller N. In ths paper, we propose a new fxed-prorty schedulng algorthm for multprocessor systems based on semparttoned schedulng, whose utlzaton bound s Θ(N). The algorthm uses RMS on each processor, and has the same tas splttng overhead as n prevous wors [18], [15], [16]. We frst propose a sem-parttoned fxed-prorty schedulng algorthm, whose utlzaton bound s Θ(N) for a class of tas sets n whch the utlzaton of each tas s no larger than Θ(N)/(1 + Θ(N)). Ths algorthm assgns tass n decreasng perod order, and always selects the processor wth the least worload assgned so far among all processors, to assgn the next tas. Then we remove the constrant on the utlzaton of each tas, by ntroducng an extra tas pre-assgnng mechansm; the algorthm can acheve the utlzaton bound of Θ(N) for any tas set. The rest of the paper s structured as follows: Secton II revews the pror wor on sem-parttoned schedulng; Secton III ntroduces the notatons and the basc concept of sem-parttoned schedulng. The frst and second proposed algorthms, as well as ther worst-case utlzaton bound propertes, are presented n Secton IV and V respectvely. Fnally, the concluson s made n Secton VI. II. PRIOR WORK Sem-parttoned schedulng has been studed wth both EDF schedulng [1], [8], [5], [6], [13], [14], [17] and fxedprorty schedulng [15], [16], [18]. The frst sem-parttoned schedulng algorthm s EDFfm [1] for soft real-tme systems based on EDF schedulng. Andersson et al. proposed EKG [8] for hard real-tme systems, n whch splt tass are forced to executed n certan tme slots. Later EKG was extended to sporadc and arbtrary deadlne tas systems [5] [6] wth the smlar dea. Kato et al. proposed EDDHP and EDDP [13] [14] n whch splt tass are scheduled based on prorty rather than tme slots. The worst-case utlzaton bound of EDDP s 65%. Later Kato et

2 al. proposed EDF-WM, whch can sgnfcantly reduce the context swtch overhead aganst prevous wor. There are relatvely fewer wors on the fxed-prorty schedulng sde. Kato et al. proposed RMDP [15] and DMPM [16], both wth the worst-case utlzaton bound of 50%. whch s the same as the parttoned schedulng wthout tas splttng. Recently, Lashmanan et al. [18] proposed the algorthm PDMS HPTS DS, whch can acheve the worstcase utlzaton bound of 65%, and can acheve the bound 69.3% for a specal type of tas sets only contanng lght tass. They also conducted case studes on an Intel Core Duo processor to characterze the practcal overhead of tas-splttng, and showed that the cache overheads due to tas-splttng can be expected to be neglgble on mult-core platforms. III. BASIC CONCEPTS We frst ntroduce the processor platform and tas model. The multprocessor platform conssts of M dentcal processors {P 1, P,...P M }. A tas set τ = {τ 1, τ,..., τ N } conssts of N ndependent tass. Each tas τ s a -tuple C, T, where C s the worst-case executon tme, T s the mnmum nter-release separaton (also called perod). T s also τ s relatve deadlne. Tass n τ are sorted n non-decreasng perod order,.e., j > T j T. Snce our proposed algorthms use ratemonotonc schedulng (RMS) as the schedulng algorthm on each processor, we can use the tas ndces to represent the tas prortes,.e., τ has hgher prorty than τ j f and only f < j. The utlzaton of each tas τ s defned as U = C /T. We recall the classcal result of Lu and Layland [19]: On a sngle-processor system, each tas set τ wth U N( 1 N 1) τ τ s schedulable usng rate-monotonc schedulng (RMS). The utlzaton bound of our proposed sem-parttoned schedulng algorthm s bult upon ths result. In the remander of ths paper, we use Θ(N) to denote the above utlzaton bound for N tass: Θ(N) = N( 1 N 1) (1) We further defne the utlzaton of a tas set τ n multprocessor schedulng on M processors as U(τ) = τ τ U /M () For smplcty of presentng our algorthms, we assume each tas τ τ has utlzaton U Θ(N). Note that ths assumpton does not nvaldate our results on tas sets contanng tass wth utlzaton hgher than Θ(N): If n a tas set wth U(τ) Θ(N) there are tass wth a hgher (ndvdual) utlzaton than Θ(N), we can just let them run 1 τ 1 r r r+r 1 τ 3 τ 3 r R 1 R T R 1 r+r 1 +R Fgure 1. T -R 1 -R Subtass each exclusvely on an own processor. The remanng tas set on the remanng processors stll has a utlzaton of at most Θ(N). If we are able to show ts schedulablty, then together ths results n the desred bound Θ(N) for the full tas set. A sem-parttoned schedulng algorthm conssts of two parts: the parttonng algorthm, whch determnes how to splt and assgn each tas (or rather each of ts parts) to a fxed processor, and the schedulng algorthm, whch determnes how to schedule the tass assgned to each processor. Wth the parttonng algorthm, most tass are assgned to a processor and only execute on ths processor at run tme. We call these tass non-splt tass. Other tass are called splt tass, whch are splt nto several subtass. Each subtas of splt tas τ s assgned to (thereby executes on) a dfferent processor, and the sum of the executon tme of all subtass equals C. For example, n Fgure 1 the tas τ s splt nto three subtass τ 1, τ and τ 3, executng on processor P 1, P and P 3, respectvely. The subtass of a tas need to be synchronzed to execute correctly. For example, n Fgure 1, τ can not start executon untl τ 1 s fnshed. Ths equals deferrng the actual ready tme of τ by up to R1 (relatve to τ s orgnal release tme), where R 1 s the worst-case response tme of τ 1. One can regard ths as shortenng the actual relatve deadlne of τ by up to R 1. Smlarly, the actual ready tme of τ 3 s deferred by up to R 1 + R, and τ 3 s actual relatve deadlne s shortened by up to R 1 + R. We use τ to denote the th subtas of a splt tas τ, and defne τ s synthetc deadlne as = T R l (3) l [1, 1] Thus, we represent each subtas τ by a 3-tuple c, T,, n whch c s the executon tme of τ, T s the orgnal perod, s the synthetc deadlne. For consstency, each non-splt tas τ can be represented by a sngle subtas τ 1 wth c 1 = C and 1 = T. The normal utlzaton of a subtas τ s U = c /T, and we defne another new metrc, the synthetc utlzaton d

3 V, to descrbe τ s worload wth ts synthetc deadlne: V = c / (4) We call the last subtas of τ ts tal subtas, denoted by τ t and other subtass ts body subtass, as shown n Fgure 1. We use τ bj to denote the j th body subtas. We use τ P q to denote that τ s assgned to processor P q, and say that P q s the host processor of τ. A tas set τ s schedulable under a sem-parttoned schedulng algorthm A, f after assgnng tass to processors by A s parttonng algorthm, each tas τ τ can meet ts deadlne under A s schedulng algorthm. IV. THE FIRST ALGORITHM SPA1 A sgnfcant dfference between SPA1 and the algorthms n prevous wor s that SPA1 employs a worst-ft parttonng, whle all prevous algorthms employ a frst-ft parttonng [18], [15], [16]. The basc procedure of frst-ft parttonng s as follows: one selects a processor, and assgn tass to ths processor as much as possble to fll ts capacty, then pc the next processor and repeat the procedure. In contrast, the worst-ft parttonng always selects the processor wth the mnmal total utlzaton of tass that have been assgned to t, so the occuped capactes of all processors are ncreased roughly n turn. The reason for us to prefer worst-ft parttonng s ntutvely explaned as follows. A subtas τ s actual deadlne ( ) s shorter than τ s orgnal deadlne T, and the sum of the synthetc utlzatons of all τ s subtass s larger than τ s orgnal utlzaton U, whch s the ey dffculty for sem-parttoned schedulng to acheve the same utlzaton bound as on sngle-processors. Wth worst-ft parttonng, the occuped capacty of all processors are ncreased n turn, and tas splttng only occurs when the capacty of a processor s completely flled. Then, f one parttons all tass n ncreasng prorty order, the splt tass n worstft parttonng wll generally have relatvely hgh prorty levels on each processor. Ths s good for the schedulablty of the tas set, snce the tass wth hgh prortes usually have better chance to be schedulable, so they can tolerate the shortened deadlnes better. Consder an extreme scenaro: f one can mae sure that all splt tass subtass have the hghest prorty on ther host processors, then there s no need to consder the shortened deadlnes of these subtass, snce, beng of the hghest prorty level on each processor, they are schedulable anyway. Thus, as long as the splt tass wth shorten deadlnes do not cause any problem, Lu and Layland s utlzaton bound can be easly acheved. The phlosophy behnd our proposed algorthms s mang the splt subtass get as hgh prorty as possble on each processor. In contrast, wth the frst-ft parttonng, a splt subtas may get qute low prorty on ts host processors 1. For nstance, wth the algorthm n [18] that acheves the utlzaton bound of 65%, n the worst case the second subtas of a splt tas wll always get the lowest prorty on ts host processor. As wll be seen later n ths secton, SPA1 does not completely solve the problem. More precsely, SPA1 s restrcted to a class of lght tas sets, n whch the utlzaton of each tas s no larger than Θ(N)/(1+Θ(N)). Intutvely, ths s because f a tas s utlzaton s very large, ts tal subtas mght stll get a relatvely low prorty on ts host processor, even usng worst-ft parttonng. (We wll solve ths problem wth SPA n Secton V.) In the followng, we wll ntroduce SPA1 as well as ts utlzaton bound property. The remanng part of ths secton s structured as follows: we frst present the parttonng algorthm of SPA1, and show that any tas set τ satsfyng U(τ) Θ(N) can be successfully parttoned by SPA1. Then we ntroduce how the tass assgned to each processor are scheduled. Next, we prove that f a lght tas set s successfully parttoned by SPA1, then all tass can meet ther deadlnes under the schedulng algorthm of SPA1. Together, ths mples that any lght tas set wth U(τ) Θ(N) s schedulable by SPA1, and fnally ndcates the utlzaton bound of SPA1 s Θ(N) for lght tas sets. 1: f U(τ) > Θ(N) then abort : UQ := [τn 1, τ N 1 1,..., τ 1 1 ] 3: Ψ[1...M] := all zeros 4: whle UQ do 5: P q := the processor wth the mnmal Ψ 6: τ := pop front(uq) 7: f (U + Ψ[q] Θ(N)) then 8: τ P q 9: Ψ[q] := Ψ[q] + U 10: else 11: splt τ nto two parts τ and τ +1 such that U + Ψ[q] = Θ(N) 1: τ P q 13: Ψ[q] := Θ(N) 14: push front(τ +1, UQ) 15: end f 16: end whle Algorthm 1: The parttonng algorthm of SPA1. A. SPA1: Parttonng and Schedulng The parttonng algorthm of SPA1 s very smple, whch can be brefly descrbed as follows: 1 Under the algorthms n [16], a splt subtas s prorty s artfcally advanced to the hghest level on ts host processor, whch breas down the RMS prorty order and thereby leads to a lower utlzaton bound.

4 We assgn tass n ncreasng prorty order, and always select the processor on whch the total utlzaton of tass have been assgned so far s mnmal among all the processors. When a tas (subtas) can not be assgned entrely to the current selected processor, we splt t nto two parts and assgn the frst part such that the total utlzaton of the current selected processor s Θ(N), and assgn the second part to the next selected processor. The precse descrpton of the parttonng algorthm s n Algorthm 1. U Q s the lst accommodatng unassgned tass, sorted n ncreasng prorty order. U Q s ntalzed by {τn 1, τ N 1 1,..., τ 1 1 }, n whch each element τ 1 = c 1 = C, T, 1 = T s the ntal subtas form of tas τ. Each element Ψ[q] n the array Ψ[1...M] denotes the sum of the utlzaton of tass that have been assgned to processor P q. The wor flow of SPA1 s as follows. In each loop teraton, we pc the tas at the front of UQ, denoted by τ, whch has the lowest prorty among all unassgned tass. We try to assgn τ to the processor P q, whch has the mnmal Ψ[q] among all elements n Ψ[1...M]. If U + Ψ[q] Θ(N) then we can assgn the entre τ to P q, snce there s enough capacty avalable on P q. Otherwse, we splt τ nto two subtass τ and τ +1, such that U + Ψ[q] = Θ(N) (Note that wth U = c /T we denote the utlzaton of subtas τ.) We further set Ψ[q] := Θ(N), whch means ths processor P q s full and we wll not assgn any more tass to P q. Then we nsert τ +1 bac to the front of UQ, to assgn t n the next loop teraton. We contnue ths procedure untl all tass have been assgned. It s easy to see that all tas sets below the desred utlzaton bound can be successfully parttoned by SPA1: Lemma 1. Any tas set wth U(τ) Θ(N) (5) can be successfully parttoned to M processors wth SPA1. Note that there s no schedulablty guarantee n the parttonng algorthm. It wll be proved n next subsecton. After the tass are assgned (and possbly splt) to the processors by the parttonng algorthm of SPA1, they wll be scheduled usng RMS on each processor locally,.e., wth ther orgnal prortes. The subtass of a splt tas respect ther precedence relatons,.e., a splt subtas τ s ready for executon when ts precedng subtas τ 1 on some other processor has fnshed. release of τ ready for τ release of τ ready for τ c j j< T c j Fgure. Each subtas τ can be vewed as an ndependent tas wth perod of T and deadlne of. B. Schedulablty We frst show an mportant property of SPA1: Lemma. After parttonng accordng to SPA1, each body subtas has the hghest prorty on ts host processor. Proof: In the parttonng algorthm of SPA1, tas splttng only occurs when a processor s full. Thus, after a body tas was assgned to a processor, there wll be no more tass assgned to t. Further, the tass are parttoned n ncreasng prorty order, so all tass assgned to the processor before have lower prorty. By Lemma, we further now that the response tme of each body subtas equals ts executon tme, so the synthetc deadlne t of each tal subtas τ t s calculated as follows: t = T j [1,B] j< c bj = T (C c t ) (6) So we can vew the schedulng n SPA1 on each processor wthout consderng the synchronzaton between the subtass of a splt tas, and just regard every splt subtas τ as an ndependent tas wth perod T and a shorter relatve deadlne calculated by Equaton (6), as shown n Fgure. In the followng we prove the schedulablty of non-splt tass, body subtass and tal subtass, respectvely. 1) Non-splt Tass: Lemma 3. If tas set τ wth U(τ) Θ(N) s parttoned by SPA1, then any non-splt tas of τ can meet ts deadlne. Proof: The tass on each processor are scheduled by RMS, and the sum of the utlzaton of all tass on a processor s no larger than Θ(N). Further, the deadlnes of the non-splt tass are unchanged and therefore stll equal ther perods. Thus, each non-splt tas s schedulable. Note that although the synthetc deadlnes of other subtass are shorter than ther orgnal perods, ths does not affect the schedulablty of the non-splt tass, snce only the perods of these subtass are relevant to the schedulablty of the non-splt tass. ) Body Subtass: Lemma 4. If tas set τ wth U(τ) Θ(N) s parttoned by SPA1, then any body subtas of τ can meet ts deadlne. Proof: The body subtass have the hghest prortes on ther host processors and wll therefore always meet

5 U b1 U b U bb Y t U t hgh prorty Θ(N) b1 X Xb XbB Xt P b1 P b P bb P t low prorty (a) Γ (b) Γ Fgure 3. Illustraton of X b j, X t and Y t Fgure 4. Illustraton of Γ ther deadlnes. (Ths holds even though the deadlnes were shortened because of the tas splttng). 3) Tal Subtass: Now we prove the schedulablty for an arbtrary tal subtas τ t, durng whch we only focus on τ t, but do not consder whether other tal subtass are schedulable or not. Snce the same reasonng can be appled to every tal subtas, the proofs guarantee that all tal subtass are schedulable. Suppose tas τ s splt nto B body subtass and one tal subtas. Recall that we use τ bj, j [1, B] to denote the j th body subtas of τ, and τ t to denote τ s tal subtas. U bj = c bj /T and U t = c t /T denotes τ bj s and τ t s orgnal utlzaton respectvely. Addtonally, we use the followng notatons (cf. Fgure 3): For each body subtas τ bj, let X bj denote the sum of the utlzatons of all the tass τ assgned to P bj wth lower prorty than τ bj. For the tal subtas τ t, let Xt denote the sum of the utlzatons of all the tass assgned to P t wth lower prorty than τ t. For the tal subtas τ t, let Y t denote the sum of the utlzatons of all the tass assgned to P t wth hgher prorty than τ t. We can use these now for the schedulablty of the tal subtass: Lemma 5. Suppose a tal subtas τ t s assgned to processor P t. If τ t satsfes then τ t Y t T / t + V t Θ(N), (7) can meet ts deadlne. Proof: The proof dea s as follows: We consder the set Γ consstng of τ t and all tass wth hgher prorty than τ t on the same processor,.e., the tass contrbutng to Y t. For ths set, we construct a new tas set Γ, n whch the tass perods that are larger than t are all reduced to t. The man dea s to frst show that the counterpart of τ t s schedulable wth ths new set Γ by RMS because of the utlzaton bound, and then to prove ths mples the schedulablty of τ t n the orgnal set Γ. In partcular, let P t be the processor to whch τ t s assgned. We defne Γ as follows: Γ = {τ h τ h P t h } (8) We now gve the constructon of Γ: For each tas τh Γ, we have a counterpart τ h n Γ. The only dfference s that we possbly reduce the perods: { c h = T h, f T h t c h, Th = t, f T h > t We also eep the same prorty order of tass n Γ as ther counterparts n Γ, whch s stll a rate-monotonc orderng. Fgure 4 llustrates the constructon. In Fgure 4(a), Γ contans three tass. τ 1 has a perod that s smaller than t, and τ has a larger one. Further, τ t s contaned n Γ. Accordng to the constructon, Γ n Fgure 4(b) has also three tass τ 1, τ and τ t, where only the perods of τ and τ t are reduced to t. Now we show the schedulablty of τ t n Γ. We do ths by showng the suffcent upper bound of Θ(N) on the total utlzaton of Γ. U( Γ) = c h/ T h = c h/ T h + V (9) τh Γ τh Γ\{τ t} We now do a case dstncton for tass τ h Γ, accordng to whether ther perods were reduced or not. If T h t, we have T h = T h. Snce T > t, we have: c h/ T h = c h/t h = U h < U h T / t If T h > t, we have T h = t. Because of the prorty ordered by perods, we have T h T. Thus: c h/ T h = c h/ t c h/t h T / t = U h T / t Both cases lead to c h / T h Uh T / t, so we can apply ths to (9) from above: U( Γ) (10) τ h Γ\{τ t } U h T / t + V

6 Snce Y t = τh Γ\{τ t} U h, we have: U( Γ) Y t T / t + V t Fnally, by the assumpton from Condton (7) we now that the rght-hand sde s at most Θ(N), and thus U( Γ) Θ(N). Therefore, τ s schedulable. Note that n Γ there could exst other tal subtass whose deadlnes are shorter than ther perods. However, ths does not nvaldate that the condton U( Γ) Θ(N) s suffcent to guarantee the schedulablty of τ t under RMS. Now we need to see that ths mples the schedulablty of τ t. Recall that the only dfference between Γ and Γ s that the perod of a tas n Γ s possbly larger than ts counterpart n Γ. So the nterference τ t suffered from the hgher-prorty tass n Γ, s no larger than the nterference τ t suffered n Γ, and snce the deadlnes of τ t and τ t are the same, we now the schedulablty of τ t mples the schedulablty of τ t İt remans to show that Condton (7) holds, whch was the assumpton for ths lemma and thus a suffcent condton for tal subtass to be schedulable. As n the ntroducton of ths secton, ths condton does not hold n general for SPA1, but only for certan lght tas sets: Defnton 1. A tas τ s a lght tas f U Θ(N) 1 + Θ(N). Otherwse, τ s a heavy tas. A tas set τ s a lght tas sets f all tass n τ are lght tass. Lemma 6. Suppose a tal subtas τ t s assgned to processor P t. If τ s a lght tas, we have Y t T / t + V t Θ(N). Proof: We wll frst derve a general upper bound on Y t based on the propertes of X bj, X t and the subtass utlzatons. Based on ths, we derve the bound we want to show, usng the assumpton that τ s a lght tas. For dervng the upper bound on Y t, we note that as soon as a tas s splt nto a body subtas and a rest, the processor hostng ths new body subtas s full,.e., ts utlzaton s Θ(N). Further, each body subtas has by constructon the hghest prorty on ts host processor, so we have: j [1, B] : U bj + X bj = Θ(N) We sum over all B of these equatons, and get: U bj + X bj = B Θ(N) (11) j [1,B] j [1,B] Now we consder the processor contanng τ t, denoted by P t. Its total utlzaton s X t +U t +Y t and s at most Θ(N),.e., X t + U t + Y t Θ(N). We combne ths wth (11) and get: j [1,B] U bj j [1,B] Xbj Y t + U t X t (1) B B In order to smplfy ths, we recall that durng the parttonng phase, we always select the processor wth the smallest total utlzaton of tass that have been assgned to t so far. (Recall lne 5 n Algorthm 1). Ths mples X bj X t for all subtass τ bj. Thus, the sum over all X bj s bounded by B X t and we can cancel out both terms n (1): j [1,B] U bj Y t U t B Another smplfcaton s possble usng that B 1 and that τ s utlzaton U s the sum of the utlzatons of all of ts subtass,.e., j [1,B] U bj = U U t: Y t U U t We are now done wth the frst part,.e., dervng an upper bound for Y t. Ths can easly be transformed nto an upper bound on the term we are nterested n: Y t T t + V t (U U t ) T t + V t (13) For the rest of the proof, we try to bound the rght-hand sde from above by Θ(N) whch wll complete the proof. The ey s to brng t nto a form that s sutable to use the assumpton that τ s a lght tas. As a frst step, we use that the synthetc deadlne of τ t s the perod T reduced by the total computaton tme of τ s body subtass,.e., t = T (C c t ), cf. Equaton (6). Further, we use the defntons U = C /T, U t = c t /T and V t = c t / t to derve: (U U t ) T t + V t C c t = T (C c t ) Snce c t > 0, we can fnd a smple upper bound of the rght-hand sde: C c t T (C c t ) = Snce τ s a lght tas, we have T T (C c t ) 1 < U Θ(N) 1 + Θ(N) T T C 1 and by applyng U = C /T to the above, we can obtan T 1 Θ(N) T C Thus, we have establshed that Θ(N) s an upper bound of Y t T + V t t wth whch we started n (13). From Lemmas 5 and 6 t follows drectly the desred property: Lemma 7. If tas set τ wth U(τ) Θ(N) s parttoned by SPA1, then any tal subtas of a lght tas of τ can meet ts deadlne.

7 Table I AN EXAMPLE TASK SET 3 b t 5 Fgure 5. The tal subtas of a tas wth large utlzaton may have a low prorty level C. Utlzaton Bound By Lemma 1 we now that a tas set τ can be successfully parttoned by the parttonng algorthm of SPA1 f U(τ) s no larger than Θ(N). If τ has been successfully parttoned, by Lemma 3 and 4 we now that all the non-splt tas and body subtass are schedulable. By Lemma 7 we now a tal subtas τ s also schedulable f τ s a lght tas. Snce, n general, t s a pror unnown whch tass wll be splt, we pose ths constrant of beng lght to all tass n τ to have a suffcent schedulablty test condton: Theorem 1. Let τ be a tas set only contanng lght tass. τ s schedulable wth SPA1 on M processors f U(τ) Θ(N) (14) In other words, the utlzaton bound of SPA1 s Θ(N) for tas sets only contanng tass wth utlzaton no larger than Θ(N)/(1 + Θ(N)). Θ(N) s a decreasng functon wth respect to N, whch means the utlzaton bound s hgher for tas sets wth fewer tass. We use N to denote the maxmal number of tass (subtass) assgned to each processor, so Θ(N ), whch s strctly larger than Θ(N), also serves as the utlzaton bound of each processor. Therefore we can use Θ(N ) to replace Θ(N) n the dervaton procedure above, and get that the utlzaton bound of SPA1 s Θ(N ) for tas sets only contanng tass wth utlzaton no larger than Θ(N )/(1 + Θ(N )). V. THE SECOND ALGORITHM SPA In ths secton we ntroduce our second sem-parttoned fxed-prorty schedulng algorthm SPA, whch has the utlzaton bound of Θ(N) for tas sets wthout any constrant. As dscussed n the begnnng of Secton IV, the ey pont for our algorthms to acheve hgh utlzaton bounds s to mae each splt tas get a prorty as hgh as possble on ts host processor. Wth SPA1, the tal subtas of a tas wth very large utlzaton could have a relatvely low prorty on ts host processor, as the example n Fgure 5 llustrates. Ths s why the utlzaton bound of SPA1 s not applcable to tas sets contanng heavy tass. Tas C T Heavy Tas? Prorty τ yes hghest τ no mddle τ no lowest To solve ths problem, we propose the second semparttoned algorthm SPA n ths secton. The man dea of SPA s to pre-assgn each heavy tas whose tal subtas mght get a low prorty, before parttonng other tass, therefore these heavy tass wll not be splt. Note that f one smply pre-assgns all heavy tass, t s stll possble for some tal subtas to get a low prorty level on ts host processor. Consder the tas set n Table I wth processors, and for smplcty we assume Θ(N) = 0.8, and Θ(N)/(1 + Θ(N)) = 4/9. If we pre-assgn the heavy tas τ 1 to processor P 1, then assgn τ and τ 3 by the parttonng algorthm of SPA1, the tas parttonng loos as follows: 1) τ 1 P 1, ) τ 3 P, 3) τ can not be entrely assgned to P, so t s splt nto two subtass τ 1 = 3.75, 10, 10 and τ = 0.5, 10, 6.5, and τ 1 P, 4) τ P 1. Then the tass on each processor are scheduled by RMS. We can see that the tal subtas τ has the lowest prorty on P 1 and wll mss ts deadlne due to the hgher prorty tas τ 1. However, f we do not pre-assgn τ 1 and just do the parttonng wth SPA1, ths tas set s schedulable. To overcome ths problem, a more sophstcated preassgnng mechansm s employed n our second algorthm SPA. Intutvely, SPA pre-assgns exactly those heavy tass for whch pre-assgnng them wll not cause any tal subtas to mss deadlne. Ths s checed usng a smple test. Those heavy tass that don t satsfy ths test wll be assgned (and possbly splt) later together wth the lght tass. The ey for ths to wor s, that for these heavy tass, we can use the property of falng the test n order to show that ther tal subtass wll not mss the deadlnes ether. A. SPA: Parttonng and Schedulng We frst ntroduce some notatons. If a heavy tas τ s pre-assgned to a processor P q n SPA, we call τ as a pre-assgned tas, otherwse a normal tas, and call P q as a pre-assgned processor, otherwse a normal processor. The parttonng algorthm of SPA contans three steps: 1) We frst pre-assgn the heavy tass that satsfy a partcular condton to one processor each. ) We do tas parttonng wth the remanng (.e. normal) tass and remanng (.e. normal) processors usng SPA1 untl all the normal processors are full. 3) The remanng tass are assgned to the pre-assgned processors; the assgnment selects one processor to

8 1: f U(τ) > Θ(N) then abort : P Q := [P 1, P,..., P M ] 3: P Q pre := 4: UQ := 5: Ψ[1...M] := all zeros 6: for := 1 to N do 7: f τ s heavy j> U j ( P Q 1) Θ(N) then 8: P q := pop front(p Q) 9: Pre-assgn τ to P q 10: push front(p q, P Q pre) 11: Ψ[q] := Ψ[q] + U 1: else 13: push front(τ 1, UQ) 14: end f 15: end for 16: whle UQ do 17: τ := pop front(uq) 18: f P q P Q : Ψ[q] Θ(N) then 19: P q := the element n P Q wth the mnmal Ψ 0: else 1: P q := pop front(p Q pre) : end f 3: f U + Ψ[q] Θ(N) then 4: τ Pq 5: Ψ[q] := Ψ[q] + U 6: f P q came from P Q then 7: push front(p q, P Q pre) 8: end f 9: else 30: splt τ nto two parts τ and τ +1 such that U + Ψ[q] = Θ(N) 31: τ Pq 3: Ψ[q] = Θ(N) 33: push front(τ +1, UQ) 34: end f 35: end whle Algorthm : The parttonng algorthm of SPA. assgn as many tass as possble, untl t becomes full, then select the next processor. The precse descrpton of the parttonng algorthm of SPA s shown n Algorthm. We frst ntroduce the data structures used n the algorthm: P Q s the lst of all processors. It s ntally [P 1, P,..., P M ] and processors are always taen out and put bac n the front. P Q pre s the lst to accommodate pre-assgned processors, ntally empty. UQ s the lst to accommodate the unassgned tass after Step 1). Intally t s empty, and durng Step 1), each tas τ that s determned not to be pre-assgned wll be put nto UQ (already n ts subtas form τ 1 ). Ψ[1...M] s an array, whch has the same meanng as n SPA1: each element Ψ[q] n the array Ψ[1...M] denotes the sum of the utlzaton of tass that have been assgned to processor P q. In Step 1) (lnes 6 to 15), each tas τ n τ s vsted n ncreasng ndex order,.e., decreasng prorty order. If τ s a heavy tas, we evaluate the followng condton (lne 7): U j ( P Q 1) Θ(N) (15) j> n whch P Q s the number of processors left n P Q so far. A heavy tas τ s determned to be pre-assgned to a processor f ths condton s satsfed. The ntuton for ths s: If we pre-assgn ths tas τ, then there s enough space on the remanng processors to accommodate all remanng lower prorty tass. That way, no lower prorty tal subtas wll end up on the processor whch we assgn τ to. Step ) and 3) are both n the whle loop of lne In Step ), the remanng tass (whch are now n UQ) are assgned to normal processors (the ones n P Q). Only as soon as all processors n P Q are full, the algorthm enters Step 3), n whch tass are assgned to processors n P Q pre (decson n lnes 18 to ). The operaton of assgnng a tas τ (lnes 3 to 34) s bascally the same as n SPA1. If τ can be entrely assgned to P q wthout tas splttng, then τ P q and Ψ[q] s updated (lnes 4 to 8). If P q s a pre-assgned processor, P q s put bac to the front of P Q pre (lnes 6 to 8), so that t wll be selected agan n the next loop teraton, otherwse no puttng bac operaton s needed snce we never tae out elements from P Q, but select the proper one n t (lne 19). If τ can not be assgned to P q entrely, τ s splt nto a new τ and another subtas τ +1, such that P q becomes full after the new τ beng assgned to t, and then we put τ +1 bac to UQ (see lnes 9 to 33). Note that there s an mportant dfference between assgnng tass to normal processors and to pre-assgned processors. When tass are assgned to normal processors, the algorthm always selects the processor wth the mnmal Ψ (the same as n SPA1). In the contrast, when tass are assgned to pre-assgned processors, always the processor at the front of P Q pre s selected,.e., we assgn as many tass as possble to the processor n P Q pre whose preassgned tas has the lowest prorty, untl t s full. As wll be seen later n the schedulablty proof, ths partcular order of selectng pre-assgned processors, together wth the evaluaton of Condton (15), s the ey to guarantee the schedulablty of heavy tass. It s easy to see that any tas set below the desred utlzaton bound can be successfully parttoned by SPA: Lemma 8. Any tas set wth U(τ) Θ(N) can be successfully parttoned to M processors wth SPA. After descrbng the parttonng part of SPA, we also need to descrbe the schedulng part. It s the same as SPA1: on each processor the tass are scheduled by RMS, respectng the precedence relatons between the subtass of a splt tas,.e., a subtas s ready for executon as soon

9 as the executon of ts precedng subtas has been fnshed. Note that under SPA, each body subtas s also wth the hghest prorty on ts host processor (wll be proved later n Lemma 11), whch s the same as n SPA1. So we can vew the schedulng on each processor as the RMS wth a set of ndependent tass, n whch each subtas s deadlne s shortened by the sum of the executon tme of all ts precedng subtass. B. Propertes In the followng, we present some propertes of SPA, that wll be used to prove the schedulablty of tas sets that can be parttoned usng SPA. The frst property follows drectly from SPA s parttonng algorthm. Lemma 9. Let τ be a heavy tas, and there are η preassgned tass wth hgher prorty than τ. Then we now If τ s a pre-assgned tas, t satsfes U j (M η 1) Θ(N) (16) j> If τ s not a pre-assgned tas, t satsfes U j > (M η 1) Θ(N) (17) j> Lemma 10. Each pre-assgned tas has the lowest prorty on ts host processor. Proof: Wthout loss of generalty, We sort all processors n a lst Q as follows: we frst sort all pre-assgned processors n Q, n decreasng prorty order of the pre-assgned tass on them; then the normal processors follow n Q n an arbtrary order. We use P x to denote the x th processor n Q. Suppose τ s a heavy tas pre-assgned to P q. τ s a pre-assgned tas, and the number of pre-assgned tas wth hgher prorty than τ s q 1, so by Lemma 9 we now the followng condton s satsfed: U j (M q) Θ(N) (18) j> In the parttonng algorthm of SPA, normal tass are assgned to pre-assgned processors only when all normal processors are full, and the pre-assgned processors are selected n ncreasng prorty order of the pre-assgned tass on them, so we now only when the processors P q+1...p M are all full, normal tass can be assgned to processor P q. The total capacty of processors P q+1...p M are (M q) Θ(N) (n our algorthms a processor s full as soon as the total utlzaton on t s Θ(N)), and by (18), we now when we start to assgn tass to P q, the tass wth lower prorty than τ all have been assgned to processors P q+1...p M, so all normal tass (subtass) assgned to P q have hgher prortes than τ. Lemma 11. Each body subtas has the hghest prorty on ts host processor. Proof: Snce all normal tass are assgned n ncreasng prorty order, and a tas s splt only when the processor s full, we now a body subtas has hgher prorty than all normal tass on ts host processor. If ths body subtas s assgned to a pre-assgned processor, by Lemma 10 we now ts prorty s also hgher than the pre-assgned tas on ths processor. So a body subtas has the hghest prorty on ts host processor. C. Schedulablty Now we wll prove the schedulablty of a tas set τ whch has been successfully parttoned by SPA. To ths end, we wll prove the schedulablty of non-splt tass (Lemma 1), body subtass (Lemma 13) and tal subtass (Lemma 14) respectvely. Lemma 1. If tas set τ wth U(τ) Θ(N) s parttoned by SPA, then any non-splt tas can meet ts deadlne. The proof s the same as for SPA1 (Lemma 3). Lemma 13. If tas set τ wth U(τ) Θ(N) s parttoned by SPA, then any body subtas can meet ts deadlne. Proof: By Lemma 11 we now that under SPA a body subtas has the hghest prorty on ts host processor, so t wll meet ts deadlne anyway. Lemma 14. If tas set τ wth U(τ) Θ(N) s parttoned by SPA, then any tal subtas can meet ts deadlne. Proof: For space reason, we only brefly descrbe the proof dea. The detaled proof s gven n the full verson of ths paper [1]. We dstngush three cases: 1) τ s lght, and P t s a normal processor, ) τ s lght, and P t s a pre-assgned processor, 3) τ s heavy. Case 1) can be proved n the same way as Lemma 6 for SPA1, snce both the parttonng and schedulng algorthm of SPA on normal processors are the same as SPA1. To prove Case ) and 3), we notce that to mae a tal subtas τ t schedulable, we should mae the total utlzaton of tass nterferng wth τ t as small as possble. In other words, we should let the total utlzaton of tass on P t wth lower prorty than τ t to be as hgh as possble. Wth Case ), the pre-assgned tas on P t s heavy (wth hgh utlzaton), and has lower prorty than τ t (by Lemma 10), therefore the total utlzaton of tass wth lower prorty on P t s hgh enough to prevent τ t from mssng deadlne. Wth Case 3), by Lemma 9 we now that f a heavy tas was not preassgned under the SPA s parttonng algorthm, t satsfes Condton (17), whch guarantees the total utlzaton of all tass wth lower prorty than τ s hgh enough to prevent from mssng deadlne. τ t

10 D. Utlzaton Bound Now we now that any tas set τ wth U(τ) Θ(N) can be successfully parttoned on M processors by SPA (Lemma 8). We also now that f τ s successfully parttoned, all the non-splt tass (Lemma 1), body subtass (Lemma 13) and tal subtass (Lemma 14) can meet ther deadlnes under SPA s schedulng algorthm. Therefore we have the followng theorem: Theorem. τ s schedulable by SPA on M processors f U(τ) Θ(N) So Θ(N) s SPA s utlzaton bound for any tas set. For the same reason as presented at the end of Secton IV-C, we can use Θ(N ), the maxmal number of tass (subtass) assgned to each processor, to replace Θ(N) n Theorem. E. Tas Splttng Overhead Wth the algorthms proposed n ths paper, a tas could be splt nto more than two subtass. However, snce the tas splttng only occurs when a processor s full, for any tas set that s schedulable by SPA, the number of tas splttng s at most M 1, whch s the same as n prevous semparttoned fxed-prorty schedulng algorthms [18], [15], [16], and as shown n the case study conducted n [18], ths overhead can be expected neglgble on mult-core platforms. VI. CONCLUSIONS AND FUTURE WORK In ths paper, we have developed a sem-parttoned fxedprorty schedulng algorthm for multprocessor systems, wth the well-nown Lu and Layland s utlzaton bound N( 1 N 1) for RMS on sngle processors. The algorthm enjoys the followng property. If the utlzaton bound s used for the schedulablty test, and a tas set s determned schedulable by fxed-prorty schedulng on a sngle processor of speed M, t s also schedulable by our algorthm on M processors of speed 1 (under the assumpton that each tas s executon tme on the processors of speed 1 s stll smaller than ts deadlne). Note that the utlzaton bound test s only suffcent but not necessary. As future wor, we wll challenge the problem of constructng algorthms holdng the same property wth respects to the exact schedulablty analyss. REFERENCES [1] J. Anderson, V. Bud, and U.C. Dev. An edf-based schedulng algorthm for multprocessor soft real-tme systems. In ECRTS, 005. [] J. Anderson and A. Srnvasan. Mxed pfar/erfar schedulng of asynchronous perodc tass. In Journal of Computer and System Scences, 004. [3] B. Andersson. Global statc prorty preemptve multprocessor schedulng wth utlzaton bound 38%. In OPODIS, 008. [4] B. Andersson, S. Baruah, and J. Jonsson. Statc prorty schedulng on multprocessors. In RTSS, 001. [5] B. Andersson and K. Bletsas. Sporadc multprocessor schedulng wth few preemptons. In ECRTS, 008. [6] B. Andersson, K. Bletsas, and S. Baruah. Schedulng arbtrary-deadlne sporadc tas systems multprocessors. In RTSS, 008. [7] B. Andersson and J. Jonsson. The utlzaton bounds of parttoned and pfar statc-prorty schedulng on multprocessors are 50%. In ECRTS, 003. [8] B. Andersson and E. Tovar. Multprocessor schedulng wth few preemptons. In RTCSA, 006. [9] S. K. Baruah, N. K. Cohen, C. G. Plaxton, and D. A. Varvel. Proportonate progress: A noton of farness n resource allocaton. In Algorthmca, [10] John Carpenter, Shelby Fun, Phlp Holman, Anand Srnvasan, James Anderson, and Sanjoy Baruah. A Categorzaton of Real-Tme Multprocessor Schedulng Problems and Algorthms [11] U. Dev and J. Anderson. Tardness bounds for global edf schedulng on a multprocessor. In RTSS, 005. [1] N. Guan, M. Stgge, W. Y, and G. Yu. Fxed-prorty multprocessor schedulng wth lu & layland s utlzaton bound. In Techncal Report, Uppsala Unversty, ( y), 010. [13] S. Kato and N. Yamasa. Real-tme schedulng wth tas splttng on multprocessors. In RTCSA, 007. [14] S. Kato and N. Yamasa. Portoned edf-based schedulng on multprocessors. In EMSOFT, 008. [15] S. Kato and N. Yamasa. Portoned statc-prorty schedulng on multprocessors. In IPDPS, 008. [16] S. Kato and N. Yamasa. Sem-parttoned fxed-prorty schedulng on multprocessors. In RTAS, 009. [17] S. Kato, N. Yamasa, and Y. Ishawa. Sem-parttoned schedulng of sporadc tas systems on multprocessors. In ECRTS, 009. [18] K. Lashmanan, R. Rajumar, and J. Lehoczy. Parttoned fxed-prorty preemptve schedulng for mult-core processors. In ECRTS, 009. [19] C. L. Lu and J. W. Layland. Schedulng algorthms for multprogrammng n a hard-real-tme envronment. In Journal of the ACM, [0] D. Oh and T. P. Baer. Utlzaton bounds for n-processor rate monotone schedulng wth statc processor assgnment. In Real-Tme Systems, 1998.