Design of Second Order Adiabatic Logic for Energy Dissipation in VLSI CMOS Circuits

Transcription

1 SSRG Inrnaional Journal of VLSI & Signal Procssing (SSRG-IJVSP Volum 4 Issu 1 Jan o April 017 Dsign of Scond Ordr Adiabaic Logic for Enrgy Dissipaion in VLSI CMOS Circuis Sudhakar Alluri 1, B.Rajndra Naik, N.S.S.REDDY 3 1 Elcronics and Communicaion Enginring Dparmn, Osmania Univrsiy, Hydrabad, Tlangana Sa, India. 3 N.S.S.REDDY is wih h Elcronics and Communicaion Enginring Dparmn, VCE, Osmania Univrsiy, Hydrabad, Tlangana Sa, India. Absrac Ths circuis produc an nrgy savings of V a mos on ordr of dd V. This papr propos a novl class of adiabaic oal circuis ha fac offr svral advanags ovr xising approachs, h prim on bing ha, bcaus no diods ar usd, swiching nrgy can b dcrasd o an nrgy flooring of O ( CV. Ths scond ordr adiabaic compuing circuis produc an nrgy savings of as much as O( V dd V ovr gnral CMOS. Th proposd circuis hav bn simulad and drmin adiabaic powr savings compard o sandard CMOS circuis ovr an prforming frquncy rang from 1MHz o 100MHz using Cadnc viruoso ool a 45nm chnology. W proposd a Basic N-P diffrnial buffr/invrr, 4-Phas shif rgisr bi, Complx ga. Basic N-NP Invrr/Buffr Ga, adiabaic Full Addr using CADENCE EDA ool a 45nm chnology. Kywords Sandard CMOS circuis, adiabaic full addr, low frquncy, low powr, Enrgy dissipaion,,complx ga, 4-Phas shif rgisr bi, VLSI. I. INTRODUCTION A. Enrgic and Adiabaic Charging Th nrgics of sandard CMOS (or any ohr swiching sysm basd on a singl fixd DC powr rail ar sraigh forward, a h charging swich is closd o charg h load C up o h rail volag V, a charg Q CV is pulld ou of h posiiv powr rail. A h ing swich is closd o h load C o ground, h sam charg Q CV is ransfrrd o h ground rminal of h powr supply. Ovr an nir charg/ cycl, a oal charg of Q CV was akn from h posiiv rail of h powr supply and rurnd o h ground rminal, and hus h oal nrgy dissipad ovr h nir cycl corrsponds o QV ( CV V CV oal charg.sinc hr wr wo swiching vns involvd, h avrag nrgy dissipad during charging and ing is on half of his oal dissipad nrgy, oal CV avrag. In h cas whr all swich rsisors and load capaciors ar linar, h nrgics ar symmric and h nrgy dissipad during charging or ing is xacly qual o his avrag swiching nrgy: CV charg. In h cas of non idal or nonlinar circui lmns, h nrgy dissipad during charging and ing nd no b qual, bu bcaus all of h charg was akn from h posiiv rail and rurnd o ground, oal nrgy dissipad ovr h charg/ cycl mus always qual wic h avrag swiching nrgy: oal charg avrag CV. This nrgy is dissipad by h ingrad I R loss of h charging and ing currns hrough h ffciv rsisanc of h circui (swich rsisancs (ransisor channls and parasiic rsisancs from h powr rail o h load C and from C o h ground nod: I oal ( R( I, d.(1 Whr w hav usd R ( I, o includ all changs in ffciv currn pah rsisanc ihr as a funcion of im (i: from swiching or as a funcion of currn (from nonlinariis. Th ky poin is ha indpndn of h sizs and/or funcion of his ffciv rsisanc R, h ingraion of ovr h nir charging/ing cycl is always h sam and is qual o QV ( CV V CV.Th oal charg rason for his is ha in a fixd DC-powrd swiching sysm, h circui lmns and h swiching currn ar rlad: h only way o chang h swiching currn is o chang h circui lmns (h linariy of R or C, or h siz of R for xampl, bu h dpndncy bwn h wo will rsul in no chang in h avrag dissipad nrgy: oal CV : For sandard singl supply-rail I R ISSN: Pag 14

2 SSRG Inrnaional Journal of VLSI & Signal Procssing (SSRG-IJVSP Volum 4 Issu 1 Jan o April 017 swiching sysms, h only way o rduc nrgy consumpion is o rduc h supply volag V, or h load capacianc C. Of cours, archicural approachs can also b mployd a h sysm lvl o rduc h numbr of swiching vns in h sysm. Th ssnial poin is ha for sysms of his yp, if a paricular load mus b swichd o a paricular volag wih a paricular avrag frquncy, hr is nohing ha can b don o rduc nrgy consumpion. Adiabaic compuing is compaibl wih h nrgy savings ha can b achivd hrough rducions in V or C, y achivs addiional rducions in dissipad nrgy by avoiding h singlrail DC powr supply archicur. If a singl non-dc powr supply rail is usd boh o charg and a swiching nod, h nrgics chang considrably. In his cas, oal dissipad nrgy ovr h charging/ing cycl nd no b rlad o ransfr charg and can in fac b mad arbirarily small. Whil for h DC powr supply cas analyzd abov, whr nods ar chargd from h DC powr supply rail and d ino h ground nod, h oal dissipad nrgy mus b rlad o h ransfrrd charg: QV, in h cas oal ch arg ha h powr supply rail chargs h swiching nod by ramping up and h sam powr supply rail lar s h nod by ramping down, his dpndncy bwn ransfrrd charg and dissipad nrgy nd no longr b ru bcaus charg ransfrrd from h powr supply o charg h nod can b rcovrd by h sam powr supply whn i lar s h nod. By aking advanag of adiabaic charging principls and charg rcovry, his approach o swiching braks h dpndncy bwn h swiching currn and h circui lmns so ha h nrgy dissipad as I R losss during h charging/ing cycl can b mad arbirarily small. This is accomplishd by making us of priodic ramp-lik clockd powr supplis. How his is don can mos asily sn by considring h IR dissipaion losss in h adiabaic charging cas. For a givn ramp im T, h ransfrrd charg in h adiabaic and non-adiabaic cass mus b h sam: Q CV. Th diffrnc bwn h wo in rms of nrgy dissipad is ha, whil in h non-adiabaic cas h currn is highly non uniform, in h adiabaic cas, bcaus of h ramp, i can b mad much mor uniform ovr h ramp im T, and in fac idally consan ( I Q T. By slowing down h ramp (incrasing T, h charging currn can b mad arbirarily small. Th nrgy dissipad during h charging cycl is I RT IRQ ch arg. Incrasing im T by a facor of α will dcras currn I by a facor of α (ransfrrd charg Q = IT will rmain h sam, bu bcaus I is no linar in I, dissipad nrgy I RT ch arg will dcras by a facor of α. Adiabaic charging principls allow dissipad nrgy o b an arbirarily small prcnag of ransfrrd nrgy by ransfrring charg a a consan and arbirarily slow ra. In h non adiabaic cas, maximum swiching currn ypically flows whn h volag diffrnc bwn h load C and h volag rail V or ground ar gras, lading o nrgy dissipaion spiks. Whil i migh b possibl o dvis a non adiabaic circui which had a uniform currn flow, prhaps vn qual o ha of h adiabaic circui, his would only b possibl wih a highly non uniform rsisor which had gras rsisanc whn h volag across i was gras. Bcaus of charg loss, h rsisor ndd for uniform currn would also lad o h sam oal dissipad nrgy: oal I ( R( I, d QV ( Th sysm spcificaion is h procssor: Inl (R cor (TM i CPU@3.0GHz.,3.0GHz.Insalld mmory (RAM 4 GB (3.43GB Usabl and sysm yp: 3bi opraing sysm. This papr is formd as follows Scion II prsns h liraur rviw on adiabaic logic scond ordr nrgy dissipaion and DSP Scion III prsns h mhodology for a Basic N-P diffrnial buffr/invrr, 4-Phas shif rgisr bi, Complx ga. Basic N-NP Invrr/Buffr Ga and adiabaic Full Addr of Enrgy Dissipaion Scion IV shows h simulaion rsuls and hy ar discussd clarly, finally h papr is concludd wih Scion V. II. LITERATURE REVIEW A. Dsign Work Programmabl rvrsibl logic is dvloping as a xpcd logic dsign syl for implmnaion in low powr, low frquncy applicaions poin minimal impac on circui ha gnraion is dsirabl, such as rducion of diffrnial powr analysis aacks [1]. Major limis of CMOS-basd adiabaic logic ar analyzd. Analyic rlaions dscribing h nrgyprformanc for sub-hrshold adiabaic logic ar also xplicily drivd and opimizd [].Powr opimizaion in circuis and sysms is h dmanding facor for mos of h dsignrs and indusris. Many powr dissipaion chniqus hav bn inroducd bu mos of hs chniqus hav som pac [3]. Alhough h concps of adiabaic charging hav bn wllsablishd for som im [4,5], arly circui proposals, Alhough vry inrsing from a horical sandpoin, wr no pracicabl for larg-scal implmnaion du o h bulkinss and complxiy of h circuis, h larg ovr hads involvd, h complxiy of h iming and powr supply/clock gnraion and h rlaivly slow spds a which ISSN: Pag 15

3 SSRG Inrnaional Journal of VLSI & Signal Procssing (SSRG-IJVSP Volum 4 Issu 1 Jan o April 017 hy would opra. Currnly inrs has rsuld in svral much mor pracical circui implmnaions of adiabaic compuing circuis [6, 7,8,9,10,11,1,13]. Ths circuis, rahr han aiming o achiv nrgy dissipaion floors approaching h horical minimum, achiv much mor pracical implmnaions by aiming for nrgy floors which ar only a facor of - 0 lss han ha of convnional saic CMOS logic is calld vanilla CMOS from now on Svral rcnly dsign uss mak us of h fac ha diods can b usd o provid vry compac and fficin adiabaic charging lmns [4,5,8,11]. Ths circuis xhibi adiabaic nrgy savings, bu h us of diods for adiabaic charging in any circui limis his saving o a facor of V ovr ha of convnional circuis. Th rason V for his is ha a diod will hav a volag drop which is o firs ordr consan and qual o V for any posiiv currn drivn hrough i. This mans ha for a diod, IR = V = V (i is a nonlinar currndpndan rsisor, and nrgy dissipad in adiabaic charging hrough a diod canno b lss han E d = I RT = IT * IR = QV = CV V. Th maximum nrgy savings possibl hough any diod-basd adiabaic charging circuis is hus limid o 1/(QV/QV = 1/(V/V, no mar how slowly h charging occurs. III. DESIGN METHODOLOGY A. Ordr of Adiabaic Dissipaion W hav found his facor ofv V o b a usful rfrnc in analyzing nrgy dissipaion in adiabaic circuis as compard o convnional swiching circuis. Firs ordr adiabaic losss corrspond o losss which hav a floor of O CVV O( QV /[ V / V ], such as h diod ( charging losss dscribd abov. Scond ordr adiabaic losss corrspond o losss which hav a floor of O( CV O( QV /[ V / ], such as a V non adiabaic swiching vn from V o ground. By his convnion, horical nrgy floors which ar indpndn of V dd and V such as kt would b calld Nh ordr adiabaic losss. Pracical adiabaic compuing circuis ypically conain firs and/or scond ordr loss rms, and hus hav nrgy floors which ar high compard o h horical minimum. Whil i would sm ha firs ordr losss ar mor imporan han scond ordr losss, V V is ypically no vry larg and any loss rm has a scaling facor in fron of i, so i dos no ak many scond ordr loss rms o qual a firs ordr loss rm. In fac, whil diod basd adiabaic charging sysms mus hav a firs ordr nrgy loss, hy ofn hav on mor scond ordr losss which may domina h acual nrgy floor. B. Scond Ordr Adiabaic Circuis This work proposs a nw class of circuis wih a low nrgy floor. Th ssnial nrgy advanag of hs circuis coms from h fac ha hy hav bn adiabaically dsignd o limina all firs ordr nrgy losss and o minimiz scond ordr losss as much as possibl. This is accomplishd primarily by charging nods hrough minimal swich rsisancs rahr han diods. Th circuis w dscrib raliz his advanag wih minimal addiional ovrhad and complxiy ovr diod-basd circuis, ihr a h circui or sysm lvl. Ths circuis ar a mos wo ims h siz of h smalls diod-basd adiabaic circuis, making hm abou h sam siz as vanilla CMOS, and hy opra a similar frquncis of grar han 100MHz. Anohr advanag of hs nw circuis is ha, whil mos diod-basd adiabaic compuing circuis hav oupu lvls which ar floaing during hir oupu valid im, hs nw circuis provid oupus which ar clampd during hir oupu valid im (lik vanilla CMOS. This is imporan a h sysm lvl in rms of rducing crossalk and rsoring logic lvls. C. Basic opraion of h N-P Family Th firs of hs circuis w will inroducd is calld N-P. Th nam is basd on our convnion of using h numbr of ransisors in a ga bcaus h cos for ach inpu in rms of ransisors is Nfs and h ovrhad for ach compl ga is Pfs. Th circui uss diffrnial logic, so ach ga compus boh a logic funcion and is complmn, and ach inpu o a ga rquirs boh polariis o b rprsnd. Th basic circui for a invrr-buffr is shown in Fig 1. Each Nf inpu gs h corrsponding posiiv and ngaiv polariy inpus and h cross-coupld Pfs ar conncd o h clock-supply. Th iming and logical opraion of h ga is as follows (Fig : Figur 1: Basic n-p Diffrnial Buffr/Invrr. D. Complx Gas and Squncs of Gas Bcaus hr ar four phass o h iming, hr mus b four quadraur clocks in a compl sysm, ach clock 90 dgrs in advanc of h prvious clock. In his way, ach logic phas in h sysm holds is oupus valid whil is succssor is valuaing (ramping up and is prdcssor is ISSN: Pag 16

4 SSRG Inrnaional Journal of VLSI & Signal Procssing (SSRG-IJVSP Volum 4 Issu 1 Jan o April 017 rsing (ramping down and wais wih is oupus boh low whil is succssor is rsing (down and is succssor is valuaing (up. logical opraion of N-NP is idnical o ha of N-P. Figur : 4-Phas Shif Rgisr Bi. A shif rgisr can b consrucd by making a squnc of buffr/invrr gas conncd squnially and in h propr phas rlaionship, ha is: PHI1, PHI, PHI3, PHI4, PHI1,..(figur. W hav simulad an cadnc viruoso 45nm chnology CMOS implmnaion of such shif rgisrs using minimum siz ransisors a spds in xcss of 100 MHz Figur 3: Complx Ga. Mor complx gas can b consrucd by rplacing h singl Nfs usd in h invrr/buffr wih an arbirary Nf-basd logic r and is invrs (fig 3. Bcaus h diffrnial logic provids boh ngaiv and posiiv polariy signals, providing boh posiiv and ngaiv logic rs using only Nfs is sraighforward: whil in vanilla CMOS h posiiv logic r is crad by conncing a singl inpu polariy o Nfs and h ngaiv logic r is crad by conncing h sam inpu polariy o h Pfbasd invrs r, in h cas of diffrnial logic boh h logic r and is invrs can b Nf-basd as vry Nf conncd o an inpu in h logic r has a corrsponding Nf conncd o h invrd inpu in h invrs logic r. W hav simulad logic gas wih up o 4x4=16 inpus a spds up o 100MHz. E. N-NP and Sysm Issus A varian on h N-P logic family dscribd abov is ha of h N-NP family, h only diffrnc bing ha N-NP has a pair of cross-coupld Nfs in addiion o h cross-coupld Pfs common o boh familis (fig 4. N-NP hus has cross-coupld full invrrs and hus is vry similar o a sandard SRAM cll. Th iming and Figur 4: Basic n-np Invrr/Buffr Ga. Fully-saic logic such as vanilla CMOS has oupus which offr wo imporan advanags a h sysm lvl. Th firs of hs is ha is oupus ar always clampd o ihr V dd or Gnd. This is imporan o rsor logic lvls and rduc h ffcs of crossalk. Th scond advanag is ha fully-saic logic has saic oupus which ar always valid; if h inpus do no chang nihr do h oupus. This is imporan for simplifying iming and sysm dsign. Dynamic logic such as domino CMOS njoys nihr of hs advanags. F. Enrgy Dissipaion Th analyss of h nrgics of h N-P and N-NP adiabaic logic familis ar idnical. Th analysis rquirs a mor lcrical dscripion of h iming. As alrady dscribd in h logical iming dscripion, during h RESET phas, whn h clock is ramping down and h inpus ar hld low, on oupu is alrady low and h ohr oupu "rids" h clock down. Th high oupu will rid down only o V, rahr han gnd, bcaus a ha poin h Pf cass o conduc. Following RESET hn, boh oupus ar no low bu rahr h low oupu is low whil h high oupu is floaing a V. If during h EVALUATE phas, h logical sa of h ga has no changd (h high oupu should coninu o b high, h high oupu which is floaing a V will rid h clock up, bginning is conducion whn h rising clock has again rachd a volag of V. Ths dails do no rally chang h analysis of h nrgics in h cas whn h logical sa of h ga has no changd. Bcaus h upward and downward ramp on h oupu is fully adiabaic, nrgy loss can b mad arbirarily small by making h ramp im arbirarily long. During h HOLD phas, whn h oupus ar floaing, hr is no nrgy loss. Whn h ga oupu sa maks a ransiion from on logical sa o h ohr, h fac ha h old high oupu was floaing a V bcoms criical howvr. During h HOLD phas h inpus bcom valid and h logical sa of h ga will chang. This mans ha h floaing ISSN: Pag 17

5 SSRG Inrnaional Journal of VLSI & Signal Procssing (SSRG-IJVSP Volum 4 Issu 1 Jan o April 017 oupu, which in h prvious sa was high and hus had a non conducing logical Nf r, will now hav a conducing r. Ths valid inpus will hus connc h floaing oupu, which is a a volag of V, o ground and h rsul is a non adiabaic charg ransfr of O( CV. Th sam is ru for h old low oupu which now mus rid h ramp up; i will mak a non adiabaic ransiion from Gnd o V whn h ramp rachs V and his will dissipa nrgy of O( CV. Bcaus charg of Q CV was supplid from h ramp o h load whn h ramp was a a volag of V and his charg was lar ransfrrd o Gnd, h oal nrgy dissipaion for h charg/ cycl can b drmind as bfor: oal charg CV. Bcaus his nrgy loss is non adiabaic, hr is no way o rduc i; i is indpndn of clock spd. Ths logical familis will hus los som arbirarily small nrgy a ach clock cycl corrsponding o adiabaic I R losss in h Pfs and will los CV a ach ga ransiion cycl. This can b compard o vanilla CMOS, which will los som small nrgy as lakag a all ims and will los CV for ach ransiion cycl. Figur 5 Basic N-P Diffrnial Buffr/Invrr Of Schmaic Diagram. Figur 5 givs Basic N-P diffrnial buffr/invrr wih h inpus of Vin+, Vin- and oupus of V ou +, V ou- For all inpus combinaions frquncy of 100MHz signal is applid and vrifid IV. SYNTHESIS AND SIMULATION RESULTS Th Simulaions of Basic N-P diffrnial buffr/invrr using Cadnc Viruoso EDA ool a 45nm chnology. Ths simulaions ar obaind using h spcificaions shown in abl 1. TABLE 1: NMOS AND PMOS SPECIFICATIONS Spcificaion NMOS PMOS Library nam Gpdk 45 Gpdk45 Lngh 45 nm 45 nm Toal widh 10 nm 40 nm Fingr widh 10nm 40 nm Ris/fall im 100f s/100f s Load Capacianc 5fF Figur 6 Basic N-P Diffrnial Buffr/Invrr Of Simulaion Oupu Wavform A Th Frquncy 100M Hz. Tabl 7 Basic N-P Diffrnial Buffr/Invrr Powr Dissipaion, Tabl Basic N-P Diffrnial Buffr/Invrr Vol Frqu Pow Enrgy Dissipaion (fj ag( ncy(m r(pw V Hz ch ( I arg R * T ISSN: Pag 18

6 SSRG Inrnaional Journal of VLSI & Signal Procssing (SSRG-IJVSP Volum 4 Issu 1 Jan o April oupus of V ou +, V ou- For all inpus combinaions frquncy of 100MHz signal is applid and vrifid Tabl is obsrvd ha h powr and nrgy dissipaion and 1MHz o 100MHz frquncy rang a 0.7V. Figur 8 Engy Dissipaion of Basic N-P Diffrnial Buffr/Invrr a 45nm Tchnology. Figur 11 N-NP Buffr/Invrr Of Powr Dissipaion Tabl 3 Enrgy Dissipaion Of Basic N-NP Buffr/Invrr Vola g(v Frqun cy(m Powr( pw Enrgy Dissipaion(fJ Hz ( I R 0.7 ch arg * T Figur 9 Basic N-NP Invrr/Buffr Ga of Schmaic Diagram Th Simulaions of Basic N-N P Invrr/Buffr using Cadnc Viruoso EDA ool a 45nm Tchnology. Ths simulaions ar obaind using h spcificaions shown in abl, Figur 9 givs Basic N-NP diffrnial buffr/invrr wih h inpus of Vin+, Vin- and oupus of V ou +, V ou-. Tabl 3 is obsrvd ha h powr and nrgy dissipaion and 1MHz o 100MHz frquncy rang a 0.7V Figur 1 Enrgy Dissipaion Of Basic N-NP Buffr/Invrr Figur 10 Basic N-NP Buffr/Invrr Oupu Wav form a Frquncy 100mhz. Figur 10 givs Basic N-NP diffrnial buffr/invrr wih h inpus of Vin+, Vin- and ISSN: Pag 19

7 SSRG Inrnaional Journal of VLSI & Signal Procssing (SSRG-IJVSP Volum 4 Issu 1 Jan o April 017 Tabl 4 4 Phas Shif Rgisr Bi Volag( V Frquncy(M Hz Powr(p W 0.7 Enrgy Dissipaion(fJ ch ( arg * I R T Figur 13 4-Phas Shif Rgisr Bi Of Schmaic. Figur 13 is h Simulaions of 4-Phas shif rgisr bi using Cadnc Viruoso EDA ool a 45nm chnology a 0.7V. Tabl 4 is obsrvd ha h powr and nrgy dissipaion and 1MHz o 100MHz frquncy rang a 0.7V. Th Simulaions of 4 phas shif rgisr bi using Cadnc Viruoso EDA ool a 45nm chnology. Ths simulaions ar obaind using h spcificaions shown in abl 4. Figur 16 Enrgy Dissipaion Of 4 Phas Shif Rgisr Bi Figur 14 4-Phas Shif Rgisr Bi Of Oupu Wavform Figur 16 4-Phas shif rgisr bi of powr and nrgy dissipaion of wavform. Figur 14 4-Phas shif rgisr bi of oupu wavform, for all inpus combinaions frquncy of 100MHz signal is applid and vrifid. Figur 17 Complx Ga Of Schmaic Diagram Figur 15 4-Phas Shif Rgisr Bi Of Powr Dissipaion Figur 17 is h schmaic diagram of Complx ga using Cadnc Viruoso EDA ool a 45nm chnology a 0.7V. ISSN: Pag 0

8 SSRG Inrnaional Journal of VLSI & Signal Procssing (SSRG-IJVSP Volum 4 Issu 1 Jan o April 017 Figur 18 Complx Ga Oupu Wavform Figur 18 Complx ga of oupu wavform, For all inpus combinaions frquncy of 100MHz signal is applid and vrifid. Vola g(v Frqun cy( MH z Tabl 5 Complx Ga Powr( nw Enrgy dissipaion (pf arg ( I R ch * Figur 0 Sum Gnraion Block Of An Adiabaic Full Addr Figur 0 Sum gnraion block of an adiabaic Full Addr of using Cadnc Viruoso EDA ool a 45nm chnology load capacior 10f F applid Tabl 5 is obsrvd ha h powr and Enrgy dissipaion and 1MHz o 100MHz frquncy rang a 0.7V. Figur 1 Sum Gnraion Block Of An Adiabaic Full Addr Of Oupu Wav Form Figur 1 Sum gnraion block of an adiabaic Full Addr of oupu wav for all inpus combinaions frquncy of 100MHz signal is applid and vrifid. Figur 19 Enrgy Dissipaion Of Complx Ga Figur 19 Enrgy Dissipaion of Complx ga of using Cadnc Viruoso EDA ool a 45nm chnology. Figur Sum Gnraion Block Of An Adiabaic Full Addr Of Powr Dissipaion ISSN: Pag 1

9 SSRG Inrnaional Journal of VLSI & Signal Procssing (SSRG-IJVSP Volum 4 Issu 1 Jan o April 017 Tabl 6 Comparison In Enrgy Dissipaion Of Adiabaic Full Addr Vo la g( V Frq unc y(m Hz Full addr (Sum Powr( nw Enrgy dissipaio n of full addr SUM Full addr (Carr y Pow Enrgy dissipaion of full addr CARRY (pj (pj r(nw ch arg ( I R * T Figur 3 Carry Gnraion Block Of An Adiabaic Full Addr Figur 3 Carry gnraion block of an adiabaic Full Addr using Cadnc Viruoso EDA ool a 45nm chnology and load capacior 10f F applid Figur 6 Comparison of powr and Enrgy dissipaion Adiabaic Full Addr a 45nm Tchnology. Figur 4 Carry Gnraion Block Of An Adiabaic Full Addr Oupu Wav Form. Figur 4 Carry gnraion block of an adiabaic full addr oupu wav form. for all inpus combinaions frquncy of 100MHz signal is applid and vrifid. Figur 6 Comparison of powr and Enrgy dissipaion of adiabaic full addr. Tabl 7 Comparison in nrgy dissipaion of Basic N-P Buffr/invrr and N-NP Buffr/invrr Basic N-P Buffr/invrr Enrgy Dissipaion(fJ Basic N-NP Buffr/invrr Enrgy Dissipaion(fJ Figur 5 Carry Gnraion Block Of An Adiabaic Full Addr Of Powr Dissipaion ISSN: Pag

10 SSRG Inrnaional Journal of VLSI & Signal Procssing (SSRG-IJVSP Volum 4 Issu 1 Jan o April 017 Figur 7 Comparison in nrgy dissipaion of Basic N- P Buffr/invrr and N-NP Buffr/invrr Figur 7 Comparison in nrgy dissipaion of Basic N-P Buffr/invrr and N-NP Buffr/invrr of Comparison in Enrgy dissipaion of adiabaic full addr. ACKNOWLEDGEMENT W acknowldg h Univrsiy Grans Commission for is conomic suppor in h form of Rajiv Gandhi Naional Fllowship (RGNF for h yar W hank all h faculis in h Dparmn of ECE and h lab saff for hir suppor. V. CONCLUSION In his papr, w dsignd a Basic N-P diffrnial buffr/invrr, 4-Phas shif rgisr bi, Complx ga. Basic N-NP Invrr/Buffr Ga, adiabaic Full Addr using CADENCE EDA ool a 45nm chnology, Tabl Comparison of powr and nrgy dissipaion of Basic N-P diffrnial buffr/invrr, Tabl 3 Comparison of powr and nrgy dissipaion Basic N-NP diffrnial buffr/invrr, Tabl 4 Comparison of powr and nrgy dissipaion of 4-Phas shif rgisr bi, Tabl 5 Comparison of powr and nrgy dissipaion of Complx ga, Tabl 6 Comparison of powr and nrgy dissipaion of adiabaic full addr, Tabl 7 Comparison in nrgy dissipaion of Basic N-P Buffr/invrr and N-NP Buffr/invrr. REFERENCES [1] Mahw Morrison, and Nagarajan Ranganahan," Synhsis of Dual-Rail Adiabaic Logic for Low Powr Scuriy Applicaions",IEEE TRANSACTIONS ON COMPUTER- AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 33, NO. 7, JULY 014, _c 014 IEEE. [] Samr Houri, Grard Billio, Marc Bllvill, Alxandr Valnian, and Hrvé Fan," Limis of CMOS Tchnology and Inrs of NEMS Rlays for Adiabaic Logic Applicaions",IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, IEEE. [3] Irfan Ahmad Pindoo, Tjindr Singh, Amripal Singh," Powr Dissipaion Rducion Using Adiabaic Logic Tchniqus for CMOS Invrr Circui",6h ICCCNT July 13-15, 015, Dnon, U.S.A,IEEE [4] Rolf Landaur, "Irrvrsibiliy and Ha Gnraion in h Compuing Procss", IBM J. Rs. Dvl. vol. 5pp (1961. [5] C. H. Bnn,"Logical Rvrsibiliy of Compuaion", IBM J. Rs. Dvl. vol. 17, pp55-53 (1973. [6] C. Siz al., "Ho Clock nmos", Procdings of h 1985 Chapl Hill Confrnc on VLSI. Compur Scinc Prss (1985. [7] Rodrick T. Hinman and Marin F. Schlch, "Powr Dissipaion Masurmns on Rcovrd Enrgy Logic", 1994 Symposium on VLSI Circuis / Digs of Tchnical Paprs, 19. IEEE (Jun [8] A. G. Dickinson and J. S. Dnkr, "Adiabaic Dynamic Logic", Procdings of h Cusom Ingrad Circuis Confrnc. IEEE (1994. [9] [J. G. Kollr and W.C. Ahas, "Adiabaic Swiching, Low Enrgy Compuing, and h Physics of Soring and Erasing Informaion", PhysComp '9: Proc. of h Workshop on Physics and Compuaion. IEEE (1993. [10] Ralph C. Mrkl, "Rvrsibl Elcronic Logic using Swichs", Nanochnology Vol. 4 1{40. (1993. [11] Alan Kramr, John S. Dnkr, Sphn C. Avry, Alx G. Dickinson, and Thomas R. Wik, "Adiabaic Compuing wih h N-ND Logic Family", 1994 Symposium on VLSI Circuis / Digs of Tchnical Paprs,5. IEEE (Jun [1] J. S. Hall, "An Elcroid Swiching Modl for Rvrsibl Compur Archicurs", Phys Comp '9: Proc. of h Workshop on Physics and Compuaion. IEEE (1993. [13] S. G. Younis and T. Knigh, "Pracical Implmnaion of Charg Rcovring Asympoically Zro Powr CMOS", Proc. of 1993 Symposium on Ingrad Sysms, 34{50. MIT Prss (1993. [14] T.J. Gabara, "Pulsd Low Powr CMOS", Inr. J. of High Spd Elc. and Sysms, Vol. 5, (1994. [15] Y. Van Rnrgm and A. D Vos, Opimal dsign of a rvrsibl full addr, in Proc. In. J. Unconvnional Compu., 005, pp [16] A. D Vos, Rvrsibl Compuing. Winhim: Wily-VCH, 010. [17] V. V. Zhirnov, R. K. Cavin, J. A. Huchby, and G. I. Bourianoff, Limis o binary logic swich scaling: A Gdankn modl, Proc. IEEE, vol. 91, no. 11, pp , Nov [18] K. Cavin, V. V. Zhirnov, J. A. Huchby, and G. I. Bourianoff, Enrgy barrirs, dmons, and minimum nrgy opraion of lcronic dvics, in Proc. Fluc. Nois L., Ausin, TX, USA, 005. [19] G. P. Bochlr, J. M. Whiny, C. S. Ln, A. O. Orlov, and G. L. Snidr, Fundamnal limis of nrgy dissipaion in charg-basd compuing, Appl. Phys. L., vol. 97, no. 10, pp , Sp [0] V. V. Zhirnov and R. K. Cavin, Commn on Fundamnal limis of nrgy dissipaion in charg-basd compuing, Appl. Phys. L., vol. 98, no 9, 010. [1] G. P. Bochlr, J. M. Whiny, C. S. Ln, A. O. Orlov, and G. L. Snidr, Rspons o Commn on Fundamnal limis of nrgy dissipaion in charg-basd compuing, Appl. Phys. L., vol. 98, no. 9, pp , 011. [] G. L. Snidr al., Minimum nrgy for compuaion, hory vs.xprimn, in Proc. IEEE-NANO, Porland, OR, USA, Aug. 011, pp [3] R. Puri, Opporuniis and challngs for high prformanc microprocssor dsigns and dsign auomaion, in Proc. ACM ISPD, Nw York, NY, USA, 013, p [4] Y. Moon and D. K. Jong, An fficin charg rcovry logic circui, IEEE J. Solid Sa Circuis, vol. 31, no. 4, pp , Apr [5] M. Sad and I. Markov, Synhsis and opimizaion of rvrsibl circuis A survy, ACM CSUR, vol. 45, no., Aricl 1, Fb [6] D. Sokolov, J. Murphy, A. Bysrov, and A. Yakovlv, Dsign and analysis of dual-rail circuis for scuriy applicaions, IEEE Trans. Compu., vol. 54, no. 4, pp , Apr ISSN: Pag 3

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