A Low-Complexity and High-Throughput RTL Design of a BCH (15,7) Decoder

Transcription

1 ITB J. ICT, Vol., No.,, - A Low-Compleity and High-Thoghpt RTL Design of a BCH (,) Decode Henda Setiawan Electical Engineeing Depatment, Islamic Univesity of Indonesia Jl. Kaliang Km.. Yogyakata, Indonesia, 8 henda.setiawan@ii.ac.id Abstact. The Bose, Chadhi and Hocqenghem (BCH) codes fom a lage class of powefl andom-eo coecting cyclic codes. Howeve, the implementation of its decode eqies high-compleity comptation esoces with a hge nmbe of seqential cicits. This pape pesents a low-compleity egiste tansfe level (RTL) cicit design of a BCH decode. In accodance with the table elationship between the syndome and the eo bit position, we popose a cicit that is mostly occpied by combinational elements withot any seqential evolvement. Theefoe the designed system has a low compleity and high thoghpt popeties. The implementation of the BCH (,)decode on Vite FXTFF eqies look-p tables (LUTs) with the maimm thoghpt eaching. Gbps. Keywods: BCH decode; cyclic code; eo coection; RTL; syndome. Intodction Today, eo-coecting codes ae sed thoghot digital commnication systems. Satellite commnications, cell-phones, compact disc playes, DVDs, disk dives, two-dimensional ba code systems and many othe commnication devices se vaying amonts of eo contol to achieve a cetain degee of accacy in tansmitting infomation. The Binay Bose, Chadhi and Hocqenghem (BCH) codes, discoveed by Hocqenghem in 99 and independently investigated by Bose and Chadhi in 9, ae a emakable genealization of the Hamming codes fo mltiple-eo coection. BCH codes containing Reed-Solomon codes have been widely adopted in pactical eocontol applications, owing to thei good pefomance against degadation and the fleibility they allow in setting appopiate paametes []. Digital Video Boadcasting (DVB) [] and Woldwide Inteopeability fo Micowave Access (WiMAX) [] ae eamples of cent standads that tilize BCH in thei system. One of the well-developed algoithms to decode binay BCH code ses a Eclidean algoithm []. Howeve, its pocess eqies high comptation esoces de to the eo-locato polynomial. Othe algoithms ae step-by-step Received Apil th,, Revised Agst th,, Accepted fo pblication Agst th,. Copyight Pblished by LPPM ITB, ISSN: 98-8, DOI:./itbj.ict...

2 RTL Design of BCH (,) Decode algoithms [],[] that consist of pocede tests to check whethe the eo patten weight falls by changing the eceived symbols one at a time. This decoding pocede does not teminate ntil the eo patten weight has been edced to zeo o all eceived infomation symbols have been tested. Hence, this is called an iteative method of decoding. Even thogh the hadwae implementation [] is less comple than that of the fist decoding algoithm, the thoghpt may not be highe de to the iteative pocedes. In this pape, we popose a simple hadwae implementation pocede with low compleity and high thoghpt popeties. This simple combinational cicit was developed based on the table elationship between the syndome and the eo bit position. Ths, a low-compleity BCH decode cold be developed. Fthemoe, the decode thoghpt cold be inceased by employing pipelining and paallelization. This pape is oganized as follows. In Section, the achitecte of the encode and the decode is detailed. The design compleity is eplained in Section. In Section, the compilation and synthesis eslts ae pesented. Finally, conclsions ae dawn in Section. Achitecte Desciption. Encode Specification The achitecte of a BCH encode sing shift egiste has been intodced by Massy in 99 [8]. This pape consides a BCH (,) encode consisting of infomation bits and 8 paity bits as taget implementation. The sending bit (SB) of this BCH (,) encode ae based on the polynomial given by: 8 9 SB whee,,,,,, epesent infomation, and,,,,,,, epess the paity bits. This can be implemented sing the emainde polynomial, based on: 8. () Fthemoe, Eq. () can be ealized by a simple cicit, as shown in Fige, whee,,, inptted seially in signal inpt pot (SIN), and,,, geneated afte seven clock cycles. ()

3 Henda Setiawan Fige Cicit implementation of the BCH (,) encode. A paallel pocess to get the paity bits is intodced in ode to each a highe thoghpt. Paallel comptation is pefomed based on the emainde polynomial of 9 8 R. () Based on Eq. (), we can deive the emainde polynomial 9,,,, and,and then sbstitte to Eq. (). Hence, we get R () Theefoe, ; ; ; ; ; ; ;. Eq. () can be ealized easily in a cicit, as shown in Fige, whee the adde symbol is implemented sing XOR gates.

4 RTL Design of BCH (,) Decode U U U U U U U Fige Paallel comptation of a BCH (,) encode.. Poposed BCH (,) Decode This pape poposes paallel comptation fo the BCH (,) decode to each a highe thoghpt. The poposed system consists of main blocks, as shown in Fige. RBWE [:] Syndome S [:] Eo Possibility Detection [:] [:] [:] [:] Eo Coection RBEC [:] Colmn Gop Detection Eo Possibility Eo Possibility [:] [:] [:] Detection Decode [:] [:] [:] Syndome S Fige Block diagam of the BCH (,) decode... Syndome Calclation In this pocess, syndome blocks S and S geneate the syndome bits of eceived bits with eo (RBWE). The geneation polynomial G() fo eochecking is given by, G G (). ()

5 Henda Setiawan G () and G () ae elated to syndome S and syndome S espectively. If thee is no eo in the eceived code, both the emainde polynomial of G () and that of G () emain zeo. Sppose the eceived bits with eo (RBWE) ae epessed as, 8 9 RBW E. () Based on Eq. (), we can deive the emainde polynomial fo,,, and then sbstitte it in Eq.(), hence syndome S is: S. (8) Ths, S ; S ; S ; S. (9) In the same way, syndome S can be epessed as, S ; S ; S ; S () By eplacing each (+) sign with an XOR gate, in total 8 XOR gates ae eqied fo the syndome calclation block. Howeve, this can be edced by shaing the same logic, sch as û XOR û, sed in S() as well as in S(). This will edce the nmbe of XOR gates fom 8 to... Eo Position Detection The net pocess is eo position detection based on the vales of syndome S and S. Eq. () will be e-applied and eaanged, becoming:

6 RTL Design of BCH (,) Decode S S S S () It is clea that an eo occs in û, o and has only eslted on S(). In the same way, an eo in û, o only has an effect on S(). In Table, fom the table elationship between the syndome bits and eo bits position, it can be seen that they occpy the same colmn. Ths, thee ae colmn gops (CG), i.e. CG, consisting ofû, and, coesponds to S = ; CG, consisting of û, and, coesponds to S = ; CG, consisting of û, and, coesponds to S = ; CG, consisting of û,û and, coesponds to S = ; CG, consisting of û,û and, coesponds to S =. Table Relation between syndome bits and eo bits position. Eo S (S, S, S, S ) Position None 8,,,,,9,,,,,,8 9,,,,,,9,,, 8,,,, 8,,,,9, 8,,,,,, 9,,,,,9,,8,,8,,,,9,,,8,,,,9,,9,,8,,,,, 8,,,,, 9,,8, 9,,,,, 9,,,,,8,,, 8,,9,,,,,,,8,,,, 9,,,,,,, 8,9 S (S, S, S, S) Theefoe, the ecognition of a CG can be based on the position of bit in S. Fo eample, S = means thee is an eo in CG and an eo in CG. Howeve, if an eo in CGis intodced fom anothe CG, the ecognition scheme becomes diffeent. Fo eample, an eo occs in CG as well as an eo in CG, whee S = cannot be ecognized fom the bit position. In this case, an invete is eqied befoe ecognition of the bit position takes place. Howeve, the invete only woks if the nmbe of bit is moe

7 8 Henda Setiawan than two. Theefoe, the code gop detection system consists of the nmbe of bit calclation, selectos, and bit position ecognition. The fist component in the code gop detection system is the nmbe of bit calclation. A -bit adde can be sed to implement it. Howeve, it may need big esoces since an adde consist of XOR and AND gates in fo bits. Since o taget does not actally cont the nmbe of bit bt only ecognizes that the nmbe of bit is moe than two, we popose a combinational cicit that only ses fo AND gates and thee OR gates. This is epessed in tem of syndome S as SEL. SEL is when the nmbe of bit within S bits is moe than two. This eqation also epesses CG detection, since CG always eists if the nmbe of bit is moe than two. The net component is the selecto. Its fnction isto select between S and (NOTS). The XOR gate has been chosen as the selecto. The inpts ae S and SEL, and the otpt belongs to the code gop. Theefoe, bit position ecognition is no longe eqied. Finally, the code gop detection cicit shown in Fige consists of AND gates, OR gates, and XOR gates. S() S() CG S() S() SEL (Nmbe of bit '') > Detecto CG CG CG CG Selecto Fige Code gop detection cicit. Fthemoe, to simplify the eo detection pocess, we divide the eo possibilities into two gops: eo possibility (EP) and eo possibility (EP). EP consists of two eos occing at the same time and in the same CG. Notice Eq. (), when two eos in the same CG occ at the same time, it makess =. In the net discssion, all eo possibilities in the S = colmn of Table ae categoized as EP.

8 RTL Design of BCH (,) Decode 9 The net eo gop is eo possibility (EP). This gop incldes all eos in evey colmn of Table ecept colmn S =. Note that all eos means, all eos that can be ecognized and ecoveed by this eo coection algoithm.... Eo Possibility (EP) EP occs when two eos come fom the same CG. The popety of this case is syndome S = AND S. The only way to detect the eos is diect mapping between S and the eo bit position within eceived bits. Based on Table, colmn S =, the combinational cicit fo ERROR(:) can be epessed as: ERROR() = S_ OR S_ ERROR() = S_ OR S_ ERROR() = S_ OR S_ ERROR() = S_ OR S_ ERROR() = S_ OR S_8 ERROR(9) = S_9 OR S_ ERROR(8) = S_ OR S_ ERROR() = S_ OR S_ ERROR() = S_ OR S_ ERROR() = S_8 OR S_ ERROR() = S_ OR S_9 ERROR() = S_ OR S_ ERROR() = S_ OR S_ ERROR() = S_ OR S_ ERROR() = S_ OR S_ () whee, S_ = (NOT S()) AND (NOT S()) AND (NOT S()) AND S() S_ = (NOT S()) AND (NOT S()) AND S() AND (NOT S()) S_ = (NOT S()) AND (NOT S()) AND S() AND S() S_ = (NOT S()) AND S() AND (NOT S()) AND (NOT S()) S_ = (NOT S()) AND S() AND (NOT S()) AND S() S_ = (NOT S()) AND S() AND S() AND (NOT S()) S_ = (NOT S()) AND S() AND S() AND S() S_8 = S() AND (NOT S()) AND (NOT S()) AND (NOT S()) S_9 = S() AND (NOT S()) AND (NOT S()) AND S() S_ = S() AND (NOT S()) AND S() AND (NOT S()) S_ = S() AND (NOT S()) AND S() AND S() S_ = S() AND S() AND (NOT S()) AND (NOT S()) S_ = S() AND S() AND (NOT S()) AND S() S_ = S() AND S() AND S() AND (NOT S()) S_ = S() AND S() AND S() AND S() This eqies AND gates, OR gates and 8 NOT gates. Howeve, shaing comptation is intodced in S_ to S_, so that:

9 Henda Setiawan S_ = C_ AND C_ S_ = C_ AND C_ S_ = C_ AND C_ S_ = C_ AND C_ S_ = C_ AND C_ S_ = C_ AND C_ S_ = C_ AND C_ S_8 = C_ AND C_ S_9 = C_ AND C_ S_ = C_ AND C_ S_ = C_ AND C_ S_ = C_ AND C_ S_ = C_ AND C_ S_ = C_ AND C_ S_ = C_ AND C_ () whee, C_ = (NOT S()) AND (NOT S()) C_ = (NOT S()) AND S() C_ = S() AND (NOT S()) C_ = S() AND S() C_ = (NOT S()) AND (NOT S()) C_ = (NOT S()) AND S() C_ = S() AND (NOT S()) C_ = S() AND S() This scheme only needs AND gates (a half less than befoe) and 8 NOT gates (edced to 8%). EP consists of thee pats, as shown in Fige. The fist pat comptes C_, C_, C_, C_, C_, C_, C_ and C_ simltaneosly. The second pat comptes S_ p to S_ as epessed in Eq. (). The last pat comptes ERROR(:) based on Eq. (). All comptations ae done withot bffe and latency. Finally, the EP block eqies AND gates, OR gates and 8 NOT gates. Fige Block diagam of EP.

10 RTL Design of BCH (,) Decode... Eo Possibility (EP) Eo detection in this gop is pefomed based on the code gop and syndome S. Thee ae possible eo positions in this gop. The detection concept consists of thee steps. Fist, the code gop is sed to geneate a maimm of nine candidates in tem of syndome Ŝ. Net, all possible combinations of the syndome Ŝcandidates ae pepaed and compaed with the actal syndome S. As a eslt, a syndome Ŝ candidate that has the same patten as the actal syndome S is ecognized. Finally, this eslt is conveted to the eo position, within to. The geneal achitecte of EP detection is shown in Fige. Each step is eplained in detail below. Syndome S ( ) Comp_ot( ) Comp_ot( ) same_ind Step CG( ) Step Comp_ot Comp_ot Comp_ot Comp_ot Comp_ot Comp_ot Comp_ot( 8) Comp_ot( 8) Step Ot_pos Ot_pos Fige Geneal achitecte of EP. The main pocess of Step is to geneate all Ŝ candidates based on the eceived code gop (CG). A maimm of two gops can be detected at the same time, whee each gop belongs to thee Ŝ candidates; a maimm of nine Ŝ candidate combinations ae podced in the Step block. The Ŝ candidates ae based on Table. They ae: CGŜ =,, CGŜ =,, CGŜ =,, CGŜ =,, CGŜ =,,. Note that S, S and Ŝ have the same configation, whee the most left is the least significant bit (LSB e.g. S()) and the most ight is the most significant bit (MSB e.g. S()).

11 Henda Setiawan Notice that one Ŝ occing in a CG is eqal to the XOR of two othe Ŝs. Theefoe, two Ŝs mst be mentioned in the pocess of Step. The details of the achitecte of Step ae shown in Fige ; it consists of ten selectos and a compaato to ecognize a single eo, since a single eo will give the same vale in both otpts. The ten bits on each selecto epesent two Ŝs (each bits) and a epesentative eo position ( bits). Patten CG = Patten CG = `` `` Patten CG = `` `` CG() Patten CG = `` `` CG() Patten CG = `` `` CG() `` `` CG() [:8] Comp_ot ( bits) CG() CG() Compaato Same ind CG() Patten CG = `` `` Patten CG = `` `` Patten CG = CG() `` `` Patten CG = CG() `` `` Patten CG = CG() Fige Detailed achitecte of Step. `` `` [:8] Comp_ot ( bits) The main pocess of Step consists of Ŝ combinations geneation and a compaison of Ŝ combinations with the actal syndome S. Since each CG contibtes thee Ŝs and thee is a maimm of two eos with a diffeent CG, the maimm nmbe of combinations is nine. Fo eample, the fist CG gives Ŝ = A, B, and C, and the othe CG gives Ŝ = A, B, and C. Theefoe, the combinations of Ŝ ae (A XOR A), (A XOR B), (A XOR C), (B XOR A), (B XOR B), (B XOR C), (C XOR A), (C XOR B) and (C XOR C). One of them shold be the same as the actal S. Fige 8 shows the details of the achitecte of Step. In Step, eo positions ae ecognized based on compaing the eslts of Step with a epesentative eo fom Step. A epesentative eo is the smallest eo position in each CG, fo eample, the epesentative eo in CGis. We can ecognize two othe eos becase they have a special patten, i.e.

12 RTL Design of BCH (,) Decode inteval five. Ths, when the epesentative eo is, the othe eos ae and. Howeve, to ecognize the actal eo, the otpt of Step has to be consideed. Comp_ot [:] S [:] [:] [:] Compae Comp_ot Compae Compae Comp_ot Comp_ot [:] Same ind [:] Compae Comp_ot [:] Compae Compae Comp_ot Compae Compae Comp_ot Compae Compae Comp_ot Fige 8 Detailed achitecte of Step. Fige 9 shows the achitecte of the pocess of Step, which consists of OR gates, addes and a selecto. The Step otpt is seved in -bit fomat. Howeve, the bit coection patten is in -bit fomat. Theefoe an EP decode is eqied. Ot_pos Comp_ot [:8] + << Comp_ot Comp_ot Comp_ot [:8] Comp_ot Comp_ot Same with above Ot_pos Same_ind Fige 9 Detailed achitecte of Step.

13 Henda Setiawan... EP Decode The fnction in this section convets EP otpt fom -bit fomat to the eo position within bits. These -bit pattens ae also called ERROR. The elationship between the two pot inpts (ot_pos and ot_pos) and the - bits ERROR is epessed as: ERROR() = ot_pos_ OR ot_pos_ ERROR() = ot_pos_ OR ot_pos_ ERROR() = ot_pos_ OR ot_pos_ ERROR() = ot_pos_ OR ot_pos_ ERROR() = ot_pos_ OR ot_pos_ ERROR() = ot_pos_ OR ot_pos_ ERROR() = ot_pos_ OR ot_pos_ ERROR() = ot_pos_ OR ot_pos_ ERROR(8) = ot_pos_ OR ot_pos_ ERROR(9) = ot_pos_ OR ot_pos_ ERROR()= ot_pos_ OR ot_pos_ ERROR()= ot_pos_ OR ot_pos_ ERROR()= ot_pos_ OR ot_pos_ ERROR()= ot_pos_ OR ot_pos_ ERROR()= ot_pos_ OR ot_pos_ () whee, ot_pos_ = (NOT ot_pos()) AND (NOT ot_pos()) AND (NOT ot_pos()) AND (NOT ot_pos()) ot_pos_ = (NOT ot_pos()) AND ot_pos() AND ot_pos() AND ot_pos() ot_pos_ = (NOT ot_pos()) AND (NOT ot_pos()) AND (NOT ot_pos()) AND (NOT ot_pos()) ot_pos_ = (NOT ot_pos()) AND ot_pos() AND ot_pos() AND ot_pos() Theefoe, it can be implemented sing a combinational cicit consisting of AND and OR gates. Some pats of this cicit ae shown in Fige.

14 RTL Design of BCH (,) Decode Ot_pos [:] [] ERROR[] ERROR[] [] ERROR[] [] [] ERROR[] Ot_pos [:] [] [] [] [] Fige Achitecte of the EP decode. Finally, the total compleity of EP and its decode is given in Table, consisting of two mltiplees, a compaato, XOR gates, OR gates, 9 AND gates, 8 NOT gates, and two addes. Table Compleity of EP and EP decode. Block Component Nmbe of gate Total nmbe of gate EP Step MUX = MUX = Compaato = Compaato = Step XOR = OR = AND = NOT = XOR = OR = AND = 9 NOT = 8 Step OR = MUX = Adde = Adde = EP decode EP decode AND = 8 NOT = 8 OR =.. Eo Coection The last step is eo coection. The main concept of the eo coection system is XOR-ing the eceived infomation with the patten coection bilt fom EP

15 Henda Setiawan and EP. Howeve, we mst also conside syndome S and S fo selecting coection pattens, which can be epessed as, whee,, wh e n S a n ds RBEC RBW E ERROR, wh e n S a n ds () RBW E ERROR, wh e n o t h e s RBEC = eceived bit eo coection, [:] RBWE = eceived bit with eo, [:] S, S = syndome S, S [:] ERROR = eo possibility, [:] ERROR = eo possibility, [:] = XOR opeation Theefoe, the implementation ses si OR gates and one XOR gate, as well as a mltiplee, as shown in Fige. S() S() S() S() S() S() [:] S() S() ERROR ERROR [:] [:] [:] [:] Received Bit (RBWE) [:] Eo Coection (RBEC) Fige Eo coection achitecte. Poposed Design Compleity In section, the poposed RTL design was pesented along with the compleity. Fthemoe, the total compleity of each block is e-typed and shown in table. Note that a mltiplee is eqal to logic gates, and a compaato is eqal to an adde and a logic gate.

16 RTL Design of BCH (,) Decode Table Total compleity of the poposed design. No. Block Compleity Logic gate Adde Syndome calclation - Colmn gop detection - EP detection - EP detection 88 EP decode - Eo coection - Total Based on the calclation shown in Table, the poposed BCH (,) decode needs logic gates and addes. We now conside a simple algoithm poposed by Hong [9] as a compae. Hong s algoithm fo -bit eos gives a eslt of in total mltiplies, eclding the othe components sch as addes. The mltiplies ae distibted sch that mltiplies ae sed fo syndome evalation, mltiplies fo the eo locato polynomial, mltiplies fo oot finding, and mltiplies fo eo evalation. Consideing a -bit mltiplie, its compleity is eqal to logic gates and an adde []. Ths, Hong s algoithm fo -bit eos is eqal to logic gates and addes. Theefoe, the poposed system has a lowe compleity than Hong s algoithm. Simlation, Compilation and Synthesis Reslts In ode to ense that the developed system has been woked ot popely, we did a veification based on the block diagam in Fige. All pats wee implemented in Vey High Hadwae Desciption Langage (VHDL) and simlated sing ModelSim.. A snapshot of the fnctional simlation is shown in Fige. It is clea that all eos can be ecoveed by the decode. Fige Block diagam fo veification.

17 8 Henda Setiawan Fige Snapshot of simlation eslt. Fthemoe, sing a clock peiod of ns, a long simlation was pefomed in seconds, o clock cycles. Within this peiod, the BCH decode eceived appoimately,, data. The eslt was that thee wee no eos, as shown in Fige, which means the bit eo ate was zeo, o all eceived bits wee coected pefectly. Fige Simlation snapshot of one million data. The compilation was pocessed sing design tool ISE.. The eslt shows that the citical path appeas fom egiste inpt RBWE() to egiste otpt RBEC(), as shown in the snapshot of the compilation eslt in Fige. This path is thogh syndome S, colmn gop detection, eo possibility, and the eo coection block. The citical path delay is 8. ns fo Vite FXTFF implementation. The citical path can be edced by pipelining. Withot pipelining the poposed design has a maimm clock feqency of. MHz. Since the comptation pocess is done in -bit paallel pocessing, the maimm thoghpt that can be achieved is. Gbps.

18 RTL Design of BCH (,) Decode 9 Fige Snapshot of the timing epot. Fom a cicit aea point of view, the poposed achitecte of the BCH (,) decode eqies slice LUTs withot flip-flop, as shown in Fige. Since all components ae made fom a combinational cicit, thee ae no seqential components sch as a egiste o a memoy. Ths, clock latency is zeo. Fige Snapshot of the esoce smmay. The. Gbps thoghpt is highe than the decode achitecte poposed by A. Kma, et.al. [], which can each a data ate of p to. Gbps with a maimm clock of MHz in an application-specific integated cicit (ASIC) implementation. In addition, the poposed system has no latency since no seqential cicit is inclded. The decode poposed by A. Kma, et.al. [] has a clock latency of 8. Ths, the poposed system has a lowe latency than Kma s decode.

19 Henda Setiawan Conclsions We have designed a BCH (,) hadwae implementation in a combinational cicit instead of a seqential cicit to avoid high comptation eqiements and iteation pocesses. The simlation eslts sing ModelSim. show that the developed cicit has coect fnctional pocesses. Fthemoe, based on the compilation and synthesis eslts, the BCH decode occpies LUTs ot of the 8 LUTs on the taget device Vite FXTFF. The citical path delay is 8. ns in -bit paallel pocessing. Ths the maimm thoghpt can each. Gbps. Since seqential cicits ae no longe involved, thee is no pocess latency and the otpt can be eected in one clock cycle. Refeences [] Costello J., D.J., Hangenae, J., Imai, H. & Wicke, S.B., Applications of Eo Contol Coding, IEEE Tansactions on Infomation Theoy, (), pp. -, Oct [] ETSI, Digital Video Boadcasting (DVB); Fame Stcte Channel Coding and Modlation fo A Second Geneation Digital Teestial Television Boadcasting System (DVB-T), Eopean Std. ETSI EN, V.., Sept. 9. [] IEEE, Pat : Ai Inteface fo Fied and Mobile Boadband Wieless Access Systems, IEEE Std. 8.e-, Feb.. [] Lin, S. & Costello J., D.J., Eo Contol Coding, Pentice Hall,. [] Massey, J., Step By Step Decoding of The Bose Chadhi Hocqenghem Codes, IEEE Tansactions on Infomation Theoy, (), pp. 8-8, Oct. 9. [] Szwaja, Z., On Step By Step Decoding of The BCH Binay Codes, IEEE Tansactions on Infomation Theoy, (), pp.-, Ap. 9 [] Wei, S.W. & Wei, C.H., A High Speed Real Time Binay BCH Decode, IEEE Tansactions on Cicits and Systems fo Video Technology, (), pp.8-, Apil 99. [8] Massey, J.L., Shift-Registe Synthesis and BCH Decoding, IEEE Tansactions on Infomation Theoy, (), pp. -, Jan.99. [9] Hong, J. & Vetteli, M., Simple Algoithms fo BCH Decoding, IEEE Tansactions on Commnications, (8), pp. -, Ag. 99. [] Cate, N., Scham s Otlines of Theoy and Poblems of Compte Achitecte, Indian Special Edition, McGaw Hill,. [] Kma, A. & Sawitzki, S., High-Thoghpt and Low-Powe Achitectes fo Reed Solomon Decode, Poc. of IEEE 9 th Asiloma Confeence on Signal, Systems, and Comptes, pp.99-99, Nov..