THE ENERGY BALANCE ERROR FOR CIRCUIT TRANSIENT ANALYSIS

Transcription

1 THE ENERGY BALANCE ERROR FOR CIRCUIT TRANSIENT ANALYSIS FLORIN CONSTANTINESCU, ALEXANDRU GABRIEL GHEORGHE, MIRUNA NIŢESCU Key words: Trasiet aalysis, Eergy balace error, Time step coice. Two algoritms for te time step coice implemeted i circuit simulators are aalyzed. A ew error ad a ew time step coice algoritm are proposed. A example is give for illustratio.. INTRODUCTION Te time step magitude i trasiet aalysis of electrical circuits is cose depedig o certai errors. I SPICE-like circuit simulators (SPICE, PSPICE, HSPICE, SPECTRE, SPECTRE RF) te local trucatio error (LTE) is used for eac state variable ad its time derivative. Te LTE is estimated i te worst case correspodig to a relative error ε r ad to a absolute error ε a. For example, te error of te time derivative of a state variable is: ε = εr max x+, x +εa, x () were x + is te curret troug a capacitor or te voltage of a iductor. A similar error is defied for x. For eac time step, te maximum allowed LTE is give by: E = max( ε, ε & ). (2) Startig from tis value, a maximum time step is computed as: Rev. Roum. Sci. Tec. Électrotec. et Éerg., 55, 3, p , Bucarest, 200 x x d 3 x 6E. dt 3 (3) Tis algoritm for time step computatio ca be outlied as follows []: Politeica Uiversity of Bucarest, Departmet of Electrical Egieerig, flori.costatiescu@lce.pub.ro

2 244 Flori Costatiescu, Alexadru Gabriel George, Mirua Niţescu 2 t + = t + solve for t if iter_um <ITL4 compute + = f ( LTE) if + < 0. 9 te reject t = + compute for te ew t else accept t + = mi( +,2, TMAX ) cotiue wit t + 2 else reject t = 8 reduce itegratio order to (BE) if ( > mi ) te compute for te ew t else prit TIME STEP TOO SMALL; aalysis is aborted were te itegratio metod is trapezoidal ad ca be caged to backward Euler (BE), TMAX is te fial time, iter_um is te curret iteratio umber ad ITL4 is te maximum iteratio umber. Te mai drawback of tis algoritm is te relatio (3) wic is based o te remaider estimatio i Taylor formula [2]. Te LTE of te trapezoidal algoritm 3 is estimated as x ''' () τ, were τ is a ukow value i te viciity of t +. 2 Moreover, te tird derivative ca oly be approximated kowig oly te sample values give by a umerical metod (te form of te solutio betwee te samples is ot kow). Aoter algoritm for time step coice, based o a eergy error, is proposed i [3]. Te eergy accumulated by a oliear capacitor i te time step [t j, t j+ ] ca be computed exactly as:

3 3 Te eergy balace error for circuit trasiet aalysis 245 vj + dq E j E = + j vdv, (4) dt were q is te capacitor carge, v j is te capacitor voltage at t j ad v j+ is te capacitor voltage at t j+. For tis capacitor, te eergy balace i tis time step is te differece betwee te accumulated eergy ad te eergy fed by circuit ito capacitor: vj t j + t j ( ) ( ) E = Ej+ Ej i τ v τ d, τ (5) were i is te capacitor curret. If E 0, te itegratio algoritm gives a erroeous estimate of te solutio. Obviously lim E = 0. j + 0 Wile te accumulated eergy depeds oly o v j ad v j+, te eergy fed by circuit ito capacitor depeds o te fuctios i( τ ) ad v( τ ) also. A algoritm for te computatio of te time step based o E cotrol is developed i [3]. Te maximum allowed E j+ i te time iterval [t j, t j+ ] is computed i a similar maer to (): E ε E ε j+ < r j + a. (6) Te time step j+ is computed solvig a optimizatio problem wose costraits are te relatios (6) for all dyamic elemets ad j+ >0. Te actual implemetatio of tis algoritm i te circuit simulator PAN, available freely o [4], uses a cut ad try mecaism similar to te SPICE oe [5]. Some tests o becmark circuits proved tat PAN trasiet aalysis ca be up to a order of magitude faster ta tat of SPICE or SPECTRE [6]. Tere are two reasos explaiig tese results: Te LTE approac is aimed to cotrol te error wit wic te circuit state equatios x& = Ax + b( t) are verified, but A ad b(t) are ot available i a circuit simulator; tat s wy te SPICE approac imposes some errors for te computatio of all magitudes x ad x& witout ay coectio to teir weigtigs give by A ad wic are related to te circuit structure; te eergy balace for eac dyamic circuit elemet is more efficiet because it takes partially ito accout te circuit structure.

4 246 Flori Costatiescu, Alexadru Gabriel George, Mirua Niţescu 4 Te umerical evaluatio of tird order derivatives ca lead to erroeous results, wic, i tur, ca force te algoritm to coose smaller values of te time step ta are really eeded to verify circuit equatios. Te mai idea of tis paper is to go furter takig totally ito accout te circuit structure ad usig te eergy balace error for te wole circuit. Tis approac is discussed i Sectio 2, togeter wit a algoritm for te time step coice. A example is preseted Sectio 3, wile Sectio 4 cotais coclusios ad future work. 2. ENERGY BALANCE ERROR AND CHOICE OF THE TIME STEP For eac dyamic elemet te eergy fed ito it is defied so tat for a liear capacitor we ave: ( t ) ( t ) t t ( τ) t t+ du EC = u( τ) i( τ) dτ= u( τ) C dτ= dt u + C C = C u u = u t u t = u u 2 2 ad for a liear iductor we ave: u ( ) ( ) ( + ) d, ( τ) ( ) it+ t t+ di EL = u( τ) i( τ) dτ= L i( τ) dτ= L idi dt = t t i( t) L 2 2 L 2 2 = i ( t) i ( t) = ( i+ i ). 2 2 A umerical metod gives oly te sample values for certai values of time, te form of te fuctio betwee samples beig ukow. To compute te eergy fed ito resistors ad sources, teir voltages ad currets are cosidered as liear or quadratic fuctios of time i te iterval [t j, t j+ ]. Tis approximatio ca lead to errors i eergy computatio. Te absolute eergy balace error is defied as: a k = ad te relative eergy balace error is defied as: k (7) (8) E = E, (9)

5 5 Te eergy balace error for circuit trasiet aalysis 247 E k k = r, MAX( Ek ) E = were is te umber of circuit elemets icludig sources ad MAX(E k ) gives te eergy wit te maximum module. Te time step is cose computig ad te assumed time step is accepted if E r EER, were EER is te imposed relative eergy balace error margi. Te algoritm for te time step coice ca be outlied as follows: t = t + + solve for t compute Er if E r < EER 0 accept t = 2 + = mi +, ( TMAX ) cotiue else if EER 0 < Er < EER (0) accept t + + = cotiue else if E r > EER reject t + = 2 if + < H mi prit TIME STEP TOO SMALL; aalysis is aborted Te algoritm based o te relative eergy balace error i a time step guaratees a relative eergy balace error less ta te imposed value EER o te wole time iterval (from t start to t stop ). Tis is a global estimate of te correctess of te trasiet aalysis for te wole circuit ad for te wole time iterval. Tis algoritm as bee implemeted i C ad was tested o liear circuits wit damped oscillatory resposes. For a similar level of imposed errors it was foud tat tis implemetatio of te proposed algoritm rejects a smaller umber of time steps ta te SPICE algoritm, te umber of te accepted time steps beig similar.

6 248 Flori Costatiescu, Alexadru Gabriel George, Mirua Niţescu 6 3. EXAMPLE Te circuit i Fig. was aalyzed startig from a iitial coditio cose so tat to give a damped oscillatory respose. Tis circuit is drive by a siusoidal voltage of V ad MHz. I order to compare te results of SPICE ad of te proposed algoritm, two cases were take ito accout. Te voltage of te capacitor C is give i Fig. 2 for te first case. Te parameters of te aalyses ave bee cose so tat te ig frequecy detail is almost idetical (Fig. 4). Te parameters of te SPICE aalysis ad of te proposed algoritm are give i Table. Fig. Liear circuit wit damped oscillatory respose. Fig. 2 Te circuit respose i te first case.

7 7 Te eergy balace error for circuit trasiet aalysis 249 Table Algoritm Errors Accepted Rejected steps steps SPICE reltol = e 4, abstol = e proposed ERR = 0.6e Fig. 3 Te circuit respose i te secod case. Fig. 4 Te circuit respose i te secod case (ig frequecy detail). Te iitial coditios are v C = V, v C = V, i L = 0 A. Te secod case uses smaller error margis. Te circuit respose is give i Fig. 3 ad Fig. 4, wile te parameters of te aalyses are give i Table 2. Algoritm Errors Table 2 Accepted steps Rejected steps SPICE Reltol = 2e 6, abstol = e 5 proposed ERR = 0.6e I bot first ad secod cases it ca be observed tat te proposed algoritm rejects fewer steps ta te SPICE oe, te umber of accepted steps beig similar. Te similar umber of accepted steps follows from te coditio of similar accuracy wic must be esured i order to compare te two algoritms. 4. CONCLUSIONS A ew error for trasiet aalysis of electrical circuits is proposed i tis paper. A ew algoritm for time step coice usig tis error as bee developed. Some prelimiary tests sow tat for a similar umber of accepted steps (wic

8 250 Flori Costatiescu, Alexadru Gabriel George, Mirua Niţescu 8 leads to a similar form of te trasiet respose), te proposed algoritm rejects fewer steps ta te SPICE algoritm. Future work will be devoted to compariso wit aalytical solutios, ivestigatio of te frequecy warpig peomeo i ig Q circuits, ad adaptive algoritms for time step coice. ACKNOWLEDGMENT Te autors would like to tak prof. Agelo Brambilla from Politecico di Milao ad prof. Miai Iordace from Politeica Uiversity, Bucarest, for elpful discussios. Tis work as bee supported by te CNCSIS project ID_297 New metods for time domai ad frequecy domai circuit aalysis. Received o 28 November, 2009 REFERENCES. W. Nagel, SPICE2: A computer program to simulate semicoductor circuits, Memoradum No. UCB/ERL M520, L. O. Cua, P. M.Li, Computer aided aalysis of electroic circuits, Pretice Hall, A. Brambilla, D. A Amore, Eergy-Based Cotrol of Numerical Errors i Time-Domai Simulatio of Dyamic Circuits, IEEE Trasactios o Circuits Ad Systems I: Fudametal Teory Ad Applicatios, 48, 5, May ttp://brambilla.elet.polimi.it 5. A. Brambilla, Private commuicatio, Marc F. Costatiescu, A. G. George, Mirua Niţescu, Large sigal aalysis of RF circuits a overview, Proceedigs of ATEE, 2006.