An Efficient Digital Circuit for Implementing Sequence Alignment Algorithm

Transcription

1 An Efficien Digil Circui for Implemening Sequence Alignmen Algorihm Vmsi Kundei Yunsi Fei CSE Deprmen ECE Deprmen Universiy of Connecicu Universiy of Connecicu Sorrs,CT Sorrs,CT Absrc The problem of Sequence Alignmen (Edi Disnce) beween pir of srings hs been well sudied in he field of compuing lgorihms. The clssic dynmic progrmming-bsed lgorihm, Needlemn- Wunsch (O(n )), is widely used in prcice, especilly pplied in he field of Biology. Biologiss use his lgorihm immensely o find similriies beween gene sequences. Any opimizion in he implemenion of his lgorihm will hve significn prcicl impc on Biologicl reserch. However, even fer severl decdes from he ime Needlemn-Wunsch s lgorihm ws published (in 1970s), no much hs been done in improving he runime of he lgorihm in rel implemenions. In view of his, we propose n efficien hrdwre implemenion of he Sequence Alignmen lgorihm o speedup he lgorihm runime. To he bes of our knowledge, his is he firs hrdwre implemenion of he Sequence Alignmen lgorihm. The experimenl resuls show h our circui implemenion cn chieve wo orders of mginude speedup compred wih he sofwre counerpr, menwhile reducing he re cos. 1 Inroducion Compuing he EdiDisnce [5] beween wo srings is one of he mos fundmenl problem in compuer science. Algorihms bsed on edi disnce re used immensely in ligning biologicl sequences. The sndrd dynmic progrmming-bsed Needlemn-Wunsch lgorihm kes O(n ) ime o compue he edi disnce of wo srings, S 1 = [ 1,, 3,..., n ] nd S = [b 1,b,b 3,...,b n ], nd O(n ) spce o compue he cul edi scrip (symbolic rnsformion from S 1 o S ). This lgorihm hs being widely used in prcice, especilly in biologicl sequence lignmen. Any improvemens eiher in ime or spce for he compuion of his lgorihm will hve significn impc on he biologicl reserch. However, in he ls few decdes no much hs been done in improving he performnce of sofwre implemenion of he lgorihm. The sympoic runime of he lgorihm remins O(n ), lhough here hs been some work producing O( n log(n) ) lgorihm [4], which hs been purely heoreicl resul nd did no find plce in rel sofwre implemenions. In view of his, we propose hrdwre implemenion of his fundmenl EdiDisnce lgorihm which could help speeding up ll sequence lignmen operions. In his pper, we presen n efficien circui design for he lgorihm. To he bes of our knowledge, our hrdwre implmenion is he firs one for he dynmic progrmming-bsed Sequence Alignmen lgorihm. Sequence Alignmen is used exensively by biologiss o idenify similriies beween genes of differen species, wih genes being chrecerized by DNA sequence (sring of chrcers), e.g., S dn = [c 1,c,c 3,...], c i A,T,G,C, where A, T, G, nd C re symbols for mino cids (lso clled bse pirs). These DNA sequences re very long, ypiclly running ino millions of bse pirs. Biologiss ofen nlyze he funcionliy of newly discovered genes by compring hem o genes which were lredy discovered nd whose funcion is fully known. Given wo DNA sequences, Sdn new nd Sknown dn, biologiss perform sequence lignmen (EdiDisnce compuion) beween he wo sequences o find if hey hve he sme funcionliy. If he EdiDisnce vlue is below hreshold ǫ, boh he DNA sequences (genes) hve some properies in common; oherwise hey differ. BLAST (Bsic Locl Algorihm Serch Tool) is he mos populr sequence lignmen ool currenly used by biologiss [3]. EdiDisnce lgorihm is fundmenl building block on which he BLAST progrm is buil, nd he lengh of DNA sequences is mjor concern for compuion since he lgorihm kes O(n ) ime. As he size of he DNA sequences rech millions of bse pirs, compuing he EdiDisnce relly suffers in performnce. To overcome his problem, BLAST uses heurisic which breks up he long DNA sequences ino smller segmens nd compues he EdiDisnce beween he 1

2 broken segmens nd pus hese segmens ogeher. As EdiDisnce compuion beween pir of srings is fundmenl operion on which severl fmilies of sequence lignmen lgorihms re buil, implemening his fundmenl operion in hrdwre would speed up ll he compuions in sofwre nd help in scling he sofwre o hndle longer DNA sequences in lesser ime. This is he mjor moivion for our hrdwre implemenion of EdiDisnce. The orgnizion of he pper is s follows. Secion formlly defines he EdiDisnce problem. In Secion 3, we briefly describe he dynmic progrmming bsed sofwre lgorihm. We describe our hrdwre implemenion of RTL srucures in deils in Secion 4. Secion 5 presenes he simulion resuls. Finlly, we drw conclusions in Secion 6. Problem Definiion Assume we hve wo srings, S 1 = [ 1,, 3,..., n ] nd S = [b 1,b,b 3,...,b m ], nd se of operions {Inser(I), Delee(D), Chnge(C)}, ech of he operions I,D,C cn be pplied o he chrcers in he srings given posiion. For exmple, if S 1 = [bcd] nd S = [bcd], pplying n operion D o he sring S 1 posiion 8 (he righmos chrcer) chnges i o [bcd ], pplying n operion I(x) o S posiion 8 insers chrcer x o S nd chnges i o [bcdx], nd pplying n operion C(b) o S 1 posiion 4 which hs chrcer mkes i [bbcd] by chnging he chrcer from o b. Noe h ech of he operions needs he posiion specified for operion, nd I nd C need n ddiionl chrcer for replcemen. The EdiDisnce problem sks for he minimum number of operions required o rnsform sring S 1 o S (or S o S 1 ). A more generl specificion of he problem ssocies cos wih ech of he operions, nd sks for se of operions wih minimum cos which cn rnsform S 1 o S. In his pper, we consider simplified problem, where ech of hese operions (I,D,C) hs uni cos, nd hence minimizing he number of operions is equivlen o minimizing he cos. We consider he previous exmple wih S 1 = [bcd], S = [bcd], nd we cn rnsform S 1 o S by sequence of operions s follows: chnge chrcer posiion 4, b posiion 5, nd c posiion 6 of S 1 o b, c nd, respecively, by operions C(b), C(c), nd C(). We cn briefly describe he series of operions s rnscrip T = {,,,C(b),C(c),C(),, }, where posiions 1,, 3, 7, 8 indices no-operion, nd he 3 operions posiions 4, 5, 6 resul in cos of 3 unis. However, we cn lso rnsform S 1 o S by pplying he following rnscrip T o S 1, T = {,,,D,,,I(),, }, where operion D delees he chrcer posiion 4 of S 1, nd operion I() insers chrcer posiion 7 in S 1. T requires only operions wheres T requires 3 operions. The EdiDisnce problem sks o find he minimum number of operions which cn rnsform S 1 o S. 3 Sofwre Algorihm Descripion The widely used lgorihm for compuing he edi disnce of wo srings is bsed on dynmic progrming. Algorihm 1 demonsres he pseudo-code for he lgorihm of EdiDisnce implemened in sofwre. We re compuing n rry of edi disnce, D, beween subses of he wo srings, i.e., D(i,j) is he edi disnce from he firs i chrcers of S 1 o he firs j chrers of S, nd D(n,n) is he minimum number of operions o rnsform S 1 o S. The firs sep is iniilizion, giving he edi disnce from NULL o subses of S (D(0,i) = i), nd subses of S1 o NULL (D(i,0) = i). The compuion of oher rry elemens is performed by wo loops which compue he vlue of D(i,j) (1 i n,1 j n). I comes from he minimum one of hree coss: D(i-1,j-1)+chnge cos for chnging he ls chrcer of S 1 when he firs i 1 chrcers of S 1 hve been successfully rnsformed o he firs j 1 chrcers in S, D(i,j-1)+inser cos for insering he ls chrcer when he firs i chrcers of S 1 rnsformed o he firs j 1 chrcers of S, nd D(i-1,j)+delee cos for deleing i h chrcer of S 1 when he firs i 1 chrcers of S 1 hve been rnsformed o he firs j chrcers of S. Noe h he inser cos nd delee cos re boh consn uni cos, nd he chnge cos is condiionlly deermined by he ls chrcers of he wo srings - only when hey re differen, here is need for chnge operion. 4 Hrdwre Implemenion of he EdiDisnce Algorihm In his secion, we describe our efficien hrdwre implemenion of he EdiDisnce lgorihm. For he core compuion of D(i,j) by wo loops, he ble D n n is filled up row by row. Le D(i, ) represen he i h row in he ble D. To fill up his row, we need he row of D(i 1, ) ny sge of he lgorihm. Thus, srigh forwrd implemenion my sve he enire row D(i 1, ) ino regiser R 1 of size n, hen use noher regiser R of size n o compue D(i, ). Once we re done wih he i h row, we copy he conens of R o R 1 nd coninue

3 INPUT : Srings S 1 nd S ech of size n OUTPUT: Minimum number of operions o rnsform S 1 o S /*Iniilizion*/ for i = 1 o n do D(0,i) = i ; D(i,0) = i ; /*Recursive Compuion of he Disnce Tble D*/ for i = 1 o n do for j = 1 o n do chnge cos = 0; if S 1 [i] S [j] hen chnge cos = 1; D(i,j) = MIN(D(i 1,j 1) + chnge cos,d(i,j 1) + 1,D(i 1,j) + 1) ; reurn D(n,n) ; Algorihm 1: Pseudo-code for he lgorihm of EdiDisnce compuion unil he finl row of D (i.e., D(n, )) is obined. This mehod would require spce of n in ddiion o he iniilizion spce of n + 1 for D(0, ) nd D(,0), nd lso i is oo complex o synhesize ino hrdwre. One mjor conribuion of his pper is o propose n efficien synhesizble design, which requires only spce of n + o compue he row D(i, ) from he row D(i 1, ) ny sge of he lgorihm. Our design is hierrchicl nd he op level block digrm is shown in Figure 1. The circui is sequenil nd consiss of four mjor blocks CompueBlock, AlgoShifer, CounerBlock, nd SringRegiser. In he nex severl secions we describe he funcionliy of ech of hese blocks. 4.1 Design Block AlgoShifer The block AlgoShifer is he core block in which ll he rows D(i, ) re compued efficienly during he lgorihm wih only spce of n +. Given wo srings of lengh n, he mximum edi disnce (cos of lignmen) beween hem would be mos n. Hence, we need log(n) bis o represen he edi disnce ny sge of he lgorihm, nd row of size n + 1, i.e., D(i,j), 0 j n, would need (n + 1)log(n) bis (flipflops) o represen. Figure illusres he inernl S i [i] INPUT: S 1 S index_i ou1 S [j] SringRegiser ou AlgoShifer CompueBlock rese ou3 SringRegiser shif_inpu index_j CounerBlock OUTPUT: EdiDisnce(S Figure 1. Top level block digrm of he circui deils of he AlgoShifer block. I conins shif regiser of size n +, S, which hs (n + )log(n) bis in ol. Le S[i] denoe he i h elemen h is log(n) bis sring from posiion ilog(n), S[0] represen he firs elemen, nd S[n + 1] he ls. The block hs wo conrol inpu signls, nd rese, wo log(n)-bi d inpus, shif inpu nd rese inpu, nd hree log(n)-bi d oupus, ou1, ou, nd ou3, which represen he conens of shif regiser S S[0], S[1], nd S[n + 1]. log(n) bis ou1 ou rese ShifRegiser(S) size = n+1 shif_inpu rese_inpu ou3 Figure. Inernl deils of block AlgoShifer The block AlgoShifer performs he following funcions. A every posiive edge of he clock conrol signl (), n inpu beween shif inpu nd rese inpu is chosen by he muliplexer nd he conrol signl rese o feed he lef shifer (shif lengh is log(n)). The oupus, ou1, ou nd ou3, re he vlues of he firs, second nd ls elemens of he shif regiser S, which re used by he CompueBlock block, s shown in Figure 1. We nex exmine how his shif regiser is used in 1,S ) 3

4 implemening Algorihm 1. We ke he exmple in which row D(1, ) needs o be filled up from D(0, ). The conens of D(0, ) = [0,1,,...,n], nd we need o compue D(1,j) (1 j n) one by one. We firs check how D(1, 1) is compued. Three inpus re needed for he MIN funcion in he code of Algorihm 1, which in his cse re D(0,0), D(0,1), nd D(1,0). We hve known D(0, ) nd D(1,0) = 1 from he iniilizion. We ssume h he firs n elemens of he shif regiser, S[0],S[1],...,S[n], re filled wih conens from row D(0, ); nd S[n + 1] conins D(1, 0). Wih his configurion, he vlues of D(0,0), D(0,1), nd D(1,0) re vilble S[0], S[1], nd S[n + 1] o be used o compue he vlue of D(1,1). Once D(1,1) hs been compued (sy, wih vlue of X 1 ), he block proceeds o compue D(1,), which needs D(0,1), D(0,) nd D(1,1) his sge. I is cler h for furher compuion of D(1,j) (j > ), he vlue of D(0,0) is no needed ny more. Thus, fer ech compuion, we shif ou he vlue in he shifer regiser which is no necessry for furher compuion (e.g., D(0, 0) - S[0] in his cse), nd shif in he vlue jus compued which will be needed by furher compuions (e.g., D(1,1)). In he bove exmple, he iniil conen of he shif regiser is S = [0,1,,...,n,1]. Afer D(1,1) is compued (wih vlue X 1 ) nd shif operion performed, S becomes [1,,...,n,1,X 1 ]. Afer noher sep, S = [,3,...,n,1,X 1,X ], where X is he compued vlue of D(1, ). Wih n seps of compuion nd shifing, S = [n,x 1,...,X n ], where (X 1,X,X 3,...,X n ) corresponds o (D(1,1),D(1,),D(1,3),...,D(1,n)). Hence, in his exmple, we hve compued D(1, ) from D(0, ). We pply he sme mehod ierively nd re ble o compue ll he rows in D. Nex, we furher generlize he usge of he block. Assume h he shif regiser(s) conins row D(i, ) wih he configurion of S = [D(i,0),D(i,1),D(i,),...,D(i,n),D(i+1,0)], fer n shif operions long wih compuions of D(i + 1, k) (k 1) s described bove, he conen of he shif regiser becomes S = [D(i,n),D(i+1,0),D(i+1,1),D(i+ 1,),...,D(i+1,n)]. Before he nex row of D(i+, ) is compued, one more shif operion is needed. Wih D(i+,0) shifed in nd D(i,n) ou, he hree oupus of S[0], S[1], nd S[n+1] provide he vlues needed o compue D(i +,1), i.e., D(i + 1,0), D(i + 1,1), nd D(i+, 0). Since D(i+, 0) is from he iniilizion in sed of on-he-fly compuion, conrol signl rese needs o be se. When rese is no se, norml shif hppens every posiive edge of o shif in he newly compued D[i, j] vlue. Noe h he conrol signl of rese is se every n seps by CounerBlock, which we describe in he nex few secions. Figure 3 shows he operion of he shifer in one clock cycle. 4. Design Block CompueBlock A ech lgorihm sge, he block CompueBlock is o compue he vlue of D(i,j) bsed on hree vlues, D(i 1,j 1),D(i 1,j), nd D(i,j 1), which re obined from he AlgoShifer block oupus ou1, ou, nd ou3. In ddiion ohe inpus of D, he CompuBlock needs he chrcers in he srings posiions i of S 1 nd j of S (provided by wo SringRegiser blocks) o deermine he chnge cos. Figure 4 shows he inernl deils of CompueBlock. The block is relized by using XOR ge for he compuion of chnge cos, wo dders for he operion coss for differen cses, nd wo insnces of MIN Compror which compres wo inpus nd oupus he minimum one. S 1 [i] XOR Adder S [j] ou1 1 MIN Compror Adder ou shif_inpu MIN Compror ou3 Figure 4. Inernl deils of CompueBlock 4.3 Design Block SringRegiser A ech compuion sge, CompueBlock requires wo chrcers posiions i nd j in he wo srings S 1 nd S. The SringRegiser block is o ke n index s inpu nd oupus he chrcer he corresponding posiion in he sring. This block cn be relized using N-1 muliplexer wih index s he conrol inpu nd chrcers in he sring s he d inpus, s shown in Figure 5. The mux conrol inpu, index, is genered from he conrol block CounerBlock, which we will explin nex. 4.4 Design Block CounerBlock CounerBlock is he block which generes he conrol signls of rese nd index (index i for S 1 nd index j for S ), nd rese inpu o he AlgoShifer block. Figure 6 shows he inernl deils of he CounerBlock. We implemen wo couners of log(n) bis, C 1 nd C, 4

5 b c d b c d Iniilil vlues in he shifer (S) Vlues in D ye o be compued Inpu o CompueBlock (0,1,1,,) b c d b c d Vlues from previous sge sill in (S) Oupu of CompueBlock shifing ino (S) Redundn vlue shifed ou from (S) Figure 3. Operion of he shifer in firs clock cycle b c d b c d Vlues in (S) o be used in nex sge Discrded vlue Inpu o CompueBlock (1,,0,,) Muliplexer 8n bi S[index] S (INPUT Sring) 8 bis log(n) bis index Figure 5. Inernl Deils of SringRegiser where couner C 1 is incremened on every posiive edge of he clock wih he mximum vlue of n, nd C is incremened whenever C 1 = 0, menwhile, he rese signl is se s well. The oupus of C 1 nd C re for index i nd index j respecively. When rese is se, he rese inpu is given by D(index i,0). index(i) mod(n+1) couner index_i 0 1 rese index(j) Accumulor index_j Figure 6. Inernl deils of CounerBlock 5 Verificion nd Experimens The circui design ws implemened in Verilog nd ws verified using Synopsys VCS (Verilog Compiler Simulor) []. The complee RTL code of his design cn be downloded from he uhor s webpge [1]. Afer funcionliy verificion, we used Cdence Encouner RTL compiler (rc) o synhesize he design wih TSMC 0.13um (CL3GFSG, fs.lib) sndrd cell librry. Tble1 illusres he re nd swiching power wih differen seings of clock period (T). All our iming experimens were performed by seing inpu dely for ll pors (excep clock) o 00ps nd oupu dely o 400ps. As he iming consrin becomes more sringen, boh he re cos nd dynmic power consumpion re incresing. The mximum frequency of he hrdwre implemenion is 1 GHz. 5.1 Speedup Esimion wih Hrdwre Implemenion In his secion, we will esime he possible speedup in he compuion wih hrdwre implemenion of he lgorihm. Wihou lossing generliy, le S 1, S be he inpu srings for which we need o compue he EdiDisnce, S 1 = S = n. M 1 is sndrd mchine which does no provide ny hrdwre implemenion of he EdiDisnce lgorihm, nd M is mchine which provides 8-bi hrdwre implemenion of EdiDisnce lgorihm. Since he inpu o he EdiDisnce problem re srings of rbirry lenghs we cnno fford o build hrdwre for such rbirry lenghs nd hence we hve o resric for only cerin fixed 8-bi implemenion in hrdwre. The Algorihm1 hs o be modified such h i cn use he -bi hrdwre implemenion vilble 5

6 Timing, Are, Power Clock Period(ps) Slck(ps) #of ges Are Swiching Power(nW) Tble 1. Comprision of vrious design merics wih Clock Period(T) Tble compring cycles required Lengh of Sring cycles on M 1 M, = 8 M, = 16 M, = Tble. Esimed cycles required wih vrious hrdwre implemenions on M. On mchine M 1, he sympoic runime of Algorihm1 is O(n ), since Algorihm1 hs o fill up he dynmic progrmming ble (D n n ) elemen by elemen (D(i,j)). However, on mchine M which hs 8-bi EdiDisnce implemenion we cn fill up dynmic progrmming ble D in one hrdwre insrucion(which kes O( ) cycles). Algorihm 1 hs o be modified o compue he ble D n n block by block (D ) rher hn elemen by elemen, wih he size of ech block, we will only hve n blocks, so he ouer wo loops in he modified lgorihm only run n imes in conrs o n imes on mchine M 1, his is n dvnge on he M becuse he sofwre overhed(in minining he loops ec.) is now reduced by fcor of 1. We currenly esime he clock cycles required on mchine M wih 8-bi EdiDisnce implemenion s follows, we pproxime he overhed of he sofwre in he EdiDisnce o be proporionl o number of cycles required, le T sof be he clock cycles required on mchine M 1 hen T sof = Kn = (k 1 n ) (k ) for consns K,k 1,k, from our design number of clock cycles o compue -bi EdiDisnce is, he fcor (k 1 n ) in T sof cn be hough of conribued by he wo ouermos for loops running from 1 o n in he incremens of (i.e {i = 1;i <= n;i+ = }), from he preceeding discussion he modified lgorihm which uses 8-bi implemenion lso hve he similr loop srucure, so he number of clock cycles on M would be T hrd = (k 1 n ) ( ) nd finlly speedup = T sof T hrd = k. We deermined T hrd empiriclly finding ou how much ime he sofwre kes o execue he wo ouer mos forloops ({i = 1;i <= n;i+ = },{j = 1;j <= n;j+ = } les cll his T n clockperiod nd T hrd = (T n ) ( ). The Tble illusres he number of clock cycles required wih = 8,16,3, ll he experimens hve been performed on.4ghz penium mchine. 6 Conclusions In his pper we hve given efficien synhesizble Design for implemening he Sequence Alignmen(EdiDisce) lgorihm in hrdwre, which could speedup he compuion of EdiDisnce. References [1] Circui Design for EdiDisnce. [Suppressed for pper blind review.]. [] Synopsys Design nd Simulion Tools. [hp:// [3] S. F. Alschul, W. Gish, W. Miller, E. W. Myers, nd D. J. Lipmn. Bsic locl lignmen serch ool. J. Mol. Biol., 15: , [4] V. Arlzrov, E. Dinic, M. Kronrod, nd I. Frdzev. On economic consrucion of he rnsiive closure of direcred grph. In Dokl. Acd. Nuk SSSR., pges , [5] C. T. H., L. C. E., R. R. L., nd S. Clifford. Inroducion o Algorihms, Second Ediion. The MIT Press, Sepember 0. 6