Fast Multi-Domain Clock Skew Scheduling For Peak Current Reduction

Transcription

1 Fast Multi-Domai Clock Skew Schedulig For Peak Curret Reductio Shih-Hsu Huag, Chia-Mig Chag, ad Yow-Tyg Nieh Departmet of Electroic Egieerig Chug Yua Christia Uiversity Chug Li, Taiwa, R.O.C. Abstract - Give several specific clockig domais, the peak curret miimizatio problem ca be formulated as a 0- iteger liear program. However, if the umber of biary variables is large, the ru time is uacceptable. I this paper, we study the reductio of this high computatioal expese. Our approach icludes the followig two aspects. First, we derive the ASAP schedule ad the ALAP schedule to prue the redudacies without sacrificig the exactess (optimality) of the solutio. Secod, we propose a zoe-based schedulig algorithm to solve a large circuit heuristically. (2) For a large circuit, the umber of biary variables ad the umber of costraits are still very large eve though all the redudacies are prued. Thus, we propose a zoebased approach to solve a large circuit heuristically. Note that the proposed algorithms are idepedet of the used peak curret model. Therefore, i fact, our approach is a geeral methodology for the reductio of peak curret uder the costrait of multi-domai clock skew schedulig. II. Prelimiaries I. Itroductio It is well kow that the clock skew ca be utilized to shorte the clock period [] or reduce the peak curret [2]. However, it is very difficult to implemet a wide spectrum of dedicated clock delays. The architecture of multiple clockig domais [3] provides a alterative to ucostraied clock skew schedulig. Fishbur [4] preseted a polyomial time complexity algorithm to derive a multi-domai clock skew schedule for a target clock period. Ravidra, Keuhlma, ad Setovich [5] also studied the clock period miimizatio problem usig multiple clockig domais combied with small withidomai latecy. Vittal, Ha, Brewer ad Marek-Sadowska [6] used the 0- iteger liear programmig (ILP) formulatios to miimize the peak curret uder the costrait of multi-domai clock skew schedulig. Although their approach guaratees the optimality (i terms of the specified cost fuctio), the ru time of the 0- ILP solver grows dramatically with the icrease of biary variables. The high computatioal expese has limited the use of their approach. This paper presets a approach to overcomig the limitatio. Our approach icludes the followig two aspects: () We derive the ASAP (as-soo-as-possible) schedule ad the ALAP (as-late-as-possible) schedule of each register. As a result, we ca prue all the redudacies without sacrificig the exactess (optimality) of the solutio. Multi-domai clock skew schedulig oly uses discrete clockig domais: d, d 2, ad d. A clockig domai d k, where k =, 2, ad, correspods to a clock arrival time. Without loss of geerality, we assume that d d 2 d. The clock arrival time of each register must be oe of the clockig domais. Thus, the clock arrival time of register R i ca be represeted by biary variables: S i,, S i,2,, S i,, where S i,k is if ad oly if T Ci is equal to d k. For each register R i, we have S =. i,k k= For each data path R i R j, the double clockig costrait ca be rewritte as below: d S d S T ; k j,k k i,k PDi,j(mi) k= k= For each data path R i R j, the zero clockig costrait ca be rewritte as below: d S d S P T. k i,k k j,k PDi,j(max) k= k= The objective is to miimize the value peak_curret. Without loss of geerality ad for the coveiece of illustratio, i the followig, we assume that the total curret derivative at the clockig domai d k is r Si,k I i, where r deotes the umber of registers ad I i deotes the maximum possible curret of register R i caused by the clock edge. As a i=

2 result, for each clockig domai d k, the peak curret costrait is as below: r i= S i,k I peak_curret. i Thus, the peak curret miimizatio problem formulated by [6] has r+2s+ costraits, where s is the umber of data paths. Usig Fig. as a example, the circuit graph has 6 registers ad 0 data paths. Suppose that clock period P = 6 tu (time uits) ad I = I 2 = I 3 = I 4 = I 5 = I 6 = c. If the circuit is fully sychroous, a huge peak curret 6*c is observed at the clock edge. Assume that we are give 3 clockig domais: d = -2 tu, d 2 = 0 tu ad d 3 = 2 tu. If we directly use the 0- ILP formulatios as described i [6], the umber of biary variables is 6*3 = 8 ad the umber of costraits is 6+2*0+3 = 29. After solvig the 0- ILP formulatios, we fid that the peak curret is reduced to 2*c uder the multidomai clock skew schedule i which T C = d = -2 tu, T C2 = d 2 = 0 tu, T C3 = d = -2 tu, T C4 = d 3 = 2 tu, T C5 = d 2 = 0 tu, ad T C6 = d 3 = 2 tu. Give the clock arrival time x of a register, we defie the followig two fuctios: floor ad ceil. The fuctio floor(x) gives the latest clockig domai before the clock arrival time x; the fuctio ceil(x) gives the earliest clockig domai after the clock arrival time x. The pseudo codes of the two fuctios are show i Fig. 2 ad Fig. 3, respectively, where is the umber of clockig domais. Give a circuit graph G ad a target clock period P, the procedure OBTAIN_ASAP_ALAP is to fid a tight boud o the clock arrival time of each register. Let ASAP i ad ALAP i deote the allowable earliest clockig domai ad the allowable latest clockig domai of register R i, respectively. Thus, we say that [ASAP i,alap i ] is the allowable clockig rage of register R i. Iitially, we let the allowable clockig rage [ASAP i,alap i ] be [d,d ] for each register R i. The, by iteratively applyig the clockig costraits uder the target clock period P, we arrow the allowable clockig rage of each register. The repeat-util-loop iteratio repeats util the allowable clockig rage of each register is stable. Thus, the umber of repeat-util-loop iteratios is O(r*). Fig. 4 gives the pseudo code Fuctio floor(x) Fuctio ceil(x) for i = dowto do for i = to do if (x d i ) the retur(d i ); if (x d i ) the retur(d i ); retur(d ); retur(d ); Fig. 2: Fuctio floor. Fig. 3: Fuctio ceil. Fig. : Circuit graph example. III. The Approach Sectio 3. derives a ASAP schedule ad a ALAP schedule to prue the redudacies. Sectio 3.2 presets a zoe-based schedulig algorithm for large circuits. A. ASAP ad ALAP I fact, due to the zero clockig costraits ad the double clockig costraits, may biary variables used i the 0- ILP formulatios are defiitely to be 0. Therefore, a large fractio of the biary variables are redudat. Moreover, a large fractio of the costraits used i the 0- ILP formulatios are also redudat as they are implied by some of the other costraits. If these redudat biary variables ad redudat costraits ca be prued, the problem size ca be sigificatly reduced. Thus, our approach is to fid a tight boud o the clock arrival time of each register without sacrificig the exactess (optimality) of the solutio. Procedure OBTAIN_ASAP_ALAP(G,P) let [ASAP host,alap host ] be [0,0]; for each register R i do [ASAP i,alap i ] = [d,d ]; repeat update = 0; for each data path R i R j do apply clockig costraits i the forward directio to arrow the allowable clockig rage [ASAP j,alap j ]; if [ASAP j,alap j ] is arrowed the update = ; ed; for each data path R i R j do apply clockig costraits i the backward directio to arrow the allowable clockig rage [ASAP i,alap i ]; if [ASAP i,alap i ] is arrowed the update = ; ed util (update == 0); Fig. 4: Procedure OBTAIN_ASAP_ALAP.

3 There are two directios to apply the clockig costraits of data paths: forward directio ad backward directio. The first for-loop applies clockig costraits i the forward directio (i.e., i the directio of data path); ad the secod for-loop applies clockig costraits i the backward directio (i.e., agaist the directio of data path). Note that the sequece of data paths i each for-loop, which applies the clockig costraits, ca be arbitrarily specified without affectig the calculatio of ASAP schedule ad ALAP schedule. The details are described as below. () If the clockig costrait of data path R i R j is applied i the forward directio, the allowable clockig rage [ASAP j,alap j ] of register R j is arrowed uder the assumptio that the allowable clockig rage [ASAP i,alap i ] of register R i is fixed. As a result, we have: ASAP j = maximum(asap j,ceil(asap i +T PDi,j(max) -P)); ALAP j = miimum(alap j,floor(alap i +T PDi,j(mi) )). (2) If the clockig costrait of data path R i R j is applied i the backward directio, the allowable clockig rage [ASAP i,alap i ] of register R i is arrowed uder the assumptio that the allowable clockig rage [ASAP j,alap j ] of register R j is fixed. As a result, we have: ASAP i = maximum(asap i,ceil(asap j -T PDi,j(mi) )); ALAP i = miimum(alap i,floor(alap j +P-T PDi,j(max) )). Let s use the circuit graph show i Fig. as a example to demostrate the procedure OBTAIN_ASAP_ALAP. Suppose that clock period P = 6 tu, I = I 2 = I 3 = I 4 = I 5 = I 6 = c, ad we are give 3 clockig domais: d = -2 tu, d 2 = 0 tu ad d 3 = 2 tu. At the ig, we have [ASAP i,alap i ] = [-2,2] for each register R i where i =, 2, 3, 4, 5 ad 6. The, we eter the repeat-util-loop. We assume that the first for-loop (i.e., applyig clockig costraits i forward directio) tackles the data paths i the sequece of host R, host R 2, R R 2, R 2 R 3, R 2 R 5, R 3 R 4, R 4 R 5, ad R 5 R 6, ad the secod for-loop (i.e., applyig clockig costraits i backward directio) tackles the data paths i the sequece of R 6 host, R 5 host, R 5 R 6, R 4 R 5, R 3 R 4, R 2 R 5, R 2 R 3, ad R R 2. Table I gives the sapshot. The repeatutil-loop iteratio takes two times. The colum forward deotes the allowable clockig rage after the first for-loop is completed, ad the colum backward deotes the allowable clockig rage after the secod for-loop is completed. Table I. The sapshots of procedure OBTAIN_ASAP_ALAP. First repeat-util-loop Secod repeat-util-loop forward backward forward backward R [-2,0] [-2,0] [-2,0] [-2,0] R 2 [0,2] [0,0] [0,0] [0,0] R 3 [-2,2] [-2,0] [-2,0] [-2,0] R 4 [-2,2] [-2,2] [-2,2] [0,2] R 5 [-2,2] [-2,0] [0,0] [0,0] R 6 [-2,2] [-2,2] [0,2] [0,2] After the procedure OBTAIN_ASAP_ALAP is completed, we have [ASAP, ALAP ] = [-2,0], [ASAP 2,ALAP 2 ] = [0,0], [ASAP 3,ALAP 3 ] = [-2,0], [ASAP 4,ALAP 4 ] = [0,2], [ASAP 5,ALAP 5 ] = [0,0] ad [ASAP 6, ALAP 6 ] = [0,2]. Sice ASAP 2 = ALAP 2 = 0 tu ad ASAP 5 = ALAP 5 = 0 tu, we have T C2 = d 2 = 0 tu ad T C5 = d 2 = 0 tu. Thus, we oly eed to use 8 biary variables: S,, S,2, S 3,, S 3,2, S 4,2, S 4,3, S 6,2 ad S 6,3. Moreover, we ca use both the ASAP schedule ad the ALAP schedule to simplify the zero clockig costraits ad the double clockig costraits. For example, the double clockig costrait of the data path R R 2 ca be simplified to 2*S, T PD,2(mi) = 2 ad thus ca be easily justified as a redudat costrait. The justificatio of redudat costraits is i polyomial time complexity. By exploitig both the ASAP schedule ad the ALAP schedule, we fid that all zero clockig costraits ad all the double clockig costraits i this circuit graph become redudat. Cosequetly, the umber of costraits is reduced from 29 to 7. As a result, we ca rewrite the 0- ILP formulatios as below: miimize peak_curret S, + S,2 = ; S 3, + S 3,2 = ; S 4,2 + S 4,3 = ; S 6,2 + S 6,3 = ; S, *I +S 3, *I 3 peak_curret; S,2 *I +*I 2 +S 3,2 *I 3 +S 4,2 *I 4 +*I 5 +S 6,2 *I 6 peak_curret; S 4,3 *I 4 +S 6,3 *I 6 peak_curret; By applyig the 0- ILP solver, we have the results that S, =, S,2 = 0, S 3, =, S 3,2 = 0, S 4,2 = 0, S 4,3 =, S 6,2 = 0 ad S 6,3 =. I other words, the peak curret is 2*c uder the multi-domai clock skew schedule i which T C = d, T C2 = d 2, T C3 = d, T C4 = d 3, T C5 = d 2 ad T C6 = d 3. Clearly, both the umber of biary variables ad the umber of costraits are dramatically reduced without scarifyig the exactess of the solutio. B. Zoe-Based Schedulig For a large circuit, the umber of biary variables is still very large eve though all the redudat biary variables are prued. Give a circuit graph G ad a target clock period P, Fig. 5 gives the procedure ZONE_BASED_SCHEDULING to deal with a large circuit. At the ig, i additio to prue all the redudat biary variables, we also use the algorithm proposed i [4] to derive a feasible multi-domai clock skew schedule for the circuit graph G to work with clock period P. We let the feasible schedule be the iitial solutio. Note that the algorithm proposed i [4] does ot attempt to miimize the peak curret. The kerel of zoebased schedulig is a iteratio process of the procedure ZONE_PARTITION_SCHEDULING.

4 The procedure ZONE_PARTITION_SCHEDULING is to reduce the peak curret by re-schedulig the registers i the set RS. Fig. 6 gives the pseudo code. By specifyig the costrait o the maximum umber of biary variables i the ILP formulatios, we partitio the set of registers RS ito some sub-sets. Each sub-set is called a zoe. The philosophy of zoe partitioig is as below. Ituitively, if a register is associated with few biary variables, the flexibility i assigig its clock arrival time is limited. O the other had, if a register is associated with may biary variables, the flexibility i assigig its clock arrival time is very high. Therefore, i order to evely spread the currets over the clockig domais, a reasoable heuristic is to first re-schedule the registers that are associated fewer biary variables. Based o this philosophy, a zoe is created to accommodate as may registers as possible. The fewer associated biary variables, the higher priority (to be assiged ito the zoe) the register has. If the curret zoe caot accommodate ay more register (due to the limitatio o the maximum umber of biary variables), we create aother ew zoe. The iteratio of zoe creatio repeats util all the registers are assiged. Note that the earlier created zoe has a higher priority to be re-scheduled. Whe a zoe is re-scheduled, the clock arrival times of other registers are assumed to be fixed. Sice the maximum umber of biary variables withi a zoe is limited, the 0- ILP solver ca re-schedule each zoe efficietly. Procedure ZONE_BASED_SCHEDULING(G,P) prue all the redudat biary variables accordig to the results of the procedure OBTAIN_ASAP_ALAP(G,P); apply [4] to derive a feasible multi-domai clock skew schedule for the circuit graph G to work with clock period P; phase = ; RS = all the registers i the circuit graph G; call ZONE_PARTITION_SCHEDULING(phase,RS, G,P); phase = 2; repeat RS=all the registers scheduled ito hottest clockig domais; call ZONE_PARTITION_SCHEDULING(phase,RS,G,P); util (the peak curret caot be further reduce); Fig. 5: Procedure ZONE_BASED_SCHEDULING. I fact, the zoe-based schedulig uses two phases to apply the procedure ZONE_PARTITION_SCHEDULING as below. () The first phase is to derive a multi-domai clock skew schedule that attempts to miimize the peak curret. We use the procedure ZONE_PARTITION_SCHEDULING to re-schedule all the registers i the circuit graph G. Whe a zoe is re-scheduled, our objective is to miimize the peak curret produced by the registers that have bee re-scheduled. I the pseudo code of Fig. 6, we use the otatio RP to deote the set of all the registers that have bee re-scheduled. (2) The secod phase attempts to further reduce the peak curret. A clockig domai is called the hottest clockig domai, if ad oly if the total curret derivative at this clockig domai is exactly the same as the peak curret. The peak curret caot be further reduced, uless some registers scheduled i hottest clockig domais ca be rescheduled ito other clockig domais. Thus, we iteratively apply the procedure ZONE_PARTITION_SCHEDULING to re-schedule the registers scheduled i hottest clockig domais. The iteratio process repeats util the peak curret caot be further reduced. Note that, i the secod phase, we let the set RP be all the registers i the circuit graph G. Procedure ZONE_PARTITION_SCHEDULING(phase,RS,G,P) partitio all the registers i the set RS ito zoes (uder the costrait o the maximum umber of biary variables); if (phase == ) the RP = else RP = all the registers i the circuit graph G; for each zoe do (i the sequece of their priorities) if (phase == ) the add all the registers i this zoe ito RP; re-schedule this zoe uder all the clockig costraits to reduce the peak curret produced by the registers i the set RP; ed Fig. 6: Procedure ZONE_PARTITION_SCHEDULING. Let s use Fig. as a example. First, we derive both the ASAP schedule ad ALAP schedule as show i Table I. Also, we derive a feasible multi-domai clock skew schedule i which T C = d 2, T C2 = d 2, T C3 = d 2, T C4 = d 2, T C5 = d 2 ad T C6 = d 2 to work with clock period 6 tu as the iitial solutio. Therefore, iitially, the peak curret is 6*c. Suppose that the maximum umber of biary variables ivolved i a zoe is oly 4. The process of zoe-based schedulig is as below. First, we eter the first phase of zoe-based schedulig. The first phase re-schedules all the registers i the circuit graph. From both the ASAP schedule ad the ALAP schedule, we kow that R, R 2, R 3, R 4, R 5 ad R 6 are associated with 2, 0, 2, 2, 0 ad 2 biary variables. Thus, all the registers i the circuit graph are partitioed ito two zoes: zoe Z = {R, R 2, R 3, R 5 } ad zoe Z 2 = {R 4, R 6 }, ad zoe Z has a higher priority to be re-scheduled. I the followig, we reduce the peak curret i the sequece of zoe Z ad zoe Z 2. We reduce the peak curret by re-schedulig zoe Z uder T C4 = d 2 ad T C6 = d 2. The 0- ILP formulatios are as below: miimize peak_curret_z

5 S, + S,2 = ; S 3, + S 3,2 = ; S, *I +S 3, *I 3 peak_curret_z ; S,2 *I +*I 2 +S 3,2 *I 3 +*I 5 peak_curret_z ; We have the results that peak_curret_z = 2*c, S, =, S,2 = 0, S 3, = ad S 3,2 = 0. As a result, we have T C = d, T C2 = d 2, T C3 = d, T C4 = d 2, T C5 = d 2, T C6 = d 2 ad the peak curret is 4*c. Thus, the peak curret is reduced from 6*c to 4*c. We further reduce the peak curret by re-schedulig zoe Z 2 uder T C = d, T C2 = d 2, T C3 = d ad T C5 = d 2. The 0- ILP formulatios are as below: miimize peak_curret_z _Z 2 S 4,2 + S 4,3 = ; S 6,2 + S 6,3 = ; *I +*I 3 peak_curret_z _Z 2 ; *I 2 +S 4,2 *I 4 +*I 5 +S 6,2 *I 6 peak_curret _Z _Z 2 ; S 4,3 *I 4 +S 6,3 *I 6 peak_curret_z _Z 2 ; We have the results that peak_curret_z _Z 2 = 2*c, S 4,2 = 0, S 4,3 =, S 6,2 = 0 ad S 6,3 =. Thus, the peak curret is reduced from 4*c to 2*c. Next, we eter the secod phase of zoe-based schedulig. The peak curret is 2*c. Sice the total curret derivative at clockig domais d, d 2 ad d 3 are 2*c, 2*c, 2*c, respectively, they are hottest clockig domais. We fid that R ad R 3 are scheduled to d, R 2 ad R 5 are scheduled to d 2, ad R 4 ad R 6 are scheduled to d 3. Thus, we partitio these six registers ito two zoes: zoe Z 3 = {R, R 2, R 3, R 5 } ad zoe Z 4 = {R 4, R 6 }, ad zoe Z 3 has a higher priority to be re-scheduled. We re-schedule zoe Z 3 uder T C4 = d 3 ad T C6 = d 3. The 0- ILP formulatios are as below: miimize peak_curret S, + S,2 = ; S 3, + S 3,2 = ; S, *I +S 3, *I 3 peak_curret; S,2 *I +*I 2 +S 3,2 *I 3 +*I 5 peak_curret; *I 4 +*I 6 peak_curret; We have the results that peak_curret = 2*c, S, =, S,2 = 0, S 3, = ad S 3,2 = 0. The peak curret is still 2*c. We re-schedule zoe Z 4 uder T C = d, T C2 = d 2, T C3 = d ad T C5 = d 2. The 0- ILP formulatios are as below: miimize peak_curret S 4,2 + S 4,3 = ; S 6,2 + S 6,3 = ; *I +*I 3 peak_curret; *I 2 +S 4,2 *I 4 +*I 5 +S 6,2 *I 6 peak_curret; S 4,3 *I 4 +S 6,3 *I 6 peak_curret; The secod phase of zoe-based schedulig is fiished with the results that peak_curret = 2*c, S 4,2 = 0, S 4,3 =, S 6,2 = 0 ad S 6,3 =. After the zoe-based schedulig is completed, the peak curret is 2*c uder the multi-domai clock skew schedule i which T C = d, T C2 = d 2, T C3 = d, T C4 = d 3, T C5 = d 2 ad T C6 = d 3. IV. Experimetal Results Our approach has bee implemeted i a C++ program ruig o a persoal computer with AMD K8-3GHz CPU ad G Bytes RAM. We use Exteded LINGO Release 8.0 as the 0- ILP solver. The circuits from ISCAS 89 bechmark suites are targeted to a 0.35µm cell library for the experimets. Without loss of geerality, i each bechmark circuit, we assume that: () the clock period P is the logest path delay; P (2) we are give 2 + clockig domais, where 0.3 s 0.3 deotes the clock skew betwee two cosecutive clockig domais; (3) each clockig domai d k = P P 0.3 (k ) s, where k =,, ; (4) the 0.3 maximum possible curret of each register is c (at the clock arrival time); ad (5) if the circuit is fully sychroous, the peak curret occurs whe all the registers are switchig simultaeously. Table II gives the characteristics of bechmark circuits. The colum zero skew deotes the peak curret of fully sychroous implemetatio, while the colum [6] deotes the peak curret solved by the 0- ILP formulatios as described i [6]. We use the otatio -- to deote that the problem complexity caot be solved withi 2 hours. Table II. Characteristics of bechmark circuits. circuit registers gates data clock peak currret paths period zero [6] skew S *c 2*c S *c 6*c S *c 4*c S *c 6*c S *c 4*c S *c -- S *c *c S *c -- S *c -- S *c -- S *c -- S *c 288*c S *c -- Table III demostrates the advatage of exploitig both the ASAP schedule ad the ALAP schedule to prue the

6 redudacies. Note that, for each bechmark circuit, both the ASAP schedule ad the ALAP scheduled ca be derived withi secod. The colum [6] describes the origial 0- ILP formulatios. The colum Reduced formulatios describes the reduced 0- ILP formulatios, i which all the redudacies are prued. The colum #vars deotes the umber of biary variables, the colum #cos deotes the umber of costraits, ad the colum CPU time gives the CPU time i secods. Table III. The advatage of pruig redudacies. Circuit [6] Reduced Formulatios #vars #cos CPU time (s) #vars #cos CPU time (s) S S S S S S S S S S S S S Table IV demostrates the results of zoe-based schedulig. The bechmark circuits that have more tha 2000 irredudat biary variables are used to test the effectiveess of zoebased schedulig. Without loss of geerality, here we use the fully sychroous solutio as the iitial solutio. The colum tackled zoes deotes the umber of times to use the 0- ILP solver to re-schedule a zoe. The CPU time icludes the time spet i both our C++ program ad the 0- ILP solver. For the coveiece of comparisos, we also report the results obtaied by whole-circuit schedulig, which solves the whole circuit as a sigle zoe. We fid that the whole-circuit schedulig caot solve bechmark circuits S5850 ad S38584 withi 2 hours. However, o the other had, the zoe-based schedulig ca solve each bechmark circuit withi 72 secods o matter the costrait o the maximum umber of biary variables ivolved i a zoe is 500, 000 or V. Coclusios This paper ivestigates a fast multi-domai clock skew schedulig for peak curret reductio. The mai cotributio of our work is that it overcomes the high computatioal expese of previous work. Bechmark data cosistetly show that our approach achieves very good results withi a acceptable ru time. Ackowledgemets This work was supported i part by the Natioal Sciece Coucil of R.O.C. uder grat umber of NSC E Refereces [] J.P. Fishbur, Clock Skew Optimizatio, IEEE Tras. o Computers, Vol. 39, No. 7, pp , 990. [2] L. Beii, P. Vuillod, A. Bogliolo, ad G. De Micheli, Clock Skew Optimizatio for Peak Curret Reductio, Joural of VLSI Sigal Processig, vol. 6, pp. 7 30, 997. [3] A. Vittal ad M. Marek-Sadowska, Power-Optimal Buffered Clock Tree Desig, i the Proc. of IEEE/ACM Desig Automatio Coferece, pp , 995. [4] J.P. Fishbur, Solvig a System of Differece Costraits with Variables Restricted to a Fiite Set, Iformatio Processig Letters, vol. 82, o. 3, pp , [5] K. Ravidra, A, Keuhlma, ad E. Setovich, Multi- Domai Clock Skew Schedulig, i the Proc. of IEEE/ACM Iteratioal Coferece o Computer Aided Desig, pp , [6] A. Vittal, H. Ha, F. Brewer, ad M. Marek-Sadowska, Clock Skew Optimizatio for Groud Bouce Cotrol, i the Proc. of IEEE/ACM Iteratioal Coferece o Computer Aided Desig, pp , 996. Table IV. The results of zoe-based schedulig. circuit 500 variables i a zoe 000 variables i a zoe 2000 variables i a zoe whole-circuit peak tackled CPU peak tackled CPU peak tackled CPU peak CPU curret zoes time (s) curret zoes Time (s) curret zoes time (s) curret time (s) S327 4*c 8 0 4*c 6 4 4*c *c 88 S3384 5*c 0 5 5*c 6 8 5*c 4 4 5*c 24 S5378 *c 7 7 *c 5 28 *c 2 54 *c 59 S6669 *c 0 *c 6 20 *c 5 26 *c 22 S9234 7*c *c *c *c 232 S3207 6*c *c *c 285 6*c 362 S5850 5*c *c *c S *c *c *c *c 27 S *c *c *c