Schedulability Analysis of Non-preemptive Real-time Scheduling for Multicore Processors with Shared Caches

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1 Schedulability Analysis of Non-preeptive Real-tie Scheduling for Multicore Processors with Shared Caches Jun Xiao, Sebastian Alteyer and Andy Pientel Inforatics Institute, University of Asterda, Asterda, Netherlands Eail: Abstract Shared caches in ulticore processors introduce serious difficulties in providing guarantees on the real-tie properties of ebedded software due to the interaction and the resulting contention in the shared caches. To address this proble, we develop a new schedulability analysis for realtie ulticore systes with shared caches. To the best of our nowledge, this is the first wor that addresses the schedulability proble with inter-core cache interference. We construct an integer prograing forulation, which can be transfored to an integer linear prograing forulation, to calculate an upper bound on cache interference exhibited by a tas within a given execution window. Using the integer prograing forulation, an iterative algorith is presented to obtain the upper bound on cache interference a tas ay exhibit during one ob execution. The upper bound on cache interference is subsequently integrated into the schedulability analysis to derive a new schedulability condition. A range of experients is perfored to investigate how the schedulability is degraded by shared cache interference. I. INTRODUCTION Multicore architectures are increasingly used in both the destop and the ebedded arets. Modern ulticore processors incorporate shared resources between cores to iprove perforance and efficiency. Shared caches are aong the ost critical shared resources on ulticore systes as they can efficiently bridge the perforance gap between eory and processor speeds by bacing up sall private caches. However, this brings aor difficulties in providing guarantees on realtie properties of ebedded software due to the interaction and the resulting contention in a shared cache. In a ulticore processor with shared caches, a real-tie tas ay suffer fro two different inds of cache interferences [13], which severely degrade the tiing predictability of ulticore systes. The first is called intra-core cache interference, which occurs within a core, when a tas is preepted and its data is evicted fro the cache by other real-tie tass. The second is inter-core cache interference, which happens when tass executing on different cores access the shared cache siultaneously. Inter-core cache interference ay cause several types of cache isses including capacity isses, conflict isses and so on [4]. It is challenging to design real-tie applications executing on ulticore platfors with shared caches, which cannot afford to iss deadlines and hence deand tiing predictability. Any schedulability analysis requires nowledge about the Worst- Case Execution Tie (WCET) of real-tie tass. With a ulticore syste, the WCETs are strongly dependent on the aount of inter-core interference on shared hardware resources such as ain eory, shared caches and interconnects. In this paper, we shall only focus on the shared cache interferences and study the schedulability analysis proble for hard real-tie tass that exhibit shared cache interferences. A aor obstacle is to predict the cache behavior to accurately obtain the WCET of a real-tie tas considering inter-core cache interference since different cache behaviors (cache hit or iss) will result in different execution ties of each instruction. In [19], it was even pointed out that it will be extreely difficult, if not ipossible, to develop analysis ethods that can accurately capture the contention aong ultiple cores in a shared cache. In this paper, tas s WCET does not account for shared cache interference. [12] presents such an approach to derive a tas s WCET without considering shared cache interference. We propose a novel schedulability analysis of non-preeptive real-tie scheduling for ulticore systes with shared caches. Intra-core cache interference is avoided since no preeption is possible during tas execution. We therefore focus on inter-core cache interference and specially conflict isses that caused by liited cache associativity. The ain contributions of this wor are: An integer prograing forulation is constructed to calculate the upper bound on the cache interference exhibited by a tas within a given execution window; An iterative algorith is presented to obtain the upper bound on inter-core cache interference a tas ay exhibit during its ob executions; A new schedulability condition is derived by integrating the upper bound on inter-core cache interference into the schedulability analysis; A set of experients are perfored using the proposed schedulability analysis to investigate the effects of intercore cache interference for a range of different tassets. The rest of the paper is organized as follows. Section II gives an overview of the related wor. The syste odel is described in Section III. Section IV describes the proposed schedulability analysis, where we also detail the coputation of processor-

2 contention and inter-core cache interferences applied in the analysis. Section V presents an iterative coputation to obtain the upper bound of inter-core cache interferences. Section VI presents the experiental results, after which Section VII concludes the paper. II. RELATED WORK For hard real-tie systes, it is essential to obtain each real-tie tas s WCET, which provides the basis for the schedulability analysis. WCET analysis has been actively investigated in the last two decades, of which an excellent overview can be found in [21]. There are well-developed techniques to estiate real-tie tass WCET for single processor systes. Unfortunately, the existing techniques for single processor platfors are not applicable to ulticores with shared caches. Only a few ethods have been developed to estiate tas WCETs for ulticore systes with shared caches [23], [11], [15]. In alost all those wors, due to the assuption that cache interferences can occur at any progra point, WCET analysis will be extreely pessiistic, especially when the syste contains any cores and tass. An overestiated WCET is not useful as it degrades syste schedulability. Since shared caches introduce the difficulty into accurately estiating the WCET, any researchers in the real-tie systes counity have recognized and studied the proble of cache interference in order to use shared caches in a predictable anner. Cache partitioning, which isolates application worloads that interfere with each other by assigning separate shared cache partitions to individual tass, is a successful and widely-used approach to address contention for shared caches in (real-tie) ulticore applications. There are two cache partitioning ethods: software-based and hardwarebased techniques [8]. The ost coon software-based cache partitioning technique is page coloring [16], [20]. By exploiting the virtual to physical page address translations present in virtual eory systes at OS-level, page addresses are apped to pre-defined cache regions to avoid the overlap of cache spaces. Hardware-based cache partitioning is achieved using a cache locing echanis [6], [19], [17], which prevents cache lines fro being evicted during progra execution. The ain drawbac of cache locing is that it requires specific hardware support that is not available in any coercial processors. With shared cache partitioning techniques, one can apply existing analyses to derive the upper bounds of a tas s WCET assuing that no cache interference can occur between tass siultaneously running on different cores. In that case, it is safe to use the derived WCETs in the schedulability analysis. Although the schedulability analysis of global ultiprocessor scheduling has been intensively studied [14], [5], [3], few wors addressing schedulability analysis for ulticores with shared caches are [9], [22], where cache space isolation is deployed. In addition to regular teporal constraints, cache constraints due to cache space isolation are added in the schedulability analysis. They propose a linear prograing forulation to perfor the schedulability test and an over approxiation of this forulation to iprove the scalability of the test. However, this solution is not applicable to our proble since our syste architecture does not deploy any cache isolation techniques. Our wor also differs fro other approaches to the tiing verification of ulticore systes [1] in that all other sources of interferences are assued to be included within the WCET. We analyze the effect of shared cache interference on the schedulability. To the best of our nowledge, this is the first wor that integrates inter-core cache interferences into schedulability analysis. A. Tas Model III. SYSTEM MODEL We consider a set τ of n periodic or sporadic real-tie tass τ 1, τ 2,... τ n to be scheduled on a ulticore processor. Each tas τ = (C, D, T ) τ is characterized by a worst-case coputation tie C, a period or iniu inter-arrival tie T, and a relative deadline D. All tass are considered to be deadline constrained, i.e. the tas relative deadline is less or equal to tas period: D T. We further assue that all those tass are independent, i.e. they have no shared variables, no precedence constraints, and so on. Moreover, obs of any tas cannot be executed at the sae tie on ore than one core. A tas τ is a sequence of obs J, where is the ob index. We denote the arrival tie, starting tie, finishing tie and absolute deadline of a ob as r, s, f and d, respectively. Note that the goal of a real-tie scheduling algorith is to guarantee that each ob will coplete before its absolute deadline: f d = r +D. As explained, it is difficult to accurately estiate C considering cache interference of other tass executing concurrently. It should be pointed out that C in this paper refers to the WCET of tas, assuing tas is the only tas executing on the ulticore processor platfor, i.e. any cache interference delays are not included in C. Since tie easureent cannot be ore precise than one tic of the syste cloc, all tiing paraeters and variables in this paper are assued to be non-negative integer values. B. Architecture Model Our syste architecture consists of a ulticore processor with identical cores onto which the individual tass are scheduled. Most ulticore processors have different independent caches, including instruction and data caches. Caches are organized as a hierarchy of ultiple cache levels to address the tradeoff between cache latency and hit rate. The low level caches (L1) in our considered ulticore processor are assued to be private, while the last level caches (LLC, for exaple L2) are shared between all cores. Furtherore, we assue that the LLC cache is noninclusive with respect to the private caches (L1), and that LLC caches are direct-apped caches. We believe this wor can be extended to set-associative LRU caches, and we plan to do so as future wor.

3 In this wor, we only consider instruction caches since we adopt the approach in [12], which only accounts for instruction cache, to derive WCET. C. NP-FP Scheduler In this paper, we focus on non-preeptive global scheduling, thus we do not have to consider intra-core cache interference. If not explicitly stated, cache interference will therefore refer to inter-core cache interference in the following discussion. For siplicity reasons, we will tae the Non-Preeptive Fixed Priority (NP-FP) global scheduling as the exaple in this paper. We will extend our wor to other non-preeptive schedulers such as a global Non-Preeptive Earliest Deadline First (NP- EDF) scheduler. To use NP-FP scheduling, a priority P is assigned to each tas τ ( = 1, 2,...n). As each tas has a unique priority, we use hp() to denote the set of tass with higher priorities than τ, and hep() = hp() {τ } the set of tass whose priorities are not lower than τ. Siilarly, lp() is the set of tass with lower priorities than τ and lep() = lp() {τ } the set of tass whose priorities are not higher than τ. The NP-FP scheduling algorith is wor-conserving, according to the following definition. Definition 1. A scheduling algorith is wor-conserving if there are no idle cores when a ready tas is waiting for execution. IV. SCHEDULABILITY ANALYSIS In this section, we give an overview of the new schedulability analysis that accounts for cache interference. We also present the approaches to derive the upper bound on the paraeters used in the schedulability condition. A. Overview We first analyze the execution of one ob J of a tas τ. The tie interval [r, d ] is called a proble window [3]. Figure 1: Overview of the new schedulability analysis that accounts for cache interference. As shown in Figure 1, a tas τ exhibits two inds of interferences during the execution of a ob. The first interference is I pre (r, d ), denoting the cuulative length of all intervals over the proble window in which τ is ready to execute but cannot proceed due to unavailability of cores as they are executing other obs. We define the interference I pre i, (r, d ) of a tas τ i on a tas τ over the interval [r, d ) as the cuulative length of all intervals in which τ is ready to execute, and τ i is executing while τ is not. The second type of interference is the cuulative length of all extra execution delays caused by shared cache interference due to conflict accesses fro all other tass running concurrently on other cores, denoted as I sc(r, d ). We also define the interference Isc i, (r, d ) as the cuulative length of all extra execution delays of τ over the proble window caused by conflict shared cache accesses between tas τ i and tas τ. It is clear that for a ob to eet its deadline, the su of the two interferences a tas exhibits in the proble window plus the tas s WCET C ust be less than the length of the proble window, which is D. For a tas to be schedulable, this condition ust hold for all its obs. We define the worst-case interference for tas τ as: Ī = ax (r, d ) + Isc (r, d )) = I pre (r p, dp ) + Isc (r p, dp ) (I pre where p is the ob instance in which the su of the two interferences is axial. By construction, we have the first schedulability test for τ. Theore 1. A tas set τ is schedulable with a NP-FP scheduling policy on a ulticore processor coposed of identical cores with shared caches if and only if for each tas τ τ Ī + C < D The necessary and sufficient schedulability condition expressed by Theore 1 cannot be used to chec if a tas set is schedulable without nowing how to copute the interference ters Ī. Unfortunately, we are not aware of any ethod to copute Ī starting fro the given tas paraeters. To sidestep this proble, we will use an upper bound on each of the interferences. We define the worst-case processor-contention interference Īpre (r, d ) and worst-case shared cache interference Ī sc(r, d ) for tas τ as: = ax (I pre (r, d )) = Ipre (r q, dq ) where q is the ob instance in which the processor-contention interference is axial and Ī sc = ax(i sc (r, d )) = Isc (r s, d s ) where s is the ob instance in which the cache interference is axial, respectively. Theore 2. A tas set τ is schedulable with a NP-FP scheduling policy on a ulticore processor coposed of identical cores with shared caches if for each tas τ τ + C + Īsc < D

4 Proof. Ī = ax ax = Īpre (I pre (I pre + Īsc (r, d ) + Isc (r, d )) (r, d )) + ax(i sc (r, d )) if Īpre + C + Īsc < D, then Ī + C < D. The Theore follows fro Theore 1. B. Coputing an upper bound of Īpre The worload W i (D ) of a tas τ i in the proble window [r, d ) of length D is the tie tas τ i executes during interval [r, d ), according to a given scheduling policy. Lea 1. The processor-contention interference that a tas τ i causes on a tas τ in the proble window of τ is never greater than the worload of τ i in the proble window. i,, I pre i, (r, d ) W i(d ) Lea 1 is obvious, since W i (D ) is an upper bound on the execution of τ i in the proble window. Since it is difficult to copute the exact value of Īpre, we will copute the upper bound of the worst-case worload by each tas in the proble window, and use the su of each tas s worload to derive an upper bound on Īpre. As shown in Figure 2, the upper bound of the worst-case worload can be calculated by categorizing each ob of τ i in the proble window into one of the three types [2]: carry-in ob: a ob with its release tie earlier than r, but with its deadline in the proble window; body ob: a ob with both its release tie and its deadline in the proble window; carry-out ob: a ob with its release tie in the proble window, but with its deadline later than d. τ i : (a) τ i : (b) D i T i carry-in ob body ob carry-out ob ob. Following the approach in [10], we copute Wi nc (D ) and Wi ci(d ) as follows: Coputing Wi nc (D ) For τ i hp(), the worst-case worload of tas τ i occurs when a ob of τ i arrives at exactly the start of the proble window, as shown in case (b) in Figure 2. The next obs of τ i are then released periodically every T i tie units. Therefore the nuber of body obs of τ i that contribute with C i to the worload in the proble window is at ost D T i. The contribution of the carry-out ob can then be bounded by in(d od T i, C i ). τ i s worload in the proble window is 0 for τ i lep(). We can copute Wi nc (D ) by: { D Wi nc T (D ) = i C i + ω nc τ i hp() (2.1) 0 τ i lep() where ω nc = in(d od T i, C i ) Coputing Wi ci(d ) If τ i hp(), the worst-case worload of τ i is generated when r coincides with the starting tie of the carry-in ob of τ i : oving the proble window bacwards, the contribution of carry-in cannot increase and the carry-out can only decrease; while advancing the proble window, the carry-in will decrease and the carry-out can increase by at ost the sae aount. Such a situation is depicted as case (a) in Figure 2. The contribution of the carry-in ob is bounded by C i. Note that the first body ob of τ i after the carry-in obs, is released at tie r + C i + T i D i. The nuber of body obs that contribute to τ i s worload is N i (D ) = ax(0,d C i T i+d i) T i. The contribution of the carry-out ob can then be bounded by in(c i, ax (0, D C i T i + D i ) od T i ). For τ i lep(), only the carry in ob of τ i starting execution before r can contribute to the worload in the proble window. Thus, we copute Wi ci W ci i (D ) = where (D ) by: { (1 + N i (D ))C i + ω ci τ i hp() in(d, C i ) τ i lep() (2.2) τ D ω ci = in(c i, ax (0, D C i T i + D i ) od T i ). r Figure 2: Three types of contribution obs and proble window. Case (a) and (b) shows the densest possible pacing of obs of τ i if τ i has a carry-in ob and has no carry-in obs, respectively. The worst-case worload of τ i occurs when a carry-in ob (if τ i has a carry-in ob) finishes execution as late as possible and a carry-out ob starts its execution as early as possible. We use (D ) to denote an upper bound of τ i s worload in the proble window if τ i has no carry-in ob, and use Wi ci(d ) to denote an upper bound of τ i s worload if τ i has a carry-in W nc i d Lea 2. If tass are scheduled with a NP-FP scheduling policy on a ulticore processor coposed of identical cores, at ost tass have carry-in obs. Proof. See Lea 5.2. in [10]. The tas set τ can be partitioned into two subsets τ nc and τ ci that include tass with carry-in obs and tass without carry-in obs in the proble window, respectively. According to Lea 2, τ ci has at ost tass. Now we define Ω as the axial value of the su of all tass worloads (other

5 than τ worload) in the proble window of τ aong all possible cases: Ω = ax i W i (D ) = ax ( W (τ nc,τ ci i nc (D ) + Wi ci (D )) (2.3) ) τ τ i τ nc τ i τ ci where τ nc and τ ci satisfy τ nc τ ci = τ\{τ }, τ nc τ ci = and τ ci. By taing the axiu over the tas set, Ω describes an upper bound on the total worst-case worload (other than τ worload) in the proble window of τ. The coplexity to copute Ω is O(n), as explained in [3]. Replacing C i. The coputation of Wi nc (D ), Wi ci(d ), Ω depends on C i. We denote the value Ω as Ω (C) when C i is used in Equation (2.1) and (2.2). Fixing paraeters other than C i in Equation (2.1) and (2.2), Wi nc (D ), Wi ci(d ) and the resulting Ω are non-decreasing with respect to C i. In the following discussion, we will show that the actual execution tie of τ i including cache interference could be larger than C i. Since cache interference could also contribute to the tas worload, we will use Ci which is the su of C i and the upper bound on cache interference exhibited by τ i to replace C i in Equation (2.1) and (2.2) in order to get the correct upper bound on the worst-case worload. We denote Ω (C ) as resulting value if Ci is used in the coputation. We are now ready to copute an upper bound of Īpre. Lea 3. If tass are scheduled with a NP-FP scheduling policy on a ulticore processor coposed of identical cores with shared cache, Ω (C ) Proof. Since the scheduling algorith NP-FP is worconserving, in the tie instants in which a ob of τ is ready but not executing, each core ust be occupied by a ob of another tas. As I pre ) = 0, we can exclude the contribution, (rq, dq of τ to the interference. So i Ipre i, (rq, dq ) By Lea 1, the interference that a tas τ i causes on a tas τ in the proble window is bounded its worload, So, we have I pre i, (rq, dq ) W i(d ). i Ipre i, (rq, dq ) ax i W i(d ) = Ω (C ) C. Coputing an upper bound of Īsc We first identify the axiu cache interference between two tass and then we construct an integer prograing forulation to calculate the upper bound on the shared cache interference exhibited by a tas within an execution window.. 1) Cache interference between two tass: We first analyze the cache interference during one ob execution between τ and τ i. Let τ be the interfered and τ i be the interfering tas. Following the approach in [12], we can obtain the WCET of a tas by perforing a Cache Access Classification (CAC) and Cache Hit/Miss Classification (CHMC) analysis for each instruction eory access at the private caches and the shared LLC cache separately. The CAC deterines the possibility that an instruction being fetched fro eory will access a certain cache level, and the access to a certain cache level can be Always (A), Uncertain (U) or Never (N). CHMC assigns a cache looup result to each eory reference according to the cache states. As a result, a reference to a eory bloc of instructions can be classified as Always Hit (AH), Always Miss (AM) or Uncertain (U). Since we consider noninclusive caches, accesses to the private caches cannot be affected by tass executing on other cores. Accesses classified as AM or U at the shared LLC cache will also not be affected by shared cache interferences, since they are already counted as isses in the WCET analysis. We start the cache interference analysis by defining two concepts for cache blocs. Definition 2. A Hit Bloc (HB) is a eory bloc whose access is classified as AH at the shared LLC cache. Definition 3. A Conflicting Bloc (CB) is a eory bloc whose access is classified as A or U at the shared LLC cache. HB and CB can be identified by the approach proposed in [12]. We use HB = {,1,,2,...,,p } to represent the set of HB for tas τ and use n,x (x = 1, 2,..., p) to denote the nuber of,x s accesses that are classified as a AH at the LLC cache. Siilarly, we define CB i = { i,1, i,2,..., i,q } as the set of CB for tas τ i and denote n i,x as the nuber of i,x s accesses that are classified as a A or U at the LLC cache. Note that HB and CB i includes the eory blocs that eet the requireent in every progra path that ay be taen by the tas. In our syste architecture, cache interference occurs only at the shared LLC cache when a cache line used by τ is evicted by τ i and consequently causing reload overhead for τ. A cache line that ay cause cache interference for τ needs to satisfy at least two conditions: (i) access to that cache line will result in a cache hit at the LLC cache in WCET analysis of τ, (ii) the cache line ay be used by τ i. Fro the above two conditions, we can analyze eory bloc accessing that ay cause interference. The first condition iplies that only accessing to HB ay cause cache interference for τ, while the second condition indicates that accessing to CB i by τ i ay interfere with τ. Furtherore, cache interference occurs only if τ accesses eory blocs in HB and τ i accesses eory blocs in CB i concurrently, and those eory blocs have the sae cache index.

6 We use Ii, sc to represent the upper bound on the shared cache interference iposed on τ by only one ob execution of τ i. Suppose the indices of the LLC cache range fro 0 to N 1, we can derive N subsets of HB according to the apping function idx that aps a eory address to the cache line index at the LLC cache as follows, ˆ,u = {,x HB idx(,x ) = u}, (0 u < N, u N). We define the characteristic function of a set A which indicates ebership of an eleent x in A as: { 1 x A χ A (x) = 0 otherwise. Let N,u represent the nuber of hit accesses to the u-th cache line by τ without cache interference. N,u equals to the total nuber of access to the HBs apping to the -th cache line, p N,u = n,x χ ˆ,u (,x ). x=1 Siilarly, we divide CB i into N subsets by ê i,u = { i,x CB i idx( i,x ) = u}, (0 u < N, u N). The nuber of accesses to the -th cache line by τ i is bounded by q N i,u = n i,x χêi,u ( i,x ), x=1 Cache interference can only happen aong eory blocs that are in the sae subset that aps to the sae cache line. For the u-th cache line, τ can be interfered at ost N,u ties and τ i can interfere at ost N i,u ties. The following forula gives an upper bound on the nuber of cache iss by accessing the HBs for tas τ. S(τ i, τ ) = N 1 u=0 in(n i,u, N,u ) Suppose the penalty for an LLC cache iss is a constant, C iss, then I sc i, satisties: I sc i, = S(τ i, τ )C iss. The coputation only taes the eory accesses of τ and τ i as input, so Ii, sc only depends on eory accesses of τ and τ i. Lea 4. I sc i, = S(τ i, τ )C iss. Proof. The lea holds as discussed above. Given a tasset, Ii, sc can be coputed, as shown in the proof of Lea 4. In the following discussion, we assue Ii, sc is nown. Lea 4 gives an upper bound on cache interference for τ iposed by only one ob of τ i. It is possible that ore than one obs of τ i interfere with τ. We denote the nuber of obs of τ i that interfere with τ as N i,. Lea 5. The total cache interference τ exhibited fro N i, obs of τ i is bounded by N i, I sc i,. Proof. For N i, obs of τ i, the total nuber of accesses to each eory bloc i,x is bounded by N i, n i,x. Thus, the execution of N i, obs of τ i accesses the -th cache line also at ost N i, N i,u ties. Fro the proof of Lea 4, the upper bound of the total cache interference exhibited by τ fro N i, obs of τ i is N 1 u=0 in(n i,n i,u, N,u )C iss. N 1 N i, Ii, sc = N i, in(n i,u, N,u )C iss = N 1 u=0 N 1 u=0 in(n i, N i,u, N i, N,u )C iss in(n i, N i,u, N,u )C iss u=0 2) IP forulation: We can copute an upper bound of the axiu cache interference a tas ay exhibit during an execution window by introducing an Integer Prograing (IP ) forulation, which can be transfored to an integer linear prograing forulation. It is necessary to chec the schedulability of the tas-set without considering cache interference. If the tas-set does not pass the initial schedulabity test, there is no need to calculate the cache interference. Only if all tass (including τ i ) pass the schedulability test (without considering cache interference), the IP is solved to copute the upper bound on cache interference. Therefore, the IP forulation is based on the assuption that τ i is schedulable without cache interference. If N i, obs of τ i executing concurrently with τ, the cache interference that τ i causes on τ is bounded by N i, Ii, sc according to Lea 5. As a tas ay exhibit cache interference fro ore than one tas during a ob execution, the total cache interference for one ob execution of τ is bounded by the su of the contributions of all other tass τ i (i ) in the tas set τ. Thus, the obective function of the IP forulation is: ax i N i, I sc i,. (2.4) The IP forulation will have an unbounded solution without further constraints to the variable N i,. To get a bounded solution, we analyze the constraints on N i,. First, we define the concept of the execution window of a ob. Definition 4. The Execution Window (EW ) of the -th ob of τ (J ) is tie interval [s, f ] fro the staring tie to the finishing tie of J. Note that the length of an execution window ay be larger than C, since the EW includes the cache interference. We use C as the length of the EW because of the iterative coputation which will be described later on.

7 N i, reaches its inial value when a ob of τ i starts to execute as soon as it is released and the execution finishes ust before the start of the EW, as shown the case (a) in Figure 3. Denoting Ci in as the sallest execution tie of τ i, often called Best-Case Execution Tie (BCET), we have the following constraint: ax(0, C i, T i + Ci in ) + ξ i N i, (2.5) T i { 1 ((C where ξ i = + Cin i ) od T i ) D i + Ci in > 0. 0 otherwise The ter ξ i indicates whether the last ob of τ i released within the EW that interferes with τ since the last released ob should start its execution Ci in before its relative deadline if the tas is schedulable. τ i : (a) τ i : (b) τ C in i s Execution window: C Figure 3: Situations where τ i interferes τ with the ost and least nuber of obs. The axiu value of N i, is taen when the first interfering ob of τ i finishes ust after the start of the EW and the last interfering ob of τ i starts to execute at the tie when it is released. Such a situation is depicted as case (b) in Figure 3. Thus, we have the second constraint on N i, : ax(0, C i, N i, 1 + T i + D i ) (2.6) If N i, > 2, the first and last interfering obs of τ i ay occupy alost 0 coputation capacity in the EW. Let J i be such a ob aong the reaining N i, 2 interfering obs of τ i between the first and the last ones. Both release tie r i and deadline d i of J i are within the EW of τ. Lea 6. If τ i is schedulable without considering cache interference, C i coputation capacity of the processing core is reserved for the execution of J i during [r i, d i ]. If J i executes for Ci act < C i, the processing core will be accuulatively idle (executing nothing, siply wasting the processing capacity for τ i ) for at least C i Ci act during [r i, d i ]. Proof. If τ i satisfies the schedulability condition without considering cache interference (shown in Pseudocode 1): Ω i(c) + C i < D i, the core on which J i is executed spends at ost D i C i in total for the execution of other interfering tass during [r i, d i ]. J i is guaranteed to have C i coputation capacity during [r i, d i ]. T i f The reaining coputation capacity of a ulticore processor with cores is ( 1)C since one core is dedicated to the execution of τ. Due to the liited coputation capacity of the processor, the total execution of the tass that ay interfere with τ within the EW can not exceed ( 1)C. Hence, we have the third constraint: ax(0, N i, 2)C i ( 1) C. (2.7) i The obective function (2.4) together with three constraints on N i, i.e. inequalities (2.5), (2.6) and (2.7) for our IP proble. Since Ci in is a relatively sall nuber, we tae the extree case: Ci in = 0. As tas paraeters such as C i, D i, T i is nown, the optial solution of the IP only depends on the length of EW. Thus, we use I sc (C ) to denote the optial value of the IP proble if C is used as the length of the EW in the IP. Note that Inequalities (2.5) and (2.7) are based on the assuption that τ i is schedulable. Thus, before solving the IP, we have to chec the schedulability of the tasset assuing no cache interference between tass, i.e. Īsc i = 0. Coputation coplexity of the IP. The original IP can be easily transfored to an Integer Linear Prograing (ILP ) proble by introducing a new integer variable y i, for each N i, with two additional constraints: y i, 0 and y i, N i, 2. Inequality (2.7) can be replaced by i y i,c i ( 1) C. In the transfored ILP proble, we have totally 2(n 1) variables and 4(n 1) + 1 constraints. The coplexity of the IP is the sae as the coplexity of solving the transfored ILP proble, which is O(4n64 n ln 4n) [7]. V. ITERATIVE COMPUTATION Due to the presence of cache interference, a ob ay execute longer than C on a ulticore platfor with shared caches. However, a larger execution tie ay introduce ore cache interference, as illustrated in Figure 4. In Figure 4 (a), if the ob of τ executes for C, only one ob of τ i interferes with τ. In Figure 4(b), if the ob of τ executes for a larger execution tie, say C +Isc (C ), two obs of τ i could possibly interfere with τ, which potentially ay increase the cache interference exhibited by τ. This exaple suggests an iterative ethod to find an upper bound on the cache interference. Figure 4: More cache interference if τ executes for a longer tie.

8 Lea 7. I sc (C ) is non-decreasing with respect to C Lea 7 is explained by the above exaple. We give a sufficient condition for a certain value that can be used as an upper bound on cache interference. Lea 8. if C C such that C = C + I sc (C ), then I sc (C ) is the upper bound on cache interference exhibited by τ. Proof. If C = C + I sc (C ), then Isc (C ) = Isc (C + I sc (C )). According to Lea 7, given an execution window of τ that is no ore than C +I sc (C ), the cache interference exhibited by τ is not larger than I sc (C ). Therefore, Isc (C ) is the upper bound on cache interference for τ. We now derive the iterative algorith, called CacheInterf erence(τ) which taes tasset τ as input, to copute an upper bound on cache interference for each tas τ τ: Since the constraints of IP assue the tasset is schedulable, we first chec the schedulability of the tasset assuing no cache interference between each tas. Only if all tass pass schedulability test, the following steps will be taen. C is initialized with C and an upper bound value on the cache interference I sc (C ) is created which is initially set to zero By solving the IP, we copute a new upper bound of the cache interference I sc (C ). If the new upper bound of cache interference is the sae as the old upper bound, the I sc (C ) is the final upper bound of τ. Otherwise, another round of coputing the upper bound on cache interference is perfored using the upper bound derived at the previous iteration. The iteration for τ stops either if no update on I sc (C ) is possible anyore or if the coputed I sc (C ) is large enough to ae τ unschedulable. The previous steps are repeated for every tas in τ. A ore foral version of the CacheInterf erence(τ, ) algorith is given by Pseudocode 1. The algorith returns I which includes the upper bounds on cache interference I sc (C ) for each tas τ and C which includes the upper bounds on the execution length C for each τ. If I and C are epty, the tasset is not schedulable. Since the solution of the IP is non-decreasing with respect to C according to Lea 7 and one terination condition is C D, the terination of the algorith is guaranteed. We propose the following Theore to chec the schedulability of the tas set. Theore 3. A tas set τ is schedulable with the NP-FP scheduling policy on a ulticore platfor coposed of identical cores with shared caches if for each tas τ τ (1) C C such that C = C + I sc (C ), (2) Ω (C ) + C < D. Pseudocode 1: CacheInterference(τ, ) 1: Input: Tas paraeters, nuber of cores: 2: I epty list, used to store I sc (C ) for each tas 3: C epty list, used to store C for each tas 4: pass true 5: for all τ τ do 6: Ω (C) calculation of Equation (2.3) using C 7: if Ω (C) + C D then 8: pass false 9: brea 10: end if 11: end for 12: if pass then 13: for all τ τ do 14: update true, I old 0, I new 0 15: C C 16: while update do 17: I old I new 18: I new Solution of IP with C as the EW 19: C = C + I new 20: if I new == I old or C D 21: update false then 22: end if 23: end while 24: Add I new to I 25: Add C 26: end for 27: end if 28: return I, C to C Proof. Fro (1), I sc (C ) is the upper bound on cache interference exhibited by τ according to Lea 8. So, I sc (C ) Īsc. Fro Lea 3, Ω (C ) If Ω (C ) + C = Ω (C ) +C +Īsc Īpre. + C + I sc (C ) < D then < D. Theore 3 follows fro Theore 2. Finally, we give the procedure ChecSchedulability(τ, ) to perfor the schedulability test, as illustrated by Pseudocode 2. Pseudocode 2: ChecSchedulability(τ, ) 1: Input: Tas paraeters, nuber of cores: 2: I, C CacheInterference(τ, ) 3: if I == null then 4: return Unschedulable 5: else 6: for all τ τ do 7: Ω (C ) calculation of Equation (2.3) using C 8: if Ω (C ) + C D then 9: return Unschedulable 10: end if 11: end for 12: end if 13: return Schedulable

9 Coputational coplexity: Let n represent the nuber of tass in the tas-set. For τ, let I in be the sallest difference between cache interference caused by one ob of τ i and τ, i.e. I in = in i, (Isc i, Isc, ), the while loop in CacheInterf erence(τ, ) taes at ost γ = (D ax C ) ties since C I in either stays the sae or increases at least with I in in each iteration. Thus, the coplexity of CacheInterference(τ) is O(γ4n 2 64 n ln4n). The coputational coplexity of Ω (C ) is O(n). Therefore, the coplexity of ChecSchedulability(τ, ) is O(γ4n 4 64 n ln4n). VI. EXPERIMENTS In this section, we evaluate the perforance of the proposed schedulability test in ters of acceptance ratio. More specifically, we will quantify the effects of cache interference on the schedulablity of the generated tassets. The experients have been perfored varying i) the nuber of cores ( = 2, 4 or 8), ii) the nuber of tass n (n = 10, 20, or 30) in the tasset, iii) total tas utilization U tot (U tot fro 0 to with steps of 0.2), iv) the cache interference factor IF (IF = 0, 0.3, 0.6 or 0.9), and v) the probability of two tass having cache interference on each other: P (P = 0.1, 0.2, 0.3 or 0.4). Given those five paraeters, we have generated tassets in each experient. As the tas generation policies ay significantly affect experiental results, we give the policies used in the experients as follows. Tas utilization generation policy. We use Randfixedsu [18] to generate vectors that consist of N eleents and whose coponents su to the U tot. Each eleent in the vector is assigned an individual tas utilization U in the tasset. Tas period and WCET generation policy. For each tas τ, T is uniforly distributed over the interval [100000, ]. The WCET of τ is derived by C = T U. We consider an iplicit deadline tas syste, which iplies that D i = T i. Cache interference generation policy. The probability of two tas having cache interference is P. If two tass τ and τ i interfere with each other, Ii, sc is generated as Isc i, = IF in(0.5c i, 0.5C ). In each experient, we easure the nuber of schedulable tassets that pass the proposed schedulability test. The acceptance ratio is the nuber of schedulable tassets devided by the total nuber of tassets (200000). Figure 5 shows the acceptance ratio for the case IF = 0, 0.3, 0.6, 0.9, when fixing = 8, n = 10, P = 0.1. The red line with IF = 0 represents the acceptance ratio when tass have no cache interference. Evidently, the acceptance ratios with a lower IF are better than those with a larger IF. As we increase IF with the sae aount, the average acceptance ratio decreases in a slower fashion. However, it does not indicate that a lower bound on the average acceptance ratio is possible since the cache interference gets larger as IF increases, eventually aing the interfered tass unschedulable. Figure 6 copares the acceptance ratio with different P, fixing = 8, n = 10, IF = 0.3. With the sae U tot, the acceptance ratio decreases as P increases because a larger P indicates ore tass in the tasset could interference with each other, which ay potentially increase the upper bound on cache interference for each tas. Figure 5: Acceptance ratio with different IF when = 8, n = 10, P = 0.1. Figure 6: Acceptance ratio with different P when = 8, n = 10, IF = 0.3. Figure 7 illustrates the acceptance ratio with respect to the nuber of cores. The acceptance ratio for tas having no cache interference is also plotted in Figure 7. Instead of using U tot as horizontal axis, we scale the horizontal axis with Utot 8 for = 2, 4. It is worth noting that an execution platfor with fewer cores is ore efficient in ters of acceptance ratio than those with ore cores. However, for processors with different cores, the difference in the acceptance ratio between the baseline (tass having no cache interference, IF = 0) and tass having cache interference is alost siilar. A set of experients are perfored to investigate the ipact of the nuber of tass in the tasset on the acceptance ratio. Figure 8 shows the acceptance ratio for different n in the tasset. It is interesting to note that when U tot is less than 2, the acceptance ratio of tassets with less tass is slightly worse than those with ore tass. When U tot is very sall, U and C in a tasset with ore tass are on average saller than those with ore tass, thus Ii, sc is also saller. While as U tot increases, the acceptance ratio for tassets with fewer tass becoes better than those with ore tass. This ay be due to the fact that ore tass in the tasset results in ore tass having cache interference as P is fixed. In order to copute the average running tie of the proposed

10 Figure 7: Acceptance ratio with different when IF = 0 or 0.3, P = 0.1, n = 10. Figure 8: Acceptance ratio with different n when IF = 0.3, P = 0.1, = 8. schedulability test with different tas-set scales, we easured the execution tie of the schedulability test for the tas-sets used in the previous experient. The executions are conducted on a server with an 48-core AMD processor (2.1GHz). On average, it taes seconds to chec the schedulability of the tas-set consisting of 10 tass, seconds for tas-set with 20 tass, while seconds for tas-set with 30 tass. VII. CONCLUSIONS In this paper, we developed a new schedulability analysis of non-preeptive real-tie scheduling for ulticore processors with shared caches. We constructed an integer prograing forulation that can be transfored to an integer linear prograing forulation to calculate the upper bound on cache interference exhibited by a tas during a given execution window. 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