An Efficient Approach for Power Delivery Network Design with Closed-Form Expressions for Parasitic Interconnect Inductances

Transcription

1 An Efficient Approach for Poer Deivery Netork Design ith Cosed-Form Expressions for Parasitic Interconnect Inductances Chen Wang, Jingkun Mao, Giuseppe Sei, Shaofeng Luan, Lin Zhang, Jun Fan, David J. Pommerenke, Richard E. DuBroff and James L. Dreniak ABSTRACT Investigation of a DC poer deivery netork, consisting of a mutiayer PCB using area fis for poer and return, invoves the distributed behavior of the poer/ground panes and the parasitics associated ith the umped components mounted on it. Fu-ave methods are often empoyed to study the poer integrity probem. Whie fu-ave methods can be accurate, they are time and memory consuming. The cavity mode of a rectanguar structure has previousy been empoyed to efficienty anayze the simutaneous sitching noise (SSN) in the poer distribution netork. Hoever, a arge number of modes in the cavity mode are needed to accuratey simuate the impedance associated ith the vias, eading to computationa inefficiency. A fast approach is detaied herein to acceerate cacuation of the summation associated ith the higherorder modes. Cosed-form expressions for the parasitics associated ith the interconnects of the decouping capacitors are aso introduced. Combining the fast cacuation of the cavity modes of reguary shaped panar circuits, a segmentation method, and cosedform expressions for the parasitics, an efficient approach is proposed herein to anayze an arbitrary shaped poer distribution netork. Whie it may take many hours for a fuave method to do a singe simuation, the proposed method can generay perform the simuation ith good accuracy in severa minutes. Another advantage of the proposed 1

2 method is that a SPICE equivaent circuit of the poer distribution netork can be derived. This aos both frequency and transient responses to be done ith SPICE simuation. I. INTRODUCTION Mutiayer printed circuit boards (PCBs) empoying entire ayers or arge area fis for poer and ground panes are commony used for DC poer distribution for integrated circuits (IC) operating at a high-speed. The poer and ground panes essentiay form a parae pate ave-guide. The parae pate ave-guide provides a good noise couping path, hich can ead to signa integrity (SI) probems, such as fauty sitching of circuits or faiure of systems. Noise couped into the poer-distribution structure can aso radiate through the fringing fieds at the edges or can coupe to nearby structures, resuting in EMI (eectromagnetic interference) probems. Therefore, a good design of the poer distribution netork is essentia to ensure signa integrity and to reduce the risk of EMI probems. Fu-ave numerica methods, such as the finite-difference time-domain (FDTD) method [1,, 3], and the partia-eement equivaent circuit technique (PEEC) [4, 5], are often empoyed to investigate the poer integrity probem. Whie fu-ave methods are accurate, they are in genera time and memory consuming. Methods to improve the efficiency of fu-ave simuators, i.e. a parae-distributed method [6], have been proposed in the iterature. A poer/ground structure ith thickness much ess than the smaest aveength of interest can be considered as a to-dimensiona microave panar circuit ith n observabe ports [7], and the associated Z-parameter matrix can be

3 derived anayticay using the cavity mode for simpe shapes. The cavity mode of a rectanguar poer-bus structure deveoped for microstrip patch antennas [8], has been previousy appied for poer distribution netorks in digita design as e [9, 10, 11]. For irreguar shapes, a segmentation method can be empoyed [1, 13]. Therefore, the distributed behavior of an arbitrary shaped poer distribution netork can be characterized ith the cavity mode, and the segmentation method. Hoever, an infinite summation of modes appears in the Z-matrix of the cavity mode. The infinite summation has to be truncated in a practica cacuation. It is demonstrated in Section II that a arge number of modes has to be incuded to mode the impedance of vias ith good accuracy. The cacuation of a arge number of modes eads to computationa inefficiency, and it aso increases the number of eements in the SPICE equivaent circuit. A Tchebyshev expansion as appied to the high-order modes to acceerate the computation in microstrip antenna appications [14]. This agorithm is empoyed herein, and further approximations are made to speed up the cacuation. Comparing the speed of the reguar cavity mode and that of the fast agorithm, a speed-up factor of seventy has been achieved for the case demonstrated in Section II. The fast agorithm aso significanty reduces the number of circuit eements for the SPICE simuation. In the case demonstrated in Section II, hie 50,000 circuit eements ere required for the reguar cavity mode to achieve good accuracy, ony 180 eements ere needed for the fast agorithm. Considering ony the distributed nature of the poer distribution netork, hoever, is not sufficient. Parasitics associated ith the umped component interconnects aso pay an important roe in the response of the poer distribution netork. Whie there 3

4 are many cosed-form expressions of parasitic inductances [15, 16, 17], their appicabiity for cacuating interconnect parasitics on PCBs is unknon. Fu-ave methods are empoyed herein to verify cosed-form expressions. This ork proposes an approach, hich systematicay combines the existing methods, namey the cavity mode ith the fast agorithm, the segmentation method, and cosed-form expressions for parasitic interconnect inductance, to effectivey mode a poer distribution netork. Whie it may take hours to do a singe simuation ith a fu-ave approach, it ony takes a fe minutes for the proposed method. Moreover, ith the equivaent circuit of the poer distribution netork, the appropriate port connections, and the interconnect parasitic inductances, a comprehensive circuit mode can be derived for poer integrity design of an irreguary shaped muti-ayer PCB, and it can be simuated ith SPICE both in the time and frequency domains. The modeing of the distributed nature of the poer deivery netork is presented in Section II. After a brief revie of the cavity mode, the effect of the high-order modes on the accuracy of the modeing is examined. Simuated resuts indicate that a arge number of modes are needed to achieve good accuracy. A fast agorithm is then presented, and a factor of more than seventy in speed improvement is achieved for the fast agorithm as compared to the reguar cavity mode. The segmentation method is aso summarized in Section II for competeness. The agreement beteen the measurements and the segmentation method in conjunction ith the fast cavity mode, iustrate the appicabiity of the proposed method for the investigation of irreguary shaped poer distribution netorks. Cosed-form expressions for the interconnect parasitics are given in Section III. The cosed-form expressions ere examined ith a fu-ave method for 4

5 typica ayout geometries of decouping capacitors, and the errors reative to the fuave method are expained based on the reevant physics. In Section IV, to exampes are presented, one is a 3-ayer PCB ith seven decouping capacitors, and the other is a structure ith three panes. Good agreement for both cases has been obtained. Concusions are given in Section V. II. FAST CALCULATION OF THE IMPEDANCE MATRIX OF A POWER AREA AND A SPICE EQUIVALENT CIRCUIT A poer deivery netork having a thickness much ess than the smaest aveength of interest can be characterized by a to-dimensiona Hemhotz equation in terms of the E-fied norma to the panes, aong ith the open boundary conditions (perfect magnetic a) around the periphery of the panes [7, 8]. Then, the poer deivery netork can be considered as a to-dimensiona microave panar circuit ith n externa observation ports. For poer and ground panes ith simpe shapes, such as a rectange and an equiatera triange, the impedance matrix can be obtained anayticay [7, 9, 10, 11], as summarized in Tabe 1. The SPICE equivaent circuits for the rectanguar and the equiatera trianguar poer distribution netorks can be derived from (3) and (4) in Tabe 1, respectivey, as shon in Fig. 1. The effect of the interpane capacitance as e as each mode is represented in the equivaent circuit. Parameters C 0, L mn, and G mn can be cacuated from the board dimensions and the dieectric properties, as given in Tabe 1. The turns ratios of idea transformers, N mni (i = 1 n), contain information regarding the ocation and dimension associated ith port i. 5

6 Tabe 1. Impedance matrices and netork parameters for a rectanguar and an equiatera trianguar poer area fis. Geometry b y Port i (x i, y i) Rectange top vie Port j (x j, y j ) W yi W xj W yj y Port j (x j, y j ) W xj Equiatera triange a W yj Impedance matrix d z W xi side vie ε, tanδ jωµ dn mni mnj Zij ( ω ) = (1) m= 0 n= 0 ab( kmn k ) m and n: the mode indices mπ nπ k mn = k = ω a b tanδ εµ 1 j N r d a r = ωµσ mπxi nπyi N mni = cmcn cos( )cos( ) a b mπw nπw xi yi sin c( )sin c( ) a b 1 m, n = 0 cm, cm =, m, n 0 x x (0,0) Port i (x i, y i ) W xi W yi board thickness: d ( ) N1 mnin1mnj NmniNmnj 4 jωµ d () Zij = 3a kmn k m, n and : m n = 0, the mode indices 16π k mn = ( m mn n ), 9a tan δ r d k = ω εµ 1 j, N = P1( x, y,, m, n) N 1mni mni i P1( x, y, m, n, ) P1( x, y, n,, m) i = P( x, y,, m, n) i i i P( x, y, m, n, ) P( x, y, n,, m) i i i ( 1) πxi πwxi P1( xi, yi,, m, n, ) = cos( ) sin c( ) 3, 3a 3a π ( m n) y π ( m n) W i yi cos( ) sin c( ) 3a 3a ( 1) πxi πwxi P( xi, yi,, m, n, ) = cos( ) sin c( ) 3 3a 3a π ( m n) y π ( m n) W i yi sin( ) sin c( ) 3a 3a i i i i x Equivaent circuit representation Z ( ω) = ω ij = mn k mn 1 N mni N mnj m= 0 n= 0 jωc0 jωlmn 1, C εµ Gmn = C0ω mn (tan δ 0 abε, = L d r ) d mn (3) Gmn 1 =, C ω 0 mn Z ( ω) = ij N N 1 1mni 1mnj N mni m= n= jωc0 jωlmn 0ωmn N G mnj 1, 3a ε ωmn = k mn C0 =, εµ 4d 1, r Lmn = Gmn = C0ω mn (tan δ ) C d mn (4) 6

7 A. A Fast Agorithm for the Cavity Mode and the Corresponding Equivaent Circuit The doube infinite summations in (1) and () (see Tabe I) must be truncated in practice. An equiatera trianguar poer distribution netork as constructed ith a doube-sided FR4 board to investigate the effect of the number of cacuated modes on the response of the netork. The thickness of the board as 1.7 mm (50 mis) and the edge ength a as 0 cm, as shon in Tabe 1. An SMA connector as sodered at (4.5 cm,.6 cm) as the feeding port, and S 11 as measured ith an HP8753D netork anayzer. Port extensions ere performed to extend the measurement reference pane to the ground pane of the board. So, ony the center conductor of the SMA connector inside the board needs to be considered in the modeing. The measured S 11 vaues ere converted to the input impedance Z in, as shon in Fig.. The input impedance Z in as aso cacuated using () ith a reative dieectric constant of ε = 4. 3, and a oss tangent of tan δ = The inductive behavior of the SMA center conductor inside the pane pair is incuded in the cavity mode, as expained in Section III. Whie the discrepancy beteen the measurement and the cavity resut truncated at n m = 0 0 modes is arge, the agreement beteen the measurement and the cavity resut truncated at modes is good, indicating that the high-order modes affect the accuracy of the cavity mode, especiay for the nus here the impedance is o. Hoever, it is not computationay efficient to cacuate the cavity mode ith a arge number of modes, especiay for the case of a arge number of ports, hich is common in a practica design, since each IC pin of interest and each decouping capacitor introduce a port. An efficient agorithm for cacuating the high order modes is presented beo. r 7

8 1 The term k k mn in (1) and () in Tabe I can be expanded in Tchebyshev poynomias for k mn k as [18] k 1 k mn 1 k = [ k k mn mn e( k k mn k )], e ( ) < (5) k mn The approximation in (5) can be appied to both the rectanguar and the equiatera trianguar geometries. The rectanguar geometry is used beo to demonstrate the fast cacuation agorithm. If k 0 corresponds to the highest frequency of interest, (1) can be approximated by Z ij jωµ d ( ab k mn < k 0 N k mni mn N mnj k X 0 X 1 k ), (6) here = N mni N mnj N mni N mnj X , and m= 0 n= 0,( m, n) (0,0) kmn kmn < k0,( m, n) (0,0) kmn = N mnin mnj N mnin mnj X Since the terms X and m= 0 n= 0,( m, n) (0,0) kmn kmn < k0,( m, n) (0,0) kmn X 1 are independent of frequency, they need to be cacuated ony once for the entire frequency range of interest. Therefore, (6) represents a considerabe improvement in the speed of the overa cacuation time. Since the second term in (5) varies as k k mn, it can be negected in comparison to the first term hen k mn is arge compared to k. The maximum error in negecting the second term in (5) is ess than 10% for further approximated by, k mn > k. Consequenty, the cavity mode can be 8

9 Z ij jωµ d ab k mn < k 0 N k mni mn N mnj k X 0. (7) Empoying a Fourier series summation formua m= Cm cosmx π cos( x π ) α = [19], the m α α sinπα 0 doube summation m= 0 n= 0,( m, n) (0,0) N mni k N mn mnj in X 0 can be reduced to a singe summation eading to [0] jωµ d ab nπw sinc( b m= 0 n= 0,( m, n) (0,0) ' yi mni mn nπw )sinc( b ' yi mnj ωµ da nπy nπy i j Cn cos( )cos( ) n 0 jb b b N k N [cos( α x ) cos( α x )] n n ) α sinα n n, (8) here nπ mπw mπw xi xj α n = ja, x± = 1 xi ± x j / a. The approximation sinc sinc 1 b a a as made to obtain (8). This approximation modes the rectanguar port i as an equivaent fat strip of idth ' W yi. The equivaent strip idth can be found as [1] W = exp(3/ ), (9) ' r yi i here r i is the radius of a circuar port ith the same cross-sectiona area of the rectanguar port. Since α n is imaginary, the series in (8) converges rapidy. Therefore, a fast singe summation cacuation for the impedance matrix can be achieved. The fast singe summation is particuary usefu hen the number of ports is arge. jωµd The reactance term X 0 ab in (7) represents the contributions of the high-order modes. Since it is ineary dependent on the frequency, the reactance term can be represented by an inductance as 9

10 µd L ij = X 0. (10) ab An equivaent circuit representation for the fast cacuation is then shon in Fig. 3. The ii L represents a sef inductance associated ith port i, and L ij represents a mutua inductance beteen ports i and j. A test board as buit to verify the fast agorithm. The test board as a 15.-cm by 9-cm doube sided board ith a feeding port at (1. cm, 6 cm) and a shorting pin at (3 cm, 3 cm), as shon in Fig. 4. The dieectric ayer beteen the to soid panes as 50 mis thick ith a reative permitivity ε r = 4.3 and a oss tangent tanδ = 0.0. An SMA connector as mounted as the feeding port, and the idth of the center conductor of the SMA connector as 1.7 mm (50 mis). The diameter of the shorting pin as aso 1.7 mm (50 mis). The input impedance as measured from 100 MHz to 3 GHz using an HP8753C netork anayzer. The input impedance as aso simuated using the cavity mode ith the votage at the shorting port set to zero. The resuts are shon in Fig. 4, and good agreement beteen the measurements and the cavity modeing resuts as obtained. A summation over modes as required to achieve the accuracy shon. The CPU time for the reguar cavity mode as in (1), the fast doube summation approach as in (7), and the fast singe summation approach as in (8) are isted in Tabe. An AMD 1.4-GHz computer as used to perform a the cacuations. The truncated mode number for a the approaches as set to m = n = 100. Whie it took 61 seconds for the reguar cavity mode to cacuate modes, it ony took 4.8 seconds for the fast doube summation agorithm, and the CPU time as further reduced to 3.5 seconds hen the fast singe summation as empoyed. From Fig. 4, it is seen that the resuts of 10

11 measurements, the reguar cavity mode, the fast doube summation and the singe summation match cosey over the entire frequency range, indicating the accuracy of the fast agorithm. Accuracy of the proposed equivaent SPICE mode in the time domain is demonstrated in []. Tabe. The cacuation time using different cacuation approaches for the -ayer board ith a shorting pin. Approach Reguar cavity mode Fast doube summation Fast singe summation CPU time (s) B. The Segmentation Method For a poer-bus ith an irreguar shape, a segmentation method can be used for anaysis [1, 13], if the pattern can be divided into segments having reguar shapes. Consider the panar circuit shon in Fig. 5. The continuous interconnection beteen the α- and β-segments is repaced by a discrete number of interconnected ports, denoted c- ports on the α-segments and d-ports on the β-segments. Ports p and q are the externa (unconnected) ports of the α- and β-segments, respectivey. The Z-matrices for α-, β-, and γ-segments, namey ~ ~ ~ Z α, Z β, and Z γ, respectivey, can be partitioned into submatrices corresponding to the externa (unconnected) and connected ports as ~ ~ ~ Z ppα Z pc Z = α (11) ~ ~ Z cp Z cc ~ ~ Z dd Z β = ~ Z qd ~ Z dq ~ Z qqβ (1) 11

12 ~ ~ Z ppγ Z γ = ~ Z qp ~ Z pq. (13) ~ Z qqγ Enforcing the continuity of votage and current on ports c and d, ~ Z γ can be cacuated as [13] here ~ ' Z dp ~ Z cc ~ ~ ~ ~ ~ ~ ' ' Z ppα Z pc Z dp Z pc Z dq Z = γ, (14) ~ ~ ~ ~ ~ ' ' Z qd Z dp Z qqβ Z qd Z dq ~ Z dd ~ 1 Z cp ~ ' ~ ~ 1 = [ ] and Z dq = [ Z cc Z dd ] Z dq. It is straightforard to ~ appy the segmentation method to the equivaent circuit by simpy connecting the c-ports of the α-circuit to the d-ports of the β-circuit. Fig. 6 shos a test board ith FR4 as the dieectric materia. The board thickness as 1.0 mm (40 mi). To SMA connectors ere sodered on the board to measure the Z-parameters. In the cavity mode, the pattern as divided into three smaer rectanges ith each piece modeed using (1). In the cacuations, four discrete interconnected ports ere used to represent the continuous interconnection beteen to adjoining rectanges. Then the impedance for the entire board as cacuated using the segmentation method. The reative dieectric constant as ε = 4. 3, and the oss tangent as tan δ = 0. 0 in the r mode. The modeed resuts agree e ith the measured resuts for both Z 11 and Z 1, as shon in Fig. 7. III. CALCULATION OF PARASITIC INDUCTANCES Decouping capacitors are idey used in poer deivery netorks to mitigate sitching noise from ICs. Decouping capacitors can provide a o-impedance path to 1

13 shunt transient energy to ground at the IC source in reativey o-frequency ranges Hoever, a rea capacitor incudes both parasitic inductance and parasitic resistance associated ith the interconnects and the package of the capacitors. The goba decouping capacitors are generay not effective in the high-frequency range hen it acts as a high-impedance eement due to the series parasitic inductance [3, 4]. Whie oca decouping capacitors can be effective up to the gigahertz range due to the mutua couping beteen the to vias associated ith the capacitors and its adjacent IC device, its benefit cannot be effectivey achieved hen the ratio of L / L 1, as shon in Fig. 8, is approximatey greater than one [5]. Therefore, cosed-form expressions of the parasitic inductances are desired for quantifying the ayout of the decouping capacitors on a poer deivery netork for both goba and oca decouping. The parasitic inductance cacuated ith cosed-form expressions can aso be incorporated in the equivaent circuit of the poer deivery netork for SPICE simuations. The current path of the decouping capacitor can be decomposed into to oops, as shon in Fig. 8. One is the oop formed by the current foing through the capacitor and the current foing on the upper surface of the return pane, denoted by Loop 3 in Fig. 8. Another portion of the interconnect inductance resuts from the current foing aong the via connected to the oer pane denoted by L 1. The couping beteen these to oops can be negected if the pane structure is sufficienty arge, and the fux penetrating through the via antipad is negigibe. The parasitic inductance associated ith Loop 3 can be approximated by a summation of L and L 3. The inductance L corresponds to the current oop Loop hen the capacitor is shorted by a trace that is directy on top of the PCB, as indicated by the dashed arro and the current path on the 13

14 return pane. The inductance L 3 is defined as the difference beteen the inductance associated ith Loop 3 and the inductance associated ith Loop, and it is caused by the current path deviation in the capacitor. The inductance L 3 denotes the increament in inductance beteen an idea current path and the rea current path through the capacitor. Whie L 3 is dependent on the capacitor mounting structure, i.e., it is dependent on the distance beteen the capacitor and the return pane, it is reasonabe to use an approximated vaue for engineering estimations. The approximated vaue can be obtained by e designed methods [5], and the method using an impedance anayzer ith open and short compensation is empoyed herein. The focus of this paper is on the cacuations of L 1 and L. The inductance L 1 is associated ith the current foing through the via. Since the input impedance of the cavity mode as derived from the Green s function for a spatia deta current density injected perpendicuary into the panes [7], L 1 is incuded in the cavity mode in the infinite summation expressions (1) and (). It shoud be noted that since the boundary condition at the feed port is repaced ith an impressed source, that hie the feed port inductance is incuded for L 1 in the cavity mode, the mutua inductance associated ith a changing current distribution on the to vias hie bringing -ports in proximity [3], is not. It as demonstrated that L 1 as associated ith the high-order modes in the cavity mode, and as dependent on the position of the via [6]. A cosed-form expression of L 1 as given in [7]. For muti-ayer appications, the parasitic inductance associated ith the interconnect segment inside the panes can aso be taken into account by connecting ports of mutipe cavity modes, as iustrated in 14

15 15 Section IV B. This section focuses on the cosed-form expression of the oop inductance above the panes, L. The fux rapping Loop in Fig. 8 can be decomposed approximatey into to orthogona contributions: the fux due to the vertica geometry defined by the vias, as shon in Fig. 9 (b), and the fux due to the horizonta geometry encompassed by the trace and the upper pane, as shon in Fig. 9 (c) [16]. For 5 >. d, the current distribution can be assumed uniform both aong the periphery of the via, and aong the ength of the via [16]. Then, the inductance associated ith the first contribution, i.e., from the vias, can be cacuated as [16] = n s s s s s ps h h h h h M π µ (15a) = n s s s s s ps h r h r r h r h h L π µ (15b) ( ) ps ps via M L L =. (15c) here r is the radius of the via, r = d/. Definitions of other parameters in these equations are shon in Fig. 9. The inductance associated ith the contribution from the microstrip can be cacuated using image theory to remove the pane. The resuting cosed-form expression has been derived in [17]. The mutua inductance beteen the microstrip and its image M t and the sef-inductance of the microstrip L t are

16 16 ( ) ( ) ( ) ( ) = 3 4 n 3 tan 4 n 3 n p p p p p p p p p p p p p p p p p p M t (16a) ( ) = n 3 n L t (16b) here p=h s. Then the tota inductance associated ith the horizonta geometry, L trace, is t t trace M L L =. (16c) The derivation in [17] assumed a uniform current distribution aong the ength and idth of the trace. The tota inductance L associated ith Loop in Fig. 8 is then L via L trace L =. (17) The inductance L is meaningfu ony at o frequencies hen the input impedance associated ith Loop can be vieed as ineary dependent on the frequency. Hoever at high frequencies, Loop behaves ike a transmission ine. Assuming the transmission ine is ossess, the input impedance can be ritten as = λ π jz Z in tan 0, here is the ength of the transmission ine and λ is the aveength. If is much ess than λ, Z in can be approximated as λ π jz Z in 0, exhibiting inductive behavior. The error of this approximation is ithin 10% for 08 < 0. λ, and ithin 0% for 11 < 0. λ.

17 A fu-ave method, CEMPIE, as empoyed to evauate (17) and the underying approximation, for cacuating the parasitic interconnect inductance associated ith SMT capacitors. CEMPIE is a circuit extraction approach based on a mixed potentia integra equation formuation [8], and is a type of partia eement equivaent circuit (PEEC) formuation [9, 30, 31]. It empoys an integra equation formuation ith a quasi-static ayered media dyadic Green s function, and enforces the boundary condition on meta surfaces. If a perfect eectric conductor (PEC) boundary condition is used for the meta surfaces, the eectrica fied integra equation can be ritten as A r r r ' r ' ' r nˆ [ jω G (, ) J ( ) ds φ( )] = 0, r S1 S, (18) S1 S here S1 represents the horizonta meta surfaces, corresponding to PCB panes and traces; S represents the vertica meta surfaces, corresponding to the vias; J v, G A, and φ are the current density, the quasi-static dyadic Green s function, and the scaar eectric potentia, respectivey. Appying the Method of Moments to (18), ith RWG basis functions for the panar surfaces [3], and roof-top basis functions for the vertica (via) surfaces, and assuming φ is constant ithin a ce, the edge current i can be reated to φ as j ω[ L][ i] [ Λ][ φ] = 0, (19) here [L] is the branch-ise inductance due to its coefficient jω, and [Λ] is the connectivity matrix that reates ce quantities to edge quantities. Defining a noda current I as the tota current foing out of a mesh ce, and appying the continuity of current, the surface charge Q on each ce can be reated to I as e j ω [ Q] = [ I ] [ I ], (0) 17

18 here I e is the externa impressed current on the ces. The noda current I can be reated T to the edge current i ith the connectivity matrix as [ I ] = [ Λ ][ i]. The surface charge Q can be reated to φ by the scaar eectric potentia Green s functions as [ φ ] = [ K][ Q] mixed-potentia integra equation can then be derived as. A jωc Λ T Λ φ I = jωl i 0 e, here [ ] [ ] 1 C = K. (1) A reationship beteen the node potentia φ and the impressed current I e can be ritten as e [ Y ][ φ ] = [ I ], () jω T 1 here [Y] is the noda admittance matrix, and [ ] [ ] ( ) ω[ ] Y = Λ L Λ j C. Then the netork parameters can be extracted from the Y-matrix for ports of interest. In the CEMPIE simuations beo, an externa port, Port 1, is defined beteen the antipad on the return pane and the via, as shon in Fig. 9 (a). The round via as discretized into 0 edges ith each edge as a current branch. The current branches ere connected to a pseudo-node and an externa impressed current as injected into the node. The injected current spreads on the vertica surfaces of the via here a interactions are incuded, therefore, the impedance can be correcty modeed by the CEMPIE method. The impedance associated ith Port 1 is extracted from the Y-matrix. The impedance varies ineary ith frequency at o frequencies, exhibiting an inductive behavior. The sope of the impedance magnitude is cacuated as the parasitic interconnect inductance L. The meta panes in CEMPIE, incuding the trace and the return pane are meshed ith trianguar ces, and the via a is meshed into rectanguar ces. Typica meshes for the trace and the return pane are shon in Fig. 10. A parametric study as considered 18

19 based on the trace ength, trace idth, height h s, and via diameter d, as shon in Fig. 9. Fig. 11 shos the parasitic inductance varying ith the trace ength and idth, hie the height, h s, is 0.10 mm (4 mis) and the via diameter remains at 0.33 mm (13 mis). These parameters ere chosen according to dimensions that are commony used in current engineering design. In the CEMPIE simuations, the antipad has a diameter of 0.89 mm (35 mis). The reative error of (17) is in genera ithin 10% for engths onger than.54 mm (100 mis). When the ength is short and the idth is narro, the assumption of a uniform current distribution on the via a fais. More current concentrates on the via a hich is the inner side of Loop, as shon in Fig. 1 (a). Consequenty, the current path is shorter than the ength from via center to center, hich is used in (16). As a resut, expression (17) overestimates the parasitic inductance. When the idth of the trace increases, the current spreads itsef aong the idth of the trace, as shon in Fig. 1 (b). Whie it may be sufficient to assume that the current is uniformy distributed in Region, as shon in Fig. 1, the assumption is not vaid in Region 1 and Region 3. In Region 1 and Region 3, the current concentrates at the vias, hose diameter is much smaer than the idth of the trace, eading to arger parasitic inductance. Therefore, expression (17) underestimates the parasitic inductance, since it assumes a uniform current distribution aong the entire ength (via center to center). As the ength of the trace increases, the contribution of the inductive current transition from the via to the trace is smaer, and the parasitic inductance is better predicted ith (17). Simuations sho the current distributions of the to cases shon in Fig

20 Next, the via diameter and height ere varied to evauate the accuracy of (17) for different package sizes of decouping capacitors. The ength and idth associated ith different dimensions ere chosen as shon in Tabe 3. The via diameter varies from 0.33 mm (13 mis) to 1.0 mm (40 mis), and the height h s changes from 0.10 mm (4 mis) to.9 mm (90 mis). The resuts from expression (17) compared to that from the CEMPIE simuations are shon in Tabe 4. The current distribution on the trace is shon in Fig. 1 (b) hen the ratio of the via diameter to the trace idth is sma. With an increase in the ratio of the via diameter to the traces idth, the current distribution changes, as shon in Fig. 1 (a). Consequenty, the error of Expression (17) increases in the overestimation direction for each capacitor size, as the via diameter varies from 13 mis to 40 mis, as shon in Tabe 4. Expression (17) overestimates the parasitic inductance for h s 0.5 mm, and the maximum discrepancy occurs hen the h s is in the range from 0.5 mm to 0.5 mm. The reason is currenty unknon. The maximum error of (17) in Tabe 4 is 18%, hich may sti be acceptabe for engineering purposes. IV. CORRELATION WITH THE MEASUREMENTS Measurements and fu-ave modeing have been empoyed to verify the resuts from the approach proposed herein. The first test case incudes a singe pair of poer and ground panes. The second test case considers a poer pane ith to ground panes. A. A Poer Bus ith Goba Decouping Capacitors An FR4 three-ayer rectanguar poer deivery netork ith seven decouping capacitors as buit to verify the proposed compete approach for poer integrity design. 0

21 The dimensions of the test board ere 3.0 cm in idth and 1.4 cm in ength. The spacing beteen the top ayer to the ground pane as cm (1 mis), and the Tabe 3. Trace ength and idth associated ith different capacitor sizes. Capacitor size Length from via center to via center (mm) Width (mm)

22 Tabe 4. Parasitic inductance vs. via diameter d, height h s and capacitor size. Parasitic inductance CEM- (17) Err* CEM- (17) Err CEM- (17) Err CEM- (17) Err (nh) PIE (%) PIE (%) PIE (%) PIE (%) d=0.33mm d=0.51mm d=0.76mm hs = 0.1 mm hs= 0.5 mm hs= 0.51 mm d=1.0mm d=0.33mm d=0.51mm d=0.76mm d=1.0mm d=0.33mm d=0.51mm d=0.76mm d=1.0mm hs= 0.76 mm hs=1.5 mm hs=.9 mm d=0.33mm d=0.51mm d=0.76mm d=1.0mm d=0.33mm d=0.51mm d=0.76mm d=1.0mm d=0.33mm d=0.51mm d=0.76mm d=1.0mm * Error is cacuated as (L (17) - L CEMPIE ) / L CEMPIE. dieectric thickness beteen the ground and poer ayers as cm (33 mis), as shon in Fig. 13. The idths of the PCB traces associated ith the decouping capacitors ere a 0.1 cm (40 mis), and the engths ere varied from 0.6 cm (36 mis) to 0.5 cm (98 mis). The capacitors mounted on the board had the same nomina capacitance of

23 10 nf and the same package size of To SMA connectors ere sodered at Port 1 and Port, and the S-parameters ere measured ith an HP8753C netork anayzer. The structure can be characterized ith a netork of nine ports. The Z matrix of the netork can be ritten as V V e c Z = Z ee ce Z Z ec cc I I e c, (3) here, [ V V ] T Vc [ V V ] T Ve 1 = corresponds to the seven decouping capacitor ports, = corresponds to the to observation ports. For the ports connecting to the decouping capacitors, the currents are reated to the votages as V = Z I, (4) c L c here Z is a diagona matrix ith the diagona eement Z L Lii = R jωl 1 jωc, i i i i = 1 7, here C i = 10 nf is the nomina capacitance, R i is the equivaent series resistance (ESR), and L i is the equivaent series inductance (ESL). The ESR, R i, is dominated by the ESR of the capacitor package since the trace on the board is short and the ESR associated ith the trace due to the skin effect is sma. The ESL, L i, has to contributions, one is the ESL of the capacitor package L c, and the other is the parasitic inductance L t of the oop bounded by the PCB trace and the ground pane. The ESR R i and the ESL L c ere measured as 0.13 Ω and 0.4 nh using an impedance anayzer HP491B ith 16193A test fixture, respectivey, for a package size of The parasitic inductance L t can be cacuated ith (17). The tota parasitic inductance associated ith each capacitor is shon in Fig. 13. The ongest trace ength on the test board is 0.6 cm, corresponding to 0.11λ at 3 GHz hen the effective dieectric constant is 3

24 3.5 [33], hich may cause the impedance at 3 GHz to be 0% off if the inductance vaid at o frequency is used. Hoever, this may sti be acceptabe for engineering purposes. Therefore, the parasitic inductances in Fig. 13 ere used throughout the entire frequency range up to 3 GHz. Substituting (4) into (3) and soving for V e, here 1 tota ( Z L Z cc ) Z ce I e Z ee I e V e = Z ee Z ec =, (5) tota Z ee is the impedance matrix of the to observation ports hen the decouping capacitors are taken into account. The S-parameters can then be cacuated as S Z ee = 50 tota I 1 Z ee 50 tota I, (6) here I is an identity matrix. The reative dieectric constant as ε = 4. 3 and the oss tangent as tan δ = 0. 0 in the cavity mode, corresponding to typica vaues of the FR4 materia. The measured and cavity-modeed S-parameters are shon in Fig. 14. Whie the resuts from the cavity mode do not agree ith the measurements hen ony the ESLs of the capacitor package are considered, the resuts agree e ith the measurements hen the parasitic inductances cacuated ith (17) are incuded. The first nu in S1 is due to the series resonance of the decouping capacitors ith the parasitic inductance. The first bare board resonance is approximatey 580 MHz, hich is not seen in either S1 or S. The resonances in S1 and S are due to the interaction beteen the parasitic inductances and the board resonant structure. The agreement beteen the measurement and the cavity resuts hen the parasitic inductances associated ith the PCB ayout are incuded indicates that the cavity mode in combination ith the cosed-form expression r 4

25 (17) is appicabe to poer integrity designs. The resuts from the CEMPIE simuation are aso shon in Fig. 14. The agreement beteen the measurements and the resuts from CEMPIE are good beo GHz, the discrepancy at high frequency may be due to the coarse mesh on the panes. The mesh size is imited by the memory that as required for soving for the inverse of the Y-matrix extracted from CEMPIE. It may aso be possiby due to the quasi-static Green s function approximation in CEMPIE. B. A Mutiayer Board A three-ayer poer distribution netork as designed to verify hether the cavity mode coud be empoyed to mode mutiayer boards. The board geometry is shon in Fig. 15. The three panes G1, P, and G form to poer deivery structures, namey A and B. Pane G1 is connected to pane G through shorting pin 1, and pane P is connected to pane G through shorting pin. Port 1 is the feeding port, exciting both poer-bus structures A and B. Ports and 3 are the observation ports. At high frequencies, here the skin depth is much ess than the thickness of the panes, the current foing on the upper surface of pane P is decouped from the current foing on the bottom surface of pane P. At the antipads of pane P, the current on the upper surface and the current on the bottom surface must be continuous. Therefore, an equivaent netork representation can be derived ith the cavity mode for the 3-ayer poer-bus structure, as shon in Fig. 16. Then, Z 11, Z 1 and Z 31 can be cacuated from the netork representation. The FDTD method as empoyed to mode the 3-ayer structure as e. In the FDTD modeing, the shorting pins and the center conductor of port 1 are modeed as 1 mm 1 mm square PEC (perfect eectrica conducting) bocks. The antipads in pane P 5

26 are square cutouts ith dimensions of mm mm. The dieectric materia beteen the panes is modeed as a Debye materia ith the same parameters as used in []. The panes ere simuated as PECs for simpicity, though it is aso possibe to simuate them as copper. The resuts from the cavity mode are compared to that from the fu-ave FDTD method in Fig. 17. Good agreement beteen the cavity mode and the fu-ave FDTD method as achieved. The discrepancy in the magnitudes is ithin 3dB for Z 11, Z 1 and Z 31, and the discrepancy in the resonant frequencies is ithin 5% in genera. The good agreement indicates that the cavity mode is appicabe to a mutiayer poer deivery netorks. V. DISCUSSIONS AND CONCLUSIONS The cavity mode, its equivaent circuit, and the segmentation method ere used herein to study irreguar-shaped poer deivery netorks on ayered substrates that use arge area fis for poer and ground. Vias that penetrate the panes ere modeed as ports in the cavity mode. The vias can be associated ith the decouping capacitors, the IC pins of interest, and the ayer transitions of the signas. The ports associated ith a singe via penetrating mutipe panes can then be connected, i.e., the shorting pin 1 in Fig. 16, to mode the poer deivery netork ith mutipe ayers. The ports associated ith the decouping capacitors can be connected to the decouping capacitors ith an ESR and ESL. The ESL of the decouping capacitor incudes the parasitics of the capacitor package as e as the interconnect parasitics of the PCB ayout. Cosed-form expressions of the interconnect parasitic inductance associated ith decouping capacitors is verified ith a fu-ave method. An appication of the proposed method to a compex poer distribution netork is demonstrated in [34]. 6

27 Measurements and fu-ave simuations have been performed to vaidate the approach shon herein. Good agreement has been achieved beteen the resuts from the method, the measurements and/or the fu-ave methods, indicating the suitabiity of appying the proposed method to poer integrity design. REFERENCES [1] W. D. Becker and R. Mittra, FDTD modeing of noise in computer package, IEEE Trans. Compon., Package., Manufact. Techno., B, vo. 17, pp , Aug [] X. Ye, M. Y. Koedintseva, M. Li, and J. L. Dreniak, DC poer-bus design using FDTD modeing ith dispersive media and surface mount technoogy components, IEEE Trans. Eectromagn. Compat., vo.43, pp , Nov [3] M. J. Choi, A. C. Cangearis, A quasi three-dimensiona distributed eectromagnetic mode for compex poer distribution netorks, IEEE Trans. Adv. Packag., vo 5, pp. 8-34, February 00. [4] B. Archambeaut, A. E. Ruei, Anaysis of poer/ground-pane EMI decouping using the partia-eement equivaent circuit technique, IEEE Trans. Eectromagn. Compat., vo.43, pp , Nov [5] J. Fan, J. L. Dreniak, J. L. Knighten, N. W. Smith, A. Orandi, T. P, Van Doren, T. H. Hubing, and R. E. Dubroff, Quantifying SMT decouping capacitor pacement in DC poer-bus design for mutipayer PCBs, IEEE Trans. Eectromagn. Compat., vo. 43, pp , Nov

28 [6] K. Araki, H. Kubota, T. Watanabe, and H. Asai, What-if anaysis of muti-ayer PWB embedded in the digita sti camera ith parae-distributed FDTD-based simuator BLESS, in Proc. 1 th Topica Meeting Eect. Performance Eectron. Packag., Princeton, NJ, 003, pp [7] T. Okoshi, Panar Circuits for Microaves and Lightaves, Springer-Verag Berin Heideberg, [8] Y. Lo, D. Soomon, W. Richards, Theory and experiment on microstrip antennas, IEEE Trans. Antennas and Propagt., vo. 7, pp , March [9] G.-T. Lei, R. W. Techentin, B. K. Gibert, High-frequency characerization of poer/ground-pane structures, IEEE Trans. Microave Theory and Tech., vo. 47, No. 5, May [10] N. Na, J. Choi, M. Saminathan, J. P. Libous ad D. P. O Connor, Modeing and simuation of core sitching noise for ASICs, IEEE Trans. Adv. Packag., vo. 5, No. 1, February 00. [11] M. Xu, T. H. Hubing, Estimating the poer bus impedance of printed circuit boards ith embedded capacitance, IEEE Trans. Adv. Packag., vo. 5, No. 3, August 00. [1] T. Okoshi, Y. Uehara, and T. Takeuchi, The segmentation method An approach to the anaysis of microave panar circuits, IEEE Trans. Microave Theory and Tech., vo. MTT-4, pp , Oct [13] R. Chadha and K. C. Gupta, Segmentation method using impedance matrices for anaysis of panar microave circuits, IEEE Trans. Microave Theory and Tech., vo. MTT-9, pp , January

29 [14] W.F. Rechards and Y. T. Lo, Theoretica and experimenta investigation of a microstrip radiator ith mutipe umped inear oads, Eectromagnetics, vo. 3, No. 3-4, pp , [15] F. W. Grover, Inductance Cacuations, Working Formuas and Tabes, Ne York, D. VanNostrand, [16] C. R. Pau, Introduction to Eectromagnetic Compatibiity, John Wiey and Sons Inc., Ne York 199. [17] C. Hoer and C. Love, Exact Inductance Equations for Rectanguar Conductors With Appications to More Compicated Geometries, Journa of Research of the Nationa Bureau of Standards C. Engineering and Instrumentation, vo.69c, pp , [18] W. F. Richards and Y. T. Lo, "A ide-band mutiport theory for thin microstrip antennas," in Proc. of IEEE Int. Symp. Antennas Propagat., Jun. 1981, pp [19] R. E. Coin, Fied Theory of Guided Waves, Ne York, IEEE press, nd ed., 1996, Appendix 6. [0] Z. L. Wang, O. Wada, Y. Toyota, and R. Koga, An improved cosed-form expression for accurate and rapid cacuation of poer/ground pane impedance in mutipayer PCBs, in Proc. Of Symp. Eectromagn. Theory, EMT-00-68, pp17-3, Toyama, Japan, Oct [1] K. F. Lee, and W. Chen, Advances in Microstrip and Printed Antennas, Ne York, John Wiey, 1997, Chapter 5. 9

30 [] J. Mao, C. Wang, L. Zhang, R. E. DuBroff, J. L. Dreniak, A. Orandi, and G. Antonini, "An efficient anaysis method for the poer bus impedance," in Proc. of EMC Europe 004, Eindhoven, Netherands, September 004, pp [3] J. Fan, W. Cui, J. L. Dreniak, T. P. Van Doren, and J. L. Knighten, Estimating the noise mitigation effect of oca decouping in printed circuit boards, IEEE Trans. Adv. Packag., vo. 5, No., May 00. [4] T. H. Hubing, J. L. Dreniak, T. P. Van Doren, and D. M. Hockanson, Poer bus decouping on mutipayer printed circuit boards, IEEE Trans. Eectromagn. Compat., vo. 37, pp , May [5] I. Novak, Z. Yang, L. Wojeoda, L. Smith, H. Ishida, and M. Shimizu, Inductance of bypass capacitors: ho to define, ho to measure, ho to simuate, in TecForum TF7 of DesignCon 005, Santa Cara, CA, January 005. [6] W. F. Richards, J. R. Zinecker, R. D. Cark and S. A. Long, Experimenta and theoretica investigation of the inductance associated ith a microstrip antenna feed, Eectromagnetics, vo 3, pp , Sept [7] J. Fan, J. L. Dreniak, J. L. Knighten, Lumped-circuit mode extraction for vias in mutipayer substrates, IEEE Trans. Eectromagn. Compat., vo. 45, No., May 003. [8] J. Fan, H. Shi, A. Orandi, J. L. Knighten and J. L. Dreniak, Modeing DC poer-bus structures ith vertica discontinuities using a circuit extraction approach based on a mixed-potentia integra equation formuation, IEEE Trans. Adv. Packag., vo. 4, No., May

31 [9] A. E. Ruehi, Inductance cacuations in a compex integrated circuit environment, IBM J. Res. And Deveopment, vo. 16, no. 8, pp , Sept [30] A. E. Ruehi, and P. A. Brennan, Efficient capacitance cacuations for threedimensiona muticonductor systems, IEEE Trans. Microave Theory Tech., MTT-1, no., pp. 76-8, Feb [31] A. E. Ruehi, Equivaent circuit modes for three dimensiona muticonductor systems, IEEE Trans. Microave Theory Tech., MTT-, no.3, pp16-1, Mar [3] S. M. Rao, D. R. Witon, A. W. Gisson, Eectromagnetic scattering by surfaces of arbitrary shape, IEEE Trans. Antenna and Propagat., vo. AP-30, no. 3, pp , May 198. [33] D. M. Pozar, Microave Engineering, John Wiey & Sons, Inc., Second Edition, pp.16, [34] J. Mao, Circuit mode extraction in digita and RF circuits using the partia eement equivaent circuit (PEEC) method, Ph.D. thesis, Dept. Eec. Eng., Univ. Missouri Roa,

32 List of Figures Fig. 1. The equivaent circuits of a rectanguar and an equiatera trianguar poer distribution netork: (a) An equivaent circuit of a rectanguar poer distribution netork, (b) An equivaent circuit of an equiatera trianguar poer distribution netork Fig.. The accuracy of the cavity mode as a function of the number of modes for an equiatera trianguar structure ith atera ength of a = 0 cm Fig. 3. A SPICE equivaent circuit for the fast agorithm Fig. 4. Comparison of the measurements, the reguar cavity mode, and the fast agorithm for the input impedance of the -ayer board ith a shorting pin Fig. 5. Iustration of the segmentation method for a poer distribution netork of an irreguar shape Fig. 6. An irreguar shaped poer/ground structure for the demonstration of the segmentation method Fig. 7. Sef and transfer impedances of the poer/ground structure ith an irreguar shape Fig. 8. Iustration of parasitic inductances associated ith a decouping capacitor Fig. 9. Decomposing oop into to contributions to cacuate the inductance Fig. 10. Discretization in CEMPIE for modeing the parasitics associated ith a decouping capacitor. (a) Mesh of the microstrip, and, (b) mesh of the return pane39 Fig. 11. Parasitic inductance varying ith trace ength and trace idth. (a) Parasitic inductance, and, (b) reative error Fig. 1. Iustration of current distribution on the trace hen the ength is short. (a) the trace is short and narro, and, (b) the trace is short and ide Fig. 13. A three-ayer rectanguar poer deivery netork ith seven decouping capacitors. Units: cm Fig. 14. S-parameters of the poer distribution netork ith seven decouping capacitors Fig. 15. Geometry of a 3-ayer poer-bus structure. Units are in cm Fig. 16. Netork representation of the 3-ayer poer-bus structure Fig. 17. Comparison of impedances from the cavity mode and that from the FDTD approach for the 3-ayer poer deivery structure

33 C 0 G 01 L 01 C 0 G mn L mn C N 00i N 01i N mni N 00j N 01j N mnj Port i Port j (a) C 0 L mn C 0 G mn 1 1 N 100i N 00i N 1mni N mni N 100j N 00j N 1mnj N mnj Port i Port i (b) Fig. 1. The equivaent circuits of a rectanguar and an equiatera trianguar poer distribution netork: (a) An equivaent circuit of a rectanguar poer distribution netork, (b) An equivaent circuit of an equiatera trianguar poer distribution netork. 33

34 Zin (dbohm) Measurement Cavity-0X0 Cavity-40X40 Cavity-80X80 Cavity-00X Frequency (GHz) Fig.. The accuracy of the cavity mode as a function of the number of modes for an equiatera trianguar structure ith atera ength of a = 0 cm. Port i N 00i N 01i N mni C 0 C 0 C 0 L 01 L mn G 01 G mn L ij L ii L jj N 00j N 01j N mnj Port j. Fig. 3. A SPICE equivaent circuit for the fast agorithm. 34

35 40 30 Measurement Cavity mode Fast doube summation Fast singe summation 0 Zin (dbω) 10 0 (0, 9) Port 1 (1., 6) -10 Shorting pin (3, 3) -0 (0, 0) (15., 0) Unit: cm Frequency (GHz) Fig. 4. Comparison of the measurements, the reguar cavity mode, and the fast agorithm for the input impedance of the -ayer board ith a shorting pin. 35

36 I c V d Vc I d I q V p I p β Vq p α c d q Fig. 5. Iustration of the segmentation method for a poer distribution netork of an irreguar shape. γ Port 1 Port Port 1 Ports for segmentation Port 96 Unit: mm Fig. 6. An irreguar shaped poer/ground structure for the demonstration of the segmentation method. 36

37 40 30 Z11 (dbω) Measured Cavity Frequency (GHz) Z1 (dbω) Measured Cavity Frequency (GHz) Fig. 7. Sef and transfer impedances of the poer/ground structure ith an irreguar shape. 37

38 capacitor Loop 3 => L 3 L Loop => L Layer 1 Layer Layer 3 Loop 1 => L 1 Fig. 8. Iustration of parasitic inductances associated ith a decouping capacitor. t Port 1 d b h s (a) decompose t (b) h s (c) d Fig. 9. Decomposing oop into to contributions to cacuate the inductance. 38

39 (a) Fig. 10. Discretization in CEMPIE for modeing the parasitics associated ith a decouping capacitor. (a) Mesh of the microstrip, and, (b) mesh of the return pane (b) 39