Implementing the Elliptic Curve Method of Factoring in Reconfigurable Hardware
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1 Implementing the Elliptic Curve Method of Factoring in Reconfigurable Hardware Kris Gaj Soonhak Kwon Patrick Baier Paul Kohlbrenner Hoang Le Khaleeluddin Mohammed Ramakrishna Bachimanchi George Mason University
2 GMU Team Computer Engineer / Cryptographer Mathematicians/ Cryptographers Kris Gaj Ph.D in Electrical Engineering, Warsaw University of Technology, Poland Associate Professor at George Mason University Soonhak Kwon Ph.D in Mathematics, Johns Hopkins University Maryland, U.S Visiting professor at GMU on leave from Sungkyunkwan University, Suwon, Korea Patrick Baier D. Phil. in Mathematics, Oxford University Oxford, U.K Affiliated with George Washington Univeristy
3 GMU Team Hardware design Hoang Le Ramakrishna Bachimanchi Khaleeluddin Mohammed MS in Computer Engineering students ECE Department George Mason University Virginia, U.S.A.
4 What is ECM? Elliptic Curve Method of Factoring Lenstra 1985 Phase 1 Brent, Montgomery Phase 2 q N < 50 bits Factoring time depends mainly on the size of factor q
5 ECM in the Number Field Sieve (NFS) Polynom ial Selection Relation Collection Sieving bit numbers Trial Factoring (ECM ) Linear Algebra Square Root
6 Elliptic Curve 2 3 Y X X p = mod p ( = 23) Y Points fullfiling the equation of the curve P=(3,13) D Doubling P=(6,19) Q=(7,12) R=P+Q=(13,7) X A 2P=P+P=(7,11) Addition + special point ϑ (point at infinity) such that: P + ϑ = ϑ+ P= P P: P,2 P,3 P,..., np= ϑ,( n+ 1) P= P, 2P all points of the curve
7 Projective vs. Affine coordinates affine coordinates addition and doubling require inversion projective coordinates P a =(X P, Y P ) P p =(x P, y P, z P ) addition and doubling can be done without inversion projective coordinates for Montgomery form of the curve addition and doubling do not require y coordinate (y coordinate can be recovered from x and z at the end of a long chain of computations) P pm = (x P: : z P ) ϑ = (0 : : 0)
8 ECM Algorithm Inputs : N E P 0 B 1 B 2 Outputs: q number to be factored elliptic curve point of the curve E : initial point smoothness bound for Phase1 smoothness bound for Phase2 - factor of N, 1 < q N or FAIL
9 0 0 ECM algorithm Phase 1 ei 1: k p such that p - consecutive primes B 2: Q kp = ( x : : z ) 3: q gcd( z, N) p i i Q : if q > 1 5: return q (factor of N) 6: else 7: go to Phase 2 8: end if Q Q i precomputations ei e - largest exponent such that p B i 1 main computations postcomputations i 1
10 ECM algorithm Phase 2 09: d 1 10: for each prime p = B to B do : ( x, y, z ) pq pq pq pq 12: d d z (mod N) pq 13: end for 14: q gcd( d, N) 15: if q > 1 then 16: return q 17: else 18: return FAIL 19: end if 0 main computations postcomputations
11 Phase 1 Numerical example N = = E : y 2 = x x + 1 (mod ) P 0 = (5 : : 1) B 1 = 20 k = = kp 0 = ( : : ) gcd ( ; ) = 1361
12 Hierarchy of Elliptic Curve Operations ECM Host computer Top level Medium level Point addition P+Q k P Scalar multiplication 2P Point doubling Elliptic curve point operations Control unit Low level x y mod N x+y mod N x-y mod N Moduar multiplication Modular addition Modular subtraction Modular arithmetic (ring operations) Functional units
13 Our architecture : Top-level view FPGA Instruction memory Control Unit Phase1 & Phase2 I/O Host computer ECM Units Global memory RAM Host computer pre-computes -E, P 0, k and post-computes - final gcds
14 ECM in Hardware Previous Proof-of-Concept Design Pelzl, Šimka, SHARCS Feb 2005 Kleinjung, Franke, FCCM Apr 2005 Priplata, Stahlke, IEE Proc. Oct 2005 Drutarovský, Fischer, Paar
15 Modifications compared to Pelzl, Šimka host Internal vs. External control Pelzl, Šimka µc control ARM7 FPGA ECM units Ours host control FPGA ECM units Memory management Pelzl, Šimka Ours suboptimal use of bit tables & consolidation memory space of memory resources Pelzl, Šimka time Functional units Ours MUL ADD/SUB MUL1 MUL2 ADD/SUB Montgomery multiplier Pelzl, Šimka Ours Based on Based on Tenca, Koc McIvor, McLoone CHES 1999 et al. IEEE Trans. Comp. Asilomar word-based CPA full-length CSAs and/or CSA word-length CPAs
16 Resources utilization in time Phase 1 Area 100% ADD/SUB (6%) MUL 1 (43%) MUL 2 (43%) Control Unit (8%) Time
17 Phase 2 Parameter D D=30= x 32 Memory of ECM Unit 16 φ(d)+120 words x 2 D=210= x words 184 words 72.1 ms Phase 2 Execution Time 35.5 ms / 2
18 Comparison with the Proof-of-Concept Design by Pelzl and Šimka: Timing (198-bit numbers N; B1 = 960, B2 = 57000) 527 ms Phase 1 Phase ms Factor of x 9.3 Factor of x 7.4 Factor of x ms 72 ms 36 ms Pelzl/Šimka Ours Major Contributors to the speed up: Pelzl/Šimka - Different design for the multiplier ( x 5 ) - Two multipliers working in parallel ( x 1.9 ) Ours D=30 Ours D=210 - Different parameter of Phase 2, D ( x 2 )
19 Comparison with the Proof-of-Concept Design by Pelzl and Šimka Resources (D=30) Memory (BRAMs) 44 (27%) Area (CLB Slices) 16% ECM Units / Virtex 2000E FPGA 7 2 (1.3%) 6% 3 Pelzl/Šimka Factor of x 22 Ours Pelzl/Šimka Ours Factor of x 2.7 Pelzl/Šimka Ours Limited by Limited by BRAMs CLB Slices Factor of x 2.33
20 Modifications compared to Pelzl, Šimka host Internal vs. External control Pelzl, Šimka µc control ARM7 FPGA ECM units Ours host control ECM units Memory management Pelzl, Šimka Ours suboptimal use of bit tables & consolidation memory space of memory resources Prime table Pelzl, Šimka time Functional units Ours MUL ADD/SUB MUL1 MUL2 ADD/SUB Montgomery multiplier Pelzl, Šimka Ours GCD-table Based on Based on Tenca, Koc McIvor, McLoone CHES 1999 et al. IEEE Trans. Comp. Asilomar word-based CPA full-length CSAs and CSA word-length CPAs
21 Comparison with the Proof-of-Concept Design by Pelzl and Šimka Time x Area Product Assuming the same control unit and the same memory management (i.e., significantly improved design in Pelzl/Šimka): Improvement Phase 1 x 3.4 Phase 2 x 5.6
22 Performance to cost ratio Number of Phase 1 & Phase 2 operations per second per $ x 16 x Spartan 3 Virtex II Spartan 3E Virtex 4 XC3S XC2V XC3S XC4VLX Low-cost High-performance Low-cost High-performance
23 339 FPGAs vs Microprocessors # Phase 1 & Phase 2 computations per second x Pentium 4 Xeon 2.8 GHz 7.4 x x.93 x Virtex II XC2V Spartan 3 XC3S Test program (No optimizations) GMP-ECM: Phase1 optimizations off GMP-ECM All optimizations on
24 Experimental testing using SRC 6 reconfigurable computer Basic unit: 2 x Pentium Xeon 3 GHz 2 x Xilinx Virtex II FPGA XC2V6000 running at 100 MHz SRC 6 from SRC Computers 24 MB of the FPGA-board RAM Fast communication interface between the microprocessor board and the FPGA board, 1600 MB/s Multiple basic units can be connected using Hi-Bar Switch and Global Common Memory
25 Results of experimental testing using SRC 6 reconfigurable computer Time (µs) 1, , , Legend: 1 General pre-computations independent of N 2 Pre-computations (µp) 3 Transfer in (µp FPGA) 4 Main computations (Phase 1 & 2) (FPGA) 5 Transfer out (FPGA µp) 6 Post-computations (µp) µp & FPGA Percentage 3.6% 0.5% 95.3% 0.4% 0.2% 100%= 38,060 µs 100%= 36,611 µs Before optimization After optimization µp FPGA Percentage 0.5% 99.1% 0.4%
26 Conclusions Hardware implementations of ECM provide a substantial improvement vs. optimized software implementations in terms of the performance to cost ratio low-cost FPGAs vs. microprocessors > 10 x Best environment for prototyping of hardware implementations of codebreakers general-purpose reconfigurable computers (e.g., SRC) Best environment for the final design of the cost-optimized cipher breaker special-purpose machines based on low-cost FPGAs (or ASICs for very high volumes)
27 Thank you! Questions???
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