A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield

Transcription

1 A Global Minimum Clock Distibution Netwok Augmentation Algoithm fo Guaanteed Clock Skew Yield Bao Liu, Andew B. Kahng, Xu Xu, CSE Depatment UC San Diego Jiang Hu and Ganesh Venkataaman ECE Depatment Texas A&M Univesity La Jolla, CA College Station, TX Tel: Tel: Fax: Fax: Abstact Nanomete VLSI systems demand obust clock distibution netwok design fo inceased pocess and opeating condition vaiabilities. In this pape, we popose minimum clock distibution netwok augmentation fo guaanteed skew yield. We pesent theoetical analysis esults on an inseted link in a clock netwok, which scales down local skew and skew vaiation, but may not guaantee global skew and skew vaiation eduction in geneal. We popose a global minimum clock netwok augmentation algoithm, which insets links simultaneously between all neaest sink pais, apply ule-based link emoval, and pefom link consolidation by Steine minimum tee constuction fo wielength eduction with guaanteed clock skew yield. Ou expeimental esults show that ou poposed algoithm achieves dominant clock netwok augmentation solutions, e.g., an aveage of 16% clock skew yield impovement, 9% maximum skew eduction, and 25% eduction of clock skew vaiation standad deviation with identical wielength compaed with pevious best clock netwok link insetion methods [11]. I. INTRODUCTION The clock distibution netwok is one of the most citical pats in a VLSI design, significantly affects system pefomance and total chip powe consumption. Taditional clock distibution netwok synthesis tagets cost minimization and zeo-skew ealization. As VLSI system pefomance inceases, pefomance magins decease and equie geate contol of clock signal distibution, notably to achieve educed clock skew. On the othe hand, inceasing vaiations in the VLSI manufactuing pocess and system opeating conditions cause geate inte-chip and inta-chip vaiations, e.g., inteconnect width, tansisto channel length, tansisto theshold voltage, supply voltage. These inceased on-chip vaiations lead to inceased clock skew vaiation in a chip. The eve-inceasing pefomance equiement and vaiability in a VLSI design demand new clock distibution netwok design techniques fo obustness enhancement and impoved vaiation toleance. Clock skew eduction techniques include the following. (1) Insetion delay eduction. Insetion delay is the souce-to-sink delay in a clock netwok. A educed insetion delay is moe likely associated with educed delay and skew vaiation. This suggests shot path lengths and lage buffes in a clock distibution netwok. (2) Balanced / symmetic clock tee constuction. Balancing a clock distibution netwok educes clock skew, e.g., with an identical numbe of buffes in each souce-to-sink path, which, at the same level, ae of identical sizes and dive the same load capacitance with the same inteconnect subtee topology [11]. Physical symmety of a clock netwok also helps to educe skew, e.g., in an H-tee stuctue. In high-pefomance and high-eliability designs, clock distibution netwoks ae implemented in symmetic non-tee stuctues, e.g., gids on a single dedicated outing laye. A typical high-pefomance/eliability clock distibution netwok includes thee levels: (1) a symmetic tee at the top level; (2) a gid; and (3) Steine tees which connect clock pins of each sequential element to the clock distibution gid. Such a clock netwok achieves educed clock skew and impoved pocess vaiation obustness at the cost of outing esouce and powe consumption. Recent methodologies have migated high-pefomance clock distibution netwok design techniques to ASIC designs. Fo example, including exta outing in a clock tee is poposed as an effective technique fo clock skew and skew vaiation eduction in an ASIC design with minimum wielength incease. Seveal clock netwok augmentation appoaches ae as follow. Link insetion based on simple heuistic ules and minimum weighted matching is poposed in [8], and impoved in [9]. An inseted link bings (1) exta esistive connection, and (2) exta inteconnect capacitance to a clock netwok. The authos of [8] poposed to adjust clock outing to estoe capacitance balance in a clock netwok afte link insetion, and estict link insetion between nodes with zeo nominal skew, which does not affect the delay to any othe node in the clock netwok. An iteative link insetion scheme based on statistical skew vaiation analysis was pesented in [2]. This method is guided by moe accuate skew and skew vaiation analysis, and applies ank-one update fo matix inveses fo efficiency impovement of iteative skew vaiation analysis. The authos popose to include dummy capacitance to estoe capacitance balance in a clock netwok afte link insetion. Fo moe pactical application, e.g., in a buffeed multi-level clock netwok, techniques have been poposed to addess pactical issues, e.g., to avoid the multi-dive inteconnect poblem intoduced by link insetion by poposed design citeia [11]. In this pape, ou contibutions ae as follows. We fomulate the clock skew eduction poblem as a paametic yield optimization poblem, based on statistical /07/$ IEEE. 25

2 analysis in an on-chip vaiation model. We popose minimum clock netwok augmentation fo guaanteed skew yield, i.e., to educe wielength in an augmented clock netwok while guaanteeing the pobability fo the global skew of the clock netwok to meet the equied skew bound. We pesent theoetical esults fo iteative link insetion in an RC inteconnect. We pove that a puely esistive link in an unbuffeed RC clock netwok scales down local +γ skew between the two nodes by a atio of, and scales down the dive admittance diffeence of the two nodes by the same atio in a buffeed RC clock netwok. In geneal, an inseted link does not guaantee global skew and skew vaiation eduction in an RC clock netwok. We popose minimum clock netwok augmentation fo guaanteed skew yield, which compises thee steps: (1) simultaneous link insetion between neaest sink pais in a clock netwok, (2) ule-based link emoval with guaanteed clock skew yield, and (3) link consolidation by Steine minimum tee constuction fo futhe wielength eduction. We validate ou poposed method with SPICE-based Monte Calo simulations consideing spatially coelated vaiations. Ou expeimental esults show that ou poposed algoithm achieves substantially dominatin solutions compaed with pevious best clock netwok link insetion methods [11]. The emainde of the pape is oganized as follows. We pesent existing on-chip vaiation models and clock netwok link insetion methods in Section II, and give ou poblem fomulation in Section III. We pesent ou theoetical analysis esults in Section IV, and popose ou mesh-eduction-based novel clock netwok augmentation method in Section V. We pesent ou expeimental esults in Section VI, and conclude in Section VII. II. OCV AND PREVIOUS LINK INSERTION METHODS A. On-Chip Vaiation Technology advancement in VLSI manufactuing enables continuous aggessive scaling of tansisto and inteconnect dimension, which esults in an eve inceasing numbe of components integated in a single chip and continuous system pefomance impovement. On the othe hand, the latest VLSI manufactuing pocess technologies also intoduce inceased vaiabilities of pocess and envionmental paametes. As a esult, moden VLSI design and analysis tools take into consideation both inte-chip and inta-chip vaiations. The inte-chip vaiations ae the same fo all components in a chip. The inta-chip vaiations epesent vaiability between components in a chip, and include spatially coelated vaiations, and puely uncoelated vaiations. Theefoe, a pocess / design paamete p can be decomposed into its nominal value p 0, global o intechip vaiation ε 1, spatially coelated vaiation ε 2, and puely uncoelated vaiation ε 3 as follows. p = p 0 + ε 1 + ε 2 + ε 3 (1) Pelgom [7] poposed a spatial coelation model in 1998, which chaacteizes the diffeence of a paamete of two devices in a chip by its standad deviation, as follows. σ 2 p = A p WL + S2 pd 2 (2) whee W and L ae espectively tansisto channel width and length of the two devices, D is the distance between the two devices, A p and S p ae coefficients. A latest spatial coelation model is poposed in [3], which obseves a linea elationship between the distance x of two devices, and the coelation ρ of a paamete of the two devices, as follows. ρ = { 1 x X L (1 ρ B ) (x X L ) ρ B x > X L (3) whee the coelation becomes ρ B if the two devices ae moe than X L distance apat. B. Pevious Link Insetion Methods Pevious clock netwok link insetion methods identify the candidate pais with tee-topology based algoithms [11] o nominal delay based ules [8]. Thee heuistic citeia ( ules ) [9] ae poposed fo selecting a pai of nodes in a clock netwok fo ceation and insetion of a new link: 1. small esistance α = R l R α loop max, 2. small capacitance β = C l 2 (R u,u R w,w ) β max,and 3. small depth of common ancesto node γ [9]. A fouth ule is poposed to avoid epeated link insetions between two subtees [11]. These heuistic ules povide vey efficient optimization algoithms, and ae moeove extended in [11] to statistical clock skew eduction unde pocess vaiation. A moe accuately guided and less efficient link insetion scheme is poposed in [2]. This method applies geedy iteative link insetion in a clock netwok based on statistical clock skew vaiation analysis on a fist ode vaiation model. The Elmoe delay, i.e., the G 1 C matix of the clock netwok, is updated incementally duing each link insetion. A ank-one update method is applied fo bette efficiency, which updates matix invese in O(mnx) time, whee m is the numbe of andom vaiables, n is the numbe of nodes, x is the numbe of inseted links. In summay, pevious woks have the following limitations. (1) Clock skew yield is not guaanteed. (2) They do not conside link emoval. (3) Rules based on nominal delay in the oignial clock outing tee may not accuately eflect the augmented clock netwok and guide the link insetion pocedue to achieve the optimum augmentation. Ou wok addesses all thee of these limitations. III. MINIMUM CLOCK NETWORK AUGMENTATION FOR GUARANTEED SKEW YIELD We conside a clock distibution netwok as an RC inteconnect, whee the esistance and the capacitance fo an intecon- 26

3 nect segment (i, j) of length l and width w ae given by ij = l w c ij = cwl (4) whee and c ae unit squae esistance and unit squae capacitance of inteconnect espectively. We take into account the following significant on-chip vaiations fo clock netwok analysis and optimization in this pape (as in [11]). 1. Inteconnect vaiation, e.g., in width, height, and intelaye dielectic thickness, which esults in inteconnect esistance and capacitance vaiations. 2. Sink capacitance vaiation, which comes fom vaiation of gate capacitance of the eceive tansistos of an inteconnect. 3. Tansisto channel length vaiation, which affects diving stength of the buffes in a clock netwok. 4. Supply voltage dop vaiation, which leads to timing degadation fo the buffes in a clock netwok. We conside global, spatially coelated, and uncoelated components fo each vaiation, and follow the spatial coelation ule (3) obseved in [3]. We define clock skew yield, Y s, as the pobability that the clock skew is within the clock skew bound, i.e., Y s = P(s < U) (5) We now fomulate the guaanteed skew yield minimum clock netwok augmentation poblem as follows. 1 Poblem 1 (Minimum Clock Netwok Augmentation) Given 1. a clock distibution inteconnect netwok N, 2. clock netwok sinks K, 3. clock buffes B, 4. inteconnect unit squae esistance, 5. inteconnect unit squae capacitance c, 6. inteconnect width w ij fo inteconnect segment (i, j) N, its mean µ(w ij ), vaiance σ 2 (w ij ) and coelation ρ(w ij,w lk ) between inteconnect segments (i, j) and (l,k), 7. sink capacitance c k fo each sink k K, its mean µ(c k ), vaiance σ 2 (c k ) and coelation ρ(c k,c l ) between sinks k and l, 8. gate length L g b fo each buffe b B, its mean µ(lg b ),vaiance σ 2 (L g b ) and coelation ρ(lg b1,lg b2 ) between gates b 1 and b 2, 9. supply voltage Vb dd fo each buffe b B, its mean µ(vb dd), vaiance σ 2 (Vb dd ) and coelation ρ(v dd two gates b 1 and b 2, 10. clock skew uppe bound U, 11. equied skew yield Y s, b1,v dd b2 ) between find an augmented clock netwok N with minimum wielength which guaantees the equied skew yield Y s. 1 A moe genealized poblem fomulation is independent of the extaction and on-chip vaiation models that we pesent hee (which ae consistent with those of the pevious methods), and ou poposed method can also be extended to be applied to moe advanced extaction and on-chip vaiation models. A. Local Skew IV. THEORETICAL ANALYSIS In this section, we deive theoetical esults fo the effect of an inseted link in an RC clock distibution netwok on local skew (vaiation), i.e., the skew (vaiation) between the two nodes which the inseted link connects. In an RC clock netwok, we define the conductance matix G n n,wheenisthenumbe of nodes in the clock netwok excluding the clock souce s, G ij = 1 ij is the negative ecipocal of the esistance between two nodes i and j, and 1 G ii = j i ij + 1 is includes all esistance between node i and its neighbos j, including the esistance is between node i and the clock souce s. We define the capacitance matix C n n,whee C ii = c i is the gound capacitance of node i, C ij = 0,i j. The Elmoe delays fom the clock souce s to the sinks ae given by a n 1 vecto D E n 1 = G 1 CI, wheei is a n 1 unit vecto, I i = 1, 1 i n. Highe ode, e.g., p-th ode moments of the delays ae given by (G 1 C) p I [6]. Theoem 1 Inseting a puely esistive link in an unbuffeed RC clock netwok scales down the skew and the skew vaiation between the two nodes, e.g., by a atio of, whee is the +γ inseted link esistance, γ = G 1 ii + G 1 jj 2G 1 ij. Poof. Inseting a esistive link between nodes i and j updates the conductance matix G by G = G + gvv T (6) whee g = 1, V is a n 1 vecto, V i = 1, V j = 1, V k i, j = 0, V T is tanspose of vecto V. Applying the ank-one update fo matix inveses [5, 4] gives whee (G + gvv T ) 1 = G 1 + βg 1 VV T G 1 (7) β = 1 + γ γ = V T G 1 V = G 1 ii + G 1 jj 2G 1 ij (8) An enty in G 1 VV T G 1 is given by (G 1 VV T G 1 ) kl =(G 1 ik G 1 jk )(G 1 il G 1 jl ) (9) We have the local skew between nodes m and n as follows. (G 1 CI) m (G 1 CI) n = ((G 1 mq G 1 nq ) q + β(g 1 im G 1 jm G 1 in + G 1 Fo m = i,n = j, thisgives jn )(G 1 iq G 1 jq ))C q (10) (G 1 CI) i (G 1 CI) j = (1 + βγ)(g 1 iq G 1 jq )C q q = + γ ((G 1 CI) i (G 1 CI) j ) (11) 27

4 Highe ode moments follow the same scaling atio. ((G 1 C) p I) i ((G 1 C) p I) j = (1 + βγ)((g 1 iq )p (G 1 jq )p )C q q = + γ (((G 1 C) p I) i ((G 1 C) p I) j ) (12) Theefoe, inseting a puely esistive link scales local skew and local skew vaiation by a atio of This atio of +γ. +γ is consistent with pevious esults. E.g., in is the esistance of the path a tee stuctue clock netwok, G 1 ii fom souce s to sink i, G 1 jj souce s to sink j, andg 1 is the esistance of the path fom ij is the common path esistance of sinks i and j. In [9], the fist heuistic ule is based on the atio of the link esistance and the esistance of the loop which is fomed by the link. Following the same line of deivation, we have the following theoem on the effect of an inseted puely esistive link on the scaling of the dive admittance moments, which ae given by G 1 B, G 1 CG 1 B,...(G 1 C) p G 1 B, espectively, whee B is a n 1 vecto, B i = 1 if node i is a dive, B i = 0 othewise [6]. Theoem 2 Inseting a puely esistive link between two nodes with diffeent dives in a buffeed RC clock netwok scales down the diffeence of the dive admittance moments by a atio of +γ G 1 jj 2G 1 ij., whee is the inseted link esistance, γ = G 1 ii + Poof. Omitted due to space limitation. The scaling atio of the dive gate delay diffeence may diffe due to the non-lineaity between gate delay and dive admittance. B. Global Skew As we pesent in the pevious section, link insetion in an RC clock netwok is an effective technique to educe local skew and local skew vaiation. In this section, we study the effect of an inseted link on global skew (vaiation), i.e., the maximum skew (vaiation) between two nodes in a clock distibution netwok. We obseve that an inseted link in a clock netwok has two effects: (1) esistive connection between the two nodes, and (2) updated capacitance balance in the netwok. The augmented (1) esistive connection helps to educe local skew and local skew vaiation between two nodes (Theoem 1), but, in geneal, does not guaantee global skew o skew vaiation eduction. One eason is the global effect, e.g., an inseted puely esistive link between a maximum delay node i and a minimum delay node j educes the delay to node i,which may also educe the delay to an upsteam node k in the path between the clock souce s and node i. When node k is a second minimum delay node, e.g., with a delay of d min + δ, this link insetion may incease the global clock skew. Howeve, this scenaio is less likely to occu in a balanced clock distibution netwok, whee clock sinks have equal depth. The othe moe common eason fo an inseted link not to guaantee skew and skew vaiation eduction is the (2) updated capacitance balance effect. E.g., an inseted link inceases the capacitance at the two sinks and inceases the delay to the two sinks, which altes the skew between each of the two nodes and any othe sink in the clock netwok. This capacitive effect of an inseted link suggests a global optimization of the poblem, i.e., a local / patial link insetion cannot guaantee global capacitance balancing and minimized global skew. An iteative link insetion pocedue may not have monotone clock skew (vaiation) eduction in achieving the minimum skew (vaiation), i.e., thee may not exist an iteative link insetion pocedue with monotone clock skew eduction which achieves the minimum skew (vaiation). We popose a batched link insetion scheme, e.g., to inset a lage numbe of links at the same time fo guaanteed clock skew yield, and poceed with a post-pocessing pocedue to educe wielength by link emoval. We base link emoval pocedue on the analysis esult of the skew yield of the augmented clock netwok, which gives moe accuate analysis esults fo the final augmented clock netwok. V. OPTIMIZATION ALGORITHM Based on the analyses of the peceding section, we popose a new clock distibution netwok augmentation algoithm fo wielength eduction with guaanteed clock skew yield. Ou poposed algoithm (see the Algoithm 1 template) has thee main steps: 1. Link insetion between all pais of sinks which ae within a shot distance ε fo guaanteed clock skew yield, as is suggested by Theoems 1 and 2, e.g., to inset links of small esistances. 2. Link emoval based on statistical yield analysis (e.g., SPICE Monte Calo simulation) and two heuistic ules, fo wielength minimization with minimum skew yield compomise. 3. Link consolidation by eplacing minimum spanning tees with Steine minimum tees fo futhe wielength eduction. The untime of the poposed algoithm is dominated by statistical clock netwok analysis. The poposed Algoithm 1 appoach has thee majo advantages. Smooth optimization. Iteative link insetion stating with a tee stuctue may not obseve monotone global skew eduction, e.g., due to the updated capacitance balance effect of the inseted links. Removing links fom a mesh stuctue clock netwok leads to moe easy contol of the optimization pocess, e.g., with minimum clock skew yield compomise. Accuate analysis. We emove links based on the statistical analysis esult fo the skew vaiation in the augmented clock netwok (afte step (1) link insetion), which is vey close to the final augmented clock netwok (afte step (3)), and is much moe accuate than the pevious methods which inset links based on the nominal delay analysis in the oiginal clock tee. Ease of physical outing of the clock links. In ou algoithm, we include all (shotest) links at the same time. 28

5 Clock links ae evenly distibuted in the layout plane with minimum wielength, with possible outing obstacle consideation. Thee is no hassle of ip-up and e-oute as in an iteative clock link insetion scheme. Algoithm 1: Clock Netwok Augmentation fo Guaanteed Skew Yield Input: Clock Distibution Netwok N, buffes B, sinks S, unit squae inteconnect esistance, capacitance c, wie width w, sink capacitance C k, gate length L g supply voltage V dd, and thei vaiabilities Output: Augmented Clock Distibution Netwok N 1. Link insetion between all pais of sinks within a distance ε 2. Statistical clock skew analysis 3. Rule based link emoval 4. Iteative link emoval 5. Link consolidation by Steine tee constuction 6. Final statistical skew yield evaluation We give a detailed desciption fo each pocedue in ou algoithm in the following subsections. A. Mesh Fomation Based on the analysis esults and the obsevations in the pevious section, e.g., a single inseted link may not guaantee global skew (vaiation) eduction, we popose to inset a sufficiently lage numbe of links at the same time in a clock distibution netwok fo guaanteed skew yield. We pefe to inset shotest links, because (1) limited outing esouce imposes wielength constaints, and (2) shotest links imply minimum capacitance balance update, which is lagely esponsible fo the complexity of the poblem. We inset links between all pais of sinks which ae within a distance of ε, and obtain a mesh-like clock netwok stuctue. We guaantee the equied clock skew yield while leaving enough oom fo mesh eduction optimization by tuning the distance theshold ε, e.g., a lage ε gives a lage wielength and a smalle clock skew. B. Mesh Reduction We pefom statistical clock skew analysis on the augmented clock netwok, e.g., by applying SPICE Monte Calo simulation, and educe wielength by selectively emoving pat of the inseted links. Fo efficiency, we establish the following two ules. Definition 1 A maximum delay sink is a sink which has the maximum delay in the clock netwok in at least one of Monte Calo SPICE simulation uns. Definition 2 The maximum skew between two sinks is the maximum delay diffeence in all of the Monte Calo SPICE simulation uns. Definition 3 A compaable delay sink pai ae two sinks of which maximum skew is smalle than a theshold α. Rule 1 Remove links between two maximum delay sinks. Rule 2 Remove links between a compaable delay sink pai. Removing a puely esistive link between two nodes with identical (compaable) delays have no (minimum) impact on the local and the global skew of the clock netwok. Removing a link between two maximum delay sinks educes the capacitances at the two sinks and helps to educe the global clock skew. We apply Rule 1 to emove all links between two maximum delay sinks, and apply Rule 2 to emove all links with thei maximum skew less than α, which is a pe-defined maximum skew theshold such that link emoval would not compomise the clock skew yield. We poceed to apply optional iteative link emoval, e.g., to gadually incease α o to emove links in an inceasing ode of the maximum skew between the sinks fo futhe wielength eduction without skew yield compomise (Algoithm 1). In iteative link emoval, we need to veify clock skew yield at each link emoval. The untime of this pocedue is dominated by statistical clock skew analysis. C. Link Consolidation The inseted links fom spanning tees. It is possible to futhe educe wielength by constucting Steine minimum tees (SMTs) in place of spanning tees. We cluste sinks which ae connected by links, and links which have ovelapped bounding boxes. Fo efficient computation of link bounding box ovelaps, we apply a line-scanning algoithm, which sots the link bounding boxes by thei x coodinates in an aay X, sweeps the layout plane in x diection, keep an aay Y of link bounding boxes which intesect with the scanline, sot the aay based on thei y coodinates, and identify ovelaps by going along the scanline in y diection and finding an aay A of active link bounding boxes. This line-scanning algoithm takes O(nlogn) time, whee n is the numbe of links. We constuct Steine minimum tees fo each cluste of sinks by applying the GeoSteine 3.1 package [13]. Algoithm 2 summaizes ou link consolidation method. Algoithm 2: Link Consolidation Algoithm Input: Spanning tees {T } of inseted links ove sinks S Output: Steine Minimum tees {T } ove sinks S 1. Fo each link (i, j) 2. Cluste i and j 3. Sot link endpoints by thei x coodinates in an aay X 4. Sweep scanline ove the layout plane, stop at each x sl X 5. If link (i, j) s left endpoint i has x coodinate x i = x sl 6. Inset link endpoints i and j into an aay Y 7. Update soting of aay Y by y coodinates 8. If link (i, j) s ight endpoint j has x coodinate x j = x sl 9. Remove link endpoints i and j fom aayy 10. Fo each endpoint i Y 11. If i is bottom endpoint of link (i, j) 12. Inset link endpoints i and j into aay of active links A 13. Link (i, j) s bbox ovelaps with those of active links in A 14. Cluste i and j with link endpoints in aay A 15. If i is top endpoint of link (i, j) 16. Remove link endpoints i and j fom aay A 17. Constuct Steine minimum tees {T } fo each cluste of sinks 29

6 TABLE I TESTCASE PROPERTIES. Case #Sinks Delay(ps) Skew(ps) WL (µm) Total cap(pf) s s s VI. EXPERIMENTS In the following expeiments, we apply ou poposed algoithm fo minimum augmented clock netwoks, and compae with the initial tee stuctue clock netwoks, and augmented clock netwoks achieved by the state-of-at link insetion method [11]. As in [11], we conduct ou expeiment on the ISCAS89 benchmak suite. A mapped netlist is synthesized with SIS [10] and the cicuit placement is obtained with an academic placement tool mpl [12]. Assuming a 180nm technology with paametes fom [1], wie capacitances ae extacted by SPACE 3D [14]. Table I gives the popeties of the balanced clock outing tees. We conside 5% standad deviations fo the vaiations of inteconnect width, sink capacitance, tansisto channel length, and supply voltage. We conside spatial coelations (3) which degade linealy as the distance between the two components inceases. Ou poposed method is implemented in C++ and uns on an Intel Xeon 2.4GHz system. Fo each statistical clock netwok analysis, we apply 1000 HSPICE Monte Calo simulation uns, and epot skew yield (SY), maximum skew (MS) and standad deviation (SD) of skew vaiations. We compae impovements fo each step of ou poposed algoithm, and compae ou poposed method with one of the best pevious methods [11]. We gadually incease theshold distance ε in mesh fomation and obtain the wielength and skew yield tadeoff cuve. Figue 1 pesents wielength inceases with diffeent skew yields fo testcase s The skew yield inceases apidly with the fist few shot links. Howeve, moe and longe links ae needed to impove skew yield when the skew yield is close to 100%. Figue 2 shows wielength inceases with diffeent skew bounds fo 100% skew yield fo testcase s The skew bound vaies fom 50ps to 110ps. Smalle clock skew bounds lead to inceased wielength of the clock distibution netwok, e.g, towads to a mesh stuctue. Figues 1 and 2 show two aspects of the same wielength incease tend. The 100% skew yield point in Figue 1 coesponds to the 100ps skew bound point in Figue 2. Table II pesents impovement and untime fo each step of ou poposed method. The wielength, maximum skew, standad deviation esults ae nomalized by those of the initial balanced tees. As in [11], the skew bounds of the thee testcases ae 50ps, 50ps and 100ps, espectively. We choose maximum skew theshold value α (in Rule 2) as 2% skew bound. Skew yield equiement is 100%. We obseve that link emoval significantly educes clock netwok wielength, e.g., by an aveage of 68% fo these test cases, with slightly inceased maximum skew and standad deviation and uncompomised skew yield. Link consolidation futhe educes an aveage of 25% wielength fo these testcases without inceasing maxi- Wielength Incease (%) Skew Yield (%) Fig. 1. Wielength inceases with diffeent skew yields with 100ps skew bound fo testcase s mum skew and standad deviation. The untime in Table II is dominated by statistical clock netwok analysis, e.g., in 100 HSPICE simulation uns. Table III compaes ou poposed method with one of the best existing method [11], e.g., with identical clock netwok wielength bound. We obseve that ou poposed algoithm achieves dominant esults than the existing method in tems of skew yield, maximum skew and standad deviation. E.g., ou method achieves an aveage of 16% clock skew yield impovement, 9% maximum skew eduction, and 25% eduction of clock skew vaiation standad deviation with identical wielength fo these test cases. VII. CONCLUSION In this pape, we fomulate the clock distibution netwok augmentation poblem as a statistical optimization poblem, i.e., to achieve guaanteed clock skew yield with minimum wielength incease. We pesent theoetical analysis on the effect of an inseted link, which scales down the local skew and skew vaiation between the two sinks by a atio of +γ,andthe dive admittance diffeence of the two sinks by the same atio. In geneal, an inseted link does not guaantee global skew and skew eduction in a clock distibution netwok. We popose a global minimum clock distibution netwok augmentation algoithm fo guaanteed clock skew yield, which augments a clock netwok by including all shotest links between sinks fo equied clock skew yield, and educes wielength by selective emoving of the inseted links based on statistical skew analysis on the augmented clock netwok. We finalize the clock netwok augmentation by constucting Steine minimum tees in place of the spanning tees which ae fomed by the inseted links. Ou expeimental esults show that ou poposed algoithm achieves dominant clock netwok solutions. Fo example, we achieve an aveage of 16% clock skew yield impovement, 9% maximum skew eduction, and 25% eduction of clock skew vaiation standad deviation with identical wielength com- 30

7 TABLE II SKEW YIELD (SY), WIRELENGTH(WL), MAXIMUM SKEW (MS) AND STANDARD DEVIATION OF SKEW VARIATION (SD) (NORMALIZED BY THOSE OF INTIAL CLOCK TREES) WITH 100% SKEW YIELD OF (1) INITIAL CLOCK TREES,(2)CLOCK MESHES,(3)REDUCED CLOCK MESHES, AND (4) CONSOLIDATED AND REDUCED CLOCK MESHES. Initial Tee Mesh Mesh + deletion Mesh + deletion + consolidation Testcases SY WL MS SD SY WL MS SD CPU(s) SY WL MS SD CPU(s) SY WL MS SD CPU(s) s s s Nomalized Avg TABLE III SKEW YIELD (SY), WIRELENGTH(WL) (NORMALIZED BY THAT OF INITIAL CLOCK TREES), MAXIMUM SKEW (MS) (ps) AND STANDARD DEVIATION OF SKEW VARIATION (SD) (ps) OF CLOCK NETWORKS ACHIEVED BY (1) LINK INSERTION METHOD IN [11], AND (2) OUR PROPOSED METHOD WITH IDENTICAL CLOCK NETWORK WIRELENGTH. [11] Ous Testcases SY WL MS(ps) SD(ps) SY WL MS(ps)SD(ps) s s s Nomalized Avg paed with one of the best pevious clock netwok link insetion methods [11]. Ou ongoing eseach effots include efficiency impovement via statistical delay calculation, and link insetion acoss buffes in a clock distibution netwok. Wielength Incease (%) Skew Bound (ps) Fig. 2. Wielength inceases with diffeent skew bounds with 100% skew yield fo testcase s REFERENCES [1] Y. Cao, T. Sato, D. Sylveste, M. Oshansky, and C. Hu, New paadigm of pedictive MOSFET and inteconnect modeling fo ealy cicuit simulation, Poc. IEEE Custom Integated Cicuits Confeence, pp , [2] W.-C. D. Lam, J. Jain, C.-K. Koh, V. Balakishnan, and Y. Chen, Statistical Based Link Insetion fo Robust Clock Netwok Design, in Poc. Intenational Confeence on Compute Aided Design, San Jose, CA, [3] P. Fiedbeg, Y. Cao, J. Cain, R. Wang, J. Rabaey, and C. Spanos, Modeling Within-Die Spatial Coelation Effects fo Pocess-Design Co-Optimization, in Poc. Intenational Symposium on Quality of Eletonic Design, pp , [4] G.H.GolubandC.F.VanLoan,Matix Computations, The John Hopkins Univesity Pess, Baltimoe, Mayland, [5] H. Levy, W. Scott, D. Macmillen, and J. White, A Rank-One Update Method fo Efficient Pocessing of Inteconnect Paasitics in Timing Analysis, in Poc. DAC, pp , [6] A. Odabasioglu, M. Celik and L. T. Pileggi, PRIMA: Passive Reduced-Ode Inteconnect Macomodeling Algoithm, IEEE Tans. on Compute-Aided Design of Integated Cicuits and Systems, 17(8), 1998, pp [7] M. J. M. Pelgom, A. C. J. Diunmije, and A. P. G. Welbes, Matching Popeties of MOS Tansisto, IEEE Jounal of Solid-State Cicuits, Vol SC-24, pp , [8] A. Rajaam, J. Hu and R. Mahapata, Reducing Skew Vaiablity via Coss Links, Design Automation Confeence, [9] A. Rajaam, D. Z. Pan and J. Hu, Impoved Algoithms fo Link Based Nontee Clock Netwoks fo Skew Vaiability Reduction, in Poc. Intenational Symposium of Physical Design, [10] E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Mugai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Bayton, and A. L. Sangiovanni-Vincentelli, SIS: a system fo sequential cicuit synthesis, Memoandum no. M92/41, ERL, Univesity of Califonia, Bekeley, [11] G. Venkataaman, N. Jayakuma, J. Hu, P. Li, S. Khati, A. Rajaam, P. McGuinness and C. Alpet, Pactical Techniques to Reduce Skew and Its Vaiations in Buffeed Clock Netwoks, Intl. Confeence on Compute-Aided Design,, pp , [12] CPMO-constained placement by multilevel optimization. [13] GeoSteine: Softwae fo Computing Steine Tees. [14] SPACE: VLSI physical design modeling and veification. 31