Floorplanning. ECE6133 Physical Design Automation of VLSI Systems

Transcription

1 Floorplanning ECE6133 Physical Design Automation of VLSI Systems Prof. Sung Kyu Lim School of Electrical and Computer Engineering Georgia Institute of Technology

2 Floorplanning, Placement, and Pin Assignment Partitioning leads to Blocks with well-defined areas and shapes (fixed blocks). Blocks with approximated areas and no particular shapes (flexible blocks). A netlist specifying connections between the blocks. Objectives Find locations for all blocks. Consider shapes of flexible block, pin locations of all the blocks. Blocks w/ areas (shapes) netlist Block locations netlist Partitioning Floorplanning/Placement (/Pin assignment) Routing

3 Floorplanning Inputs to the floorplanning problem: A set of blocks, fixed or flexible. Pin locations of fixed blocks. A netlist. Objectives: Minimize area, reduce wirelength for (critical) nets, maximize routability, determine shapes of flexible blocks An optimal floorplan, in terms of area A non optimal floorplan

4 Floorplan Design Modules: x y g e d Area: A=xy Aspect ratio: r <= y/x <= s f a b c Rotation: Module connectivity a 2 b c e f d

5 Floorplanning: Terminology Rectangular dissection: Subdivision of a given rectangle by a finite # of horizontal and vertical line segments into a finite # of non-overlapping rectangles. Slicing structure: a rectangular dissection that can be obtained by repetitively subdividing rectangles horizontally or vertically. Slicing tree: A binary tree, where each internal node represents a vertical cut line or horizontal cut line, and each leaf a basic rectangle. Skewed slicing tree: One in which no node and its right child are the same Non slicing floorplan Slicing floorplan H V H 2 1 H 3 V V A slicing tree (skewed) 2 H 1 V V 6 7 H V H Another slicing tree (non skewed)

6 Floorplan Design by Simulated Annealing Related work Wong & Liu, A new algorithm for floorplan design, DAC 86. Consider slicing floorplans. Wong & Liu, Floorplan design for rectangular and L-shaped modules, ICCAD 87. Also consider L-shaped modules. Wong, Leong, Liu, Simulated Annealing for VLSI Design, pp , Kluwer academic Publishers, Ingredients: solution space, neighborhood structure, cost function, annealing schedule?

7 the increase in a parameter called temperature T Partitioning Simulated Annealing Algorithm Concept analogous to the annealing process used for metals and glass. A random initial partition is available as input. A new partitioning is generated by ~ exchanging some elements. If the partitions improve the move is always accepted. If not then the move is accepted with a probability which decreases with 4.21 j Algorithms for VLSI Physical Design Automation csherwani 92

8 Partitioning The Annealing curve Temp Local Minima s Global Minima Time 4.22 j Algorithms for VLSI Physical Design Automation csherwani 92

9 SA Algorithm begin = t 0 t part = ini part cur score = SCORE(cur part) cur repeat repeat = SELECT(part1) comp1 = SELECT(part2) comp2 part =EXCHANGE(comp1 comp2 cur part) trial score =SCORE(trial part) trial = trial score ; cur score s (s < 0) then if score = trial score cur part =MOVE(comp1 comp2) cur else score = trial score cur part =MOVE(comp1 comp2 ) cur (equilibrium at t is reached) until = t (* 0 <<1*) t (freezing point isreached) until end. Partitioning Simulated Annealing Algorithm ~ = 1) r s RANDOM(0 <e ; t ) then (r if 4.23 j Algorithms for VLSI Physical Design Automation csherwani 92

10 Solution Representation An expression E = e 1 e 2... e 2n 1, where e i {1, 2,..., n, H, V }, 1 i 2n 1, is a Polish expression of length 2n 1 iff 1. every operand j, 1 j n, appears exactly once in E; 2. (the balloting property) for every subexpression E i = e 1... e i, 1 i 2n 1, #operands > #operators. 1 6 H 3 5 V 2 H V 7 4 H V # of operands = 4... = 7 # of operators = 2... = 5 Polish expression Postorder traversal. ijh: rectangle i on bottom of j; ijv : rectangle i on the left of j V H V H E = 16H2V75VH34HV V H 3 4 E = 16+2*75*+34+* Postorder traversal of a tree!

11 Solution Representation (cont d) V V H E = 123H4VV non skewed! 1 V V 4 H 2 3 E = 123HV4V skewed! H V Non skewed cases H V... HH VV... Question: How to eliminate ambiguous representation?

12 Normalized Polish Expression A Polish expression E = e 1 e 2... e 2n 1 is called normalized iff E has no consecutive operators of the same type (H or V ). Given a normalized Polish expression, we can construct a unique rectangular slicing structure V H V H V H 3 4 E = 16H2V75VH34HV A normalized Polish expression

13 Neighborhood Structure Chain: HV HV H... or V HV HV H 3 5 V 2 H V 7 4 H V chain Adjacent: 1 and 6 are adjacent operands; 2 and 7 are adjacent operands; 5 and V are adjacent operand and operator. 3 types of moves: M 1 (Operand Swap): Swap two adjacent operands. M2 (Chain Invert): Complement some chain (V = H, H = V ). M 3 (Operator/Operand Swap): Swap two adjacent operand and operator.

14 Effects of Perturbation M1 M2 M3 12V4H3V 12V3H4V 12H3H4V 12H34HV Question: The balloting property holds during the moves? M1 and M2 moves are OK. Check the M3 moves! Reject illegal M3 moves. Check M3 moves: Assume that the M 3 move swaps the operand e i with the operator e i+1, 1 i k 1. Then, the swap will not violate the balloting property iff 2N i+1 < i. N k : # of operators in the Polish expression E = e 1 e 2... e k, 1 k 2n

15 Φ = A + λw. Cost Function A: area of the smallest rectangle W : overall wiring length λ: user-specified parameter M1 M2 M A: 12H34HV W = ij c ijd ij. c ij : # of connections between blocks i and j. d ij : center-to-center distance between basic rectangles i and j.

16 Area Computation { (5,5) (9,4) } V { (2,5) (3,4) } { (3,5) (6,,4) } H H { (6,2) (3,3) } V V { (3,2) } 1 2 { (2,3) (3,2) } { (2,2) } { (1,2) (2,1) } { (2,2) } { (1,3) (3,1) } { (2,3) (3,2) } u1 u1 v v u2 w u2 w v+w u2 u1 max{v, w} max{u1, u2} u1+u2 H 1 2 V V 3 4 H V 5 6 Wiring cost?

17 Incremental Computation of Cost Function Each move leads to only a minor modification of the Polish expression. At most two paths of the slicing tree need to be updated for each move. V V H V 4 H V 5 6 M1 H V 5 H 4 V 6 E = 12H34V56VHV E = 12H35V46VHV

18 Incremental Computation of Cost Function (cont d) V H H 1 2 V 3 4 H V 5 6 M2 H V 4 V 5 H 6 E = 12H34V56VHV E = 12H34V56HVH V V H 1 2 V 3 4 H V 5 6 M3 1 H V 4 H 5 V 6 E = 12H34V56VHV 2 3 E = 123H4V56VHV

19 Annealing Schedule Initial solution: 12V 3V... nv n T i = r i T 0, i = 1, 2, 3,...; r = At each temperature, try kn moves (k = 5 10). Terminate the annealing process if # of accepted moves < 5%, temperature is low enough, or run out of time.

20 Algorithm: Simulated Annealing Floorplanning(P, ɛ, r, k) 1 begin 2 E 12V 3V 4V... nv ; /* initial solution */ 3 Best E; T 0 avg ; M MT uphill 0; N = kn; ln(p ) 4 repeat 5 MT uphill reject 0; 6 repeat 7 SelectMove(M); 8 Case M of 9 M 1 : Select two adjacent operands e i and e j ; NE Swap(E, e i, e j ); 10 M 2 : Select a nonzero length chain C; NE Complement(E, C); 11 M 3 : done F ALSE; 12 while not (done) do 13 Select two adjacent operand e i and operator e i+1 ; 14 if (e i 1 e i+1 ) and (2N i+1 < i) then done T RUE; 15 NE Swap(E, e i, e i+1 ); 16 MT MT + 1; cost cost(ne) cost(e); 17 if ( cost 0) or (Random < e cost T ) 18 then 19 if ( cost > 0) then uphill uphill + 1; 20 E NE; 21 if cost(e) < cost(best) then best E; 22 else reject reject + 1; 23 until (uphill > N) or (MT > 2N); 24 T = rt ; /* reduce temperature */ 25 until ( reject > 0.95) or (T < ɛ) or OutOfT ime; MT 26 end

21 Normalized Polish Expression Draw slicing floorplan based on: Initial PE: P 1 = 25V1H374VH6V8VH Dimensions: (2,4), (1,3), (3,3), (3,5), (3,2), (5,3), (1,2), (2,4) Practical Problems in VLSI Physical Design Polish Expression (1/8)

22 M1 Move Swap module 3 and 7 in P 1 = 25V1H374VH6V8VH We get: P 2 = 25V1H734VH6V8VH Area changed from to Practical Problems in VLSI Physical Design Polish Expression (2/8)

23 Change on Floorplan Practical Problems in VLSI Physical Design Polish Expression (3/8)

24 M2 Move Complement last chain in P 2 = 25V1H734VH6V8VH We get: P 3 = 25V1H734VH6V8HV Area changed from to Practical Problems in VLSI Physical Design Polish Expression (4/8)

25 Change on Floorplan Practical Problems in VLSI Physical Design Polish Expression (5/8)

26 M3 Move Swaps 6 and V in P 3 = 25V1H734VH6V8HV We get: P 4 = 25V1H734VHV68HV Area changed from to 15 7 Practical Problems in VLSI Physical Design Polish Expression (6/8)

27 Change on Floorplan Practical Problems in VLSI Physical Design Polish Expression (7/8)

28 Initial Temperature Calculation What is average change on cost function? Initial temperature with acceptance probability 0.9? Practical Problems in VLSI Physical Design Polish Expression (8/8)

29 Sample LP Problem A calculator company produces a scientific calculator and a graphing calculator. Long-term projections indicate an expected demand of at least 100 scientific and 80 graphing calculators each day. Because of limitations on production capacity, no more than 200 scientific and 170 graphing calculators can be made daily. To satisfy a shipping contract, a total of at least 200 calculators must be shipped each day. If each scientific calculator sold results in a $2 loss, but each graphing calculator produces a $5 profit, how many of each type should be made daily to maximize net profits?

30 LP Formulation Variables x: number of scientific calculators produced y: number of graphing calculators produced Objective function P = 2x + 5y Constraints 100 < x < < y < 170 y > x Answer P = 650 at (x, y) = (100, 170)

31 Linear program (LP) minimize subject to n c j x j j=1 n a ij x j b i, j=1 n c ij x j = d i, j=1 i = 1,..., m i = 1,..., p variables: x j ; problem data: c j, a ij, b i, c ij, d i properties can be solved very efficiently (several 10,000 variables, constraints) widely available general-purpose software extensive, useful theory, e.g., can characterize sensitivity of optimum with respect to changes in data Introduction and overview 1 2

32 integer linear program Integer linear program minimize subject to n j=1 c jx j n j=1 a ijx j b i, i = 1,..., m n j=1 c ijx j = d i, i = 1,..., p x j Z Boolean linear program minimize subject to n j=1 c jx j n j=1 a ijx j b i, i = 1,..., m n j=1 c ijx j = d i, i = 1,..., p x j {0, 1} very general problems; can be extremely hard to solve can be solved as a sequence of linear programs Introduction and overview 1 8

33 Floorplanning by Mathematical Programming Sutanthavibul, Shragowitz, and Rosen, An analytical approach to floorplan design and optimization, 27th DAC, Notation: w i, h i : width and height of module M i. (x i, y i ): coordinate of the lower left corner of module M i. a i w i /h i b i : aspect ratio w i /h i of module M i. (Note: We defined aspect ratio as h i /w i before.) Goal: Find a mixed integer linear programming (ILP) formulation for the floorplan design. Linear constraints? Objective function?

34 Nonoverlap Constraints Two modules M i and M j are nonoverlap, if at least one of the following linear constraints is satisfied (cases encoded by p ij and q ij ): M i to the left of M j : x i + w i x j 0 0 M i below M j : y i + h i y j 0 1 M i to the right of M j : x i w j x j 1 0 M i above M j : y i h j y j 1 1 Let W, H be upper bounds on the floorplan width and height, respectively. Introduce two 0, 1 variables p ij and q ij to denote that one of the above inequalities is enforced; e.g., p ij = 0, q ij = 1 y i + h i y j is satisfied. hi wi (xi, yi) (xj, yj) xi + wi <= xj x i + w i x j + W (p ij + q ij ) y i + h i y j + H(1 + p ij q ij ) x i w j x j W (1 p ij + q ij ) y i h j y j H(2 p ij q ij ) wj hj wi p ij (xi, yi) (xj, yj) xi + wi > xj q ij

35 Cost Function & Constraints Minimize Area = xy, nonlinear! (x, y: width and height of the resulting floorplan) How to fix? Fix the width W and minimize the height y! Four types of constraints: 1. no two modules overlap ( i, j : 1 i < j n); 2. each module is enclosed within a rectangle of width W and height H (x i + w i W, y i + h i H, 1 i n); 3. x i 0, y i 0, 1 i n; 4. p ij, q ij {0, 1}. w i, h i are known.

36 Mixed ILP for Floorplanning Mixed ILP for the floorplanning problem with rigid, fixed modules. min y subject to x i + w i W, 1 i n (1) y i + h i y, 1 i n (2) x i + w i x j + W (p ij + q ij ), 1 i < j n (3) y i + h i y j + H(1 + p ij q ij ), 1 i < j n (4) x i w j x j W (1 p ij + q ij ), 1 i < j n (5) y i h j y j H(2 p ij q ij ), 1 i < j n (6) x i, y i 0, 1 i n (7) p ij, q ij {0, 1}, 1 i < j n (8) Size of the mixed ILP: for n modules, # continuous variables: O(n); # integer variables: O(n 2 ); # linear constraints: O(n 2 ). Unacceptably huge program for a large n! (How to cope with it?) Popular LP software: LINDO, lp solve, etc.

37 Mixed ILP for Floorplanning (cont d) Mixed ILP for the floorplanning problem: rigid, freely oriented modules. min y subject to x i + r i h i + (1 r i )w i W, 1 i n (9) y i + r i w i + (1 r i )h i y, 1 i n (10) x i + r i h i + (1 r i )w i x j + M(p ij + q ij ), 1 i < j n (11) y i + r i w i (1 r i )h i y j + M(1 + p ij q ij ), 1 i < j n (12) x i r j h j + (1 r j )w j x j M(1 p ij + q ij ), 1 i < j n (13) y i r j w j (1 r j )h j y j M(2 p ij q ij ), 1 i < j n (14) x i, y i 0, 1 i n (15) p ij, q ij {0, 1}, 1 i < j n (16) For each module i with free orientation, associate a 0-1 variable r i : r i = 0: 0 rotation for module i. r i = 1: 90 rotation for module i. M = max{w, H}.

38 Flexible Modules Assumptions: w i, h i are unknown; area lower bound: A i. Module size constraints: w i h i A i ; a i w i h i b i. Hence, w min = A i a i, w max = A i b i, h min = w i h i A i nonlinear! How to fix? A i b i, h max = A i a i. Can apply a first-order approximation of the equation: a line passing through (w min, h max ) and (w max, h min ). h i = i w i + c i / y = mx + c / i = h max h min w min w max / slope / c i = h max i w min / c = y 0 mx 0 / Substitute i w i +c i for h i toform linear constraints (x i,y i,w i are unknown; i, c i,can be computed as above).

39 Wirelength Constraint Critical nets Timing analysis, power analysis, etc 6 new continuous variables per net Half perimeter of bounding box of each net is bounded Overhead is not significant: time dependence on # of continuous variable is at most linear n n n n n n n n n i n i n i n i n L y x y y y x x x n i y y n i y y n i x x n i x x + = = = =, ˆ, ˆ min ˆ, max min ˆ, max

40 Reducing the Size of the Mixed ILP Time complexity of a mixed ILP: exponential! Recall the large size of the mixed ILP: # variables, # constraints: O(n 2 ). How to fix it? Key: Solve a partial problem at each step (successive augmentation) Questions: How to select next subgroup of modules? linear ordering based on connectivity. How to minimize the # of required variables?

41 Next group of modules Partial floorplan W

42 Reducing the Size of the Mixed ILP (cont d) Size of each successive mixed ILP depends on (1) # of modules in the next group; (2) size of the partially constructed floorplan. Keys to deal with (2) Minimize the problem size of the partial floorplan. Replace the already placed modules by a set of covering rectangles. # rectangles is usually much smaller than # placed modules. Dead space (a) (b) C3 C4 R4 R5 C2 R3 Horizontal cut edges C1 R2 R1 (c) (d)

43 I. Floorplanning with Fixed Modules Fixed modules only, no rotation allowed m 1 (4,5), m 2 (3,7), m 3 (6,4), m 4 (7,7) Practical Problems in VLSI Physical Design ILP Floorplanning (1/22)

44 ILP Formulation Practical Problems in VLSI Physical Design ILP Floorplanning (2/22)

45 Non-Overlapping Constraints (cont) Practical Problems in VLSI Physical Design ILP Floorplanning (3/22)

46 Additional Constraints Practical Problems in VLSI Physical Design ILP Floorplanning (4/22)

47 Solutions Using GLPK we get the following solutions: Practical Problems in VLSI Physical Design ILP Floorplanning (5/22)

48 Final Floorplan Why the non-optimality? Due to linear approximation of area objective (= y*) Chip width/height constraints also affected In fact, our ILP solution (y* = 12) is optimal under these conditions. Practical Problems in VLSI Physical Design ILP Floorplanning (6/22)

49 II. Floorplanning with Rotation Fixed modules, rotation allowed Fixed modules: m 1 (4,5), m 2 (3,7), m 3 (6,4), m 4 (7,7) Need 4 more binary variables for rotation: z 1, z 2, z 3, z 4 We use M = max{w,h} = 23 Practical Problems in VLSI Physical Design ILP Floorplanning (7/22)

50 ILP Formulation Practical Problems in VLSI Physical Design ILP Floorplanning (8/22)

51 Non-Overlapping Constraints (cont) Practical Problems in VLSI Physical Design ILP Floorplanning (9/22)

52 Non-Overlapping Constraints (cont) Practical Problems in VLSI Physical Design ILP Floorplanning (10/22)

53 Additional Constraints Practical Problems in VLSI Physical Design ILP Floorplanning (11/22)

54 Solutions Using GLPK we get the following solutions: Practical Problems in VLSI Physical Design ILP Floorplanning (12/22)

55 III. Floorplanning with Flexible Modules 2 Fixed modules: m 1 (4,5), m 2 (3,7) (rotation allowed) 2 Flexible modules: m 3 : area = 24, aspect ratio [0.5, 2] m 4 : area = 49, aspect ratio [0.3, 2.5] Practical Problems in VLSI Physical Design ILP Floorplanning (13/22)

56 Linear Approximation Practical Problems in VLSI Physical Design ILP Floorplanning (14/22)

57 Linear Approximation (cont) Practical Problems in VLSI Physical Design ILP Floorplanning (15/22)

58 Upper Bound of Chip Dimension Practical Problems in VLSI Physical Design ILP Floorplanning (16/22)

59 Non-Overlap Constraint Practical Problems in VLSI Physical Design ILP Floorplanning (17/22)

60 Non-Overlap Constraint (cont) Practical Problems in VLSI Physical Design ILP Floorplanning (18/22)

61 More Constraints Practical Problems in VLSI Physical Design ILP Floorplanning (19/22)

62 Solutions Practical Problems in VLSI Physical Design ILP Floorplanning (20/22)

63 Comparison Fixed modules only = Rotation allowed = Flexible modules used = Practical Problems in VLSI Physical Design ILP Floorplanning (21/22)

64 Approximation Error and Overlap Due to linear approximation Approximated area of m 3 = = (actually 24) Approximated area of m 4 = = (actually 49) Real area of m 3 = = 24 Real area of m 4 = = 49 Floorplan area increases, overlap occurs Practical Problems in VLSI Physical Design ILP Floorplanning (22/22)

65 P-admissible Solution Space P-admissible solution space for Problem P: 1. the solution space is finite, 2. every solution is feasible, 3. evaluation for each configuration is possible in polynomial time and so is the implementation of the corresponding configuration, and 4. the configuration corresponding to the best evaluated solution in the space coincides with an optimal solution of P. Slicing floorplan is not P-admissible. Why? A P-admissible floorplan representation: Sequence Pair.

66 Sequence-Pair Based Floorplanning/Placement Murata, et al, ICCAD-95; Nakatake, et al, ICCAD-96; Murata, et al, ISPD-97; Murata and Kuh, ISPD-98; Xu, et al, ISPD-98; Kang and Dai, ISPD-98, ICCAD-98. Represent a packing by a pair of module-name sequences (e.g., (abdecf, cbf ade)). Correspond all pairs of the sequences to a P-admissible solution space. Search in the P-admissible solution space (typically, by simulated annealing). a d e a d e a d e b b b c f c f c f A floorplan Loci of module b

67 Relative Module Positions A floorplan is a partition of a chip into rooms, each containing at most one block. Locus (right-up, left-down, up-left, down-right) 1. Take a non-empty room. 2. Start at the center of the room, walk in two alternating directions to hit the sides of rooms. 3. Continue until to reach a corner of the chip. Positive locus: Union of right-up locus and left-down locus. Negative locus: Union of up-left locus and down-right locus. a d e a d e a d e b b b c f c f c f Loci of module b Positive loci: abdecf Negative loci: cbfade

68 Geometrical Information No pair of positive (negative) loci cross each other, i.e., loci are linearly ordered. Sequence Pair (Γ +, Γ ): Γ + is a module-name sequence representing the order of positive loci. (Exp: (Γ +, Γ ) = (abdecf, cbfade)) x is after (before) x in both Γ + and Γ = x is right (left) to x. x is after (before) x in Γ + and before (after) x in Γ = x is below (above) x. a d e a d e a d e b b b c f c f c f Loci of module b Positive loci: abdecf Negative loci: cbfade

69 (Γ +, Γ )-Packing For every sequence pair (Γ +, Γ ), there is a (Γ +, Γ ) packing. Horizontal constraint graph G H (V, E) (similarly for G V (V, E)): V : source s, sink t, m vertices for modules. E: (s, x) and (x, t) for each module x, and (x, x ) iff x must be left-to x. Vertex weight: 0 for s and t, width of module x for the other vertices. t b a d e s b a d e t b a d e c f c f c f Packing for sequence pair: (abdecf, cbfade) Horizontal constraint graph (Transitive edges are not shown) s Vertical constraint graph (Transitive edges are not shown)

70 Optimal (Γ +, Γ )-Packing Optimal (Γ +, Γ )-Packing can be obtained in O(m 2 ) time by applying a longest path algorithm on a vertex-weighted directed acyclic graph. G H and G V are independent. The X and Y coordinates of each module are determined as the minimum by assigning the longest path length between s and the vertex of the module in G H and G V, respectively. The set of all sequence pairs is a P-admissible solution space. t b a d e s b a d e t b a d e c f c f c f Packing for sequence pair: (abdecf, cbfade) Horizontal constraint graph (Transitive edges are not shown) s Vertical constraint graph (Transitive edges are not shown)

71 Sequence Pair Final chip area? Solution space size? Without rotation vs with rotation Optimization: Simulated Annealing Initial solution: Γ + = Γ - Swap two modules in Γ + Swap two modules both in Γ + and Γ - Rotate Results: produces highly packed non-slicing floorplans

72 Annealing Temperature vs. Floorplan Quality m8 m11 m7 m0 m10 m4 m1 m m2 m12 m9 m5 m13 m m6 m5 m8 m13 m9 m m3 m1 m m3 m6 m1 m11 m9 m4 m m8 m (a) temperature: 2000 area: % (b) temperature: 1000 area: (c) temperature: 20 area: %

73 Sequence Pair Floorplan (a) S1: S2: Floorplan (b) S1: S2: Floorplan (c) S1: S2:

74 Non Slicing Floorplan Sequence Pair + SA by Adam & Todd (class project)

75 Sequence Pair Representation Initial SP: SP 1 = ( , ) Dimensions: (2,4), (1,3), (3,3), (3,5), (3,2), (5,3), (1,2), (2,4) Based on SP 1 we build the following table: Practical Problems in VLSI Physical Design Sequence Pair Method (1/13)

76 Constraint Graphs Horizontal constraint graph (HCG) Before and after removing transitive edges Practical Problems in VLSI Physical Design Sequence Pair Method (2/13)

77 Constraint Graphs (cont) Vertical constraint graph (VCG) Practical Problems in VLSI Physical Design Sequence Pair Method (3/13)

78 Computing Chip Width and Height Longest source-sink path length in: HCG = chip width, VCG = chip height Node weight = module width/height Practical Problems in VLSI Physical Design Sequence Pair Method (4/13)

79 Computing Module Location Use longest source-module path length in HCG/VCG Lower-left corner location = source to module input path length Practical Problems in VLSI Physical Design Sequence Pair Method (5/13)

80 Final Floorplan Dimension: Practical Problems in VLSI Physical Design Sequence Pair Method (6/13)

81 Move I Swap 1 and 3 in positive sequence of SP 1 SP 1 = ( , ) SP 2 = ( , ) Practical Problems in VLSI Physical Design Sequence Pair Method (7/13)

82 Constraint Graphs Practical Problems in VLSI Physical Design Sequence Pair Method (8/13)

83 Constructing Floorplan Dimension: Practical Problems in VLSI Physical Design Sequence Pair Method (9/13)

84 Move II Swap 4 and 6 in both sequences of SP 2 SP 2 = ( , ) SP 3 = ( , ) Practical Problems in VLSI Physical Design Sequence Pair Method (10/13)

85 Constraint Graphs Practical Problems in VLSI Physical Design Sequence Pair Method (11/13)

86 Constructing Floorplan Dimension: Practical Problems in VLSI Physical Design Sequence Pair Method (12/13)

87 Summary Impact of the moves: Floorplan dimension changes from to to Practical Problems in VLSI Physical Design Sequence Pair Method (13/13)