Cyclic Boolean Circuits

Transcription

1 Cyclic Boolean Circuits Marc D. Riedel Electrical and Computer Engineering, University o Minnesota, Minneapolis, MN Jehoshua Bruck Electrical Engineering, Caliornia Institute o Technology, Pasadena, CA 925 Abstract A Boolean circuit is a collection o gates and wires that perorms a mapping rom Boolean inputs to Boolean outputs. The accepted wisdom is that such circuits must have acyclic (i.e., loop-ree or eed-orward) topologies. In act, the model is oten deined this way as a directed acyclic graph (DAG). And yet simple examples suggest that this is incorrect. We advocate that Boolean circuits should have cyclic topologies (i.e., loops or eedback paths). In other work, we demonstrated the practical implications o this view: digital circuits can be designed with ewer gates i they contain cycles. In this paper, we explore the theoretical underpinnings o the idea. We show that the complexity o implementing Boolean unctions can be lower with cyclic topologies than with acyclic topologies. With examples, we show that certain Boolean unctions can be implemented by cyclic circuits with as little as one-hal the number gates that are required by equivalent acyclic circuits. Keywords: Boolean circuits, Boolean unctions, combinational circuits, cyclic circuits, DAG, cycles, loops, eedback This work is partially supported by an NSF CAREER Award (grant CCF ), by the NSF Expeditions in Computing Program (grant CCF ), by a grant rom the MARCO Focus Center Research Program on Functional Engineered Nano-Architectonics (FENA), and by the Caltech Lee Center or Advanced Networking. addresses: mriedel@umn.edu (Marc D. Riedel), bruck@paradise.caltech.edu (Jehoshua Bruck) Preprint submitted to Discrete Mathematics December 3, 2009

2 . Introduction This paper presents circuit constructs that are counter-intuitive and run against the accepted practice. Accordingly, throughout the paper, we adopt a discursive tone and elucidate the ideas with many examples... Boolean Circuit Model The Boolean circuit model is a undamental one in complexity theory. It is also the core model underpinning practical digital circuit design. In general terms, a Boolean circuit consists o gates and wires. Each gate corresponds to a Boolean unction that perorms a mapping rom several input bits to an output bit. The gates are connected by wires, with the outputs o some being the inputs o others. Accordingly, the topology o the circuit may be described as a directed graph G = (V, E), with the nodes V representing logic gates and the edges E representing wires. Central to the deinition o the Boolean circuit model is the idea that such circuits perorm mappings rom designated inputs to designated outputs. So each output o a Boolean circuit computes a speciic Boolean unction: : {0, } n {0, }. () O course, a collection o gates and wires can produce outputs that are not Boolean unctions. Such circuits can exhibit memory. We will use the term Boolean circuit to reer to a circuit that produces outputs that depend only on the current inputs; digital circuit designers call these combinational circuits. We will use the term not a Boolean circuit to reer to a circuit that produces outputs that depend not only on the current inputs, but also on the previous inputs; digital circuit designers call these sequential circuits. The common way to categorize circuits is that Boolean circuits have acyclic topologies, while circuits with cyclic topologies have non-boolean behavior. This conorms to intuition. In an acyclic circuit, such as that shown in Figure, the input values propagate orward and determine the values o the outputs. The outcome can be asserted regardless o the prior values on the wires and so independently o the past sequence o inputs. The circuit is clearly Boolean (it implements the exclusive-or o x and y.) 2

3 In a cyclic circuit, such as that shown in Figure 2, the behavior is more intricate. A common approach is to characterize the output values and the next state in terms o the input values and the current state. The current state, in turn, depends on the prior sequence o inputs (starting rom some known initial state). The circuit in Figure 2 is not a Boolean circuit: given input values s = 0 and r = 0, we cannot determine the output without knowing the value o z 3 or z 4. (In act, the circuit implements a one-bit memory element, called a latch.) Figure : An acyclic circuit Figure 2: A cyclic circuit. Clearly: An acyclic topology is suicient or a circuit to be Boolean. Conversely, a cyclic topology is necessary or a circuit not to be Boolean. But we ask: Is an acyclic topology necessary or a circuit to be Boolean? The accepted wisdom is that, yes, Boolean circuits must have acyclic topologies. In act, Boolean circuits are oten deined as directed acyclic graphs (DAGs): e.g., (Papadimitriou, 995, p. 80) and (Vollmer, 999, p. 8). Circuit practitioners design combinational circuits without cycles: e.g., (Katz, 992, p. 4) and (Wakerly, 2000, p. 93). Design automation tools enorce this constraint (Sentovich et al., 992). 3

4 .2. Cyclic Boolean Circuits The accepted wisdom and theoretical practice are wrong: a circuit with a cyclic topology can be Boolean. A trivial circuit, shown in Figure 3, demonstrates this. It consists o an AND gate and an OR gate connected in a cycle, both with input x. Recall that the output o an AND gate is 0 i either input is 0; the output o an OR gate is i either input is. Consider the two possible values o x. On the one hand, i x = 0, the output o the AND gate is ixed at 0, and so the input rom the OR gate has no inluence, as shown in Figure 4 (a). On the other hand, i x =, the output o the OR gate is ixed at, and so the input rom the AND gate has no inluence, as shown in Figure 4 (b). Although useless, this circuit qualiies as Boolean: the value o the output is completely determined by the current input value x (actually = x). Figure 3: A (useless) cyclic Boolean circuit. 0 0 AND 0 OR 0 AND OR (a) (b) Figure 4: The circuit o Figure 3 with (a) x = 0 and (b) x =. One might argue that, while Boolean circuits can be cyclic, such examples are contrived or inconsequential. A convincing example suggesting otherwise is shown in 4

5 Figure 5. It consists o six alternating AND and OR gates, with inputs x, x 2 and x 3 repeated. x x2 x3 x x2 x3 g g 2 g 3 g 4 g 5 g Figure 5: A cyclic Boolean circuit due to Rivest (Rivest, 977). To show that the circuit is Boolean, we label the eedback path with an unknown value y, as shown in Figure 6. Applying standard Boolean identities, such as distribution and absorption, we obtain: = x y 2 = x 2 + = x 2 + x y 3 = x 3 2 = x 3 (x 2 + x y) 4 = x + 3 = x + x 3 (x 2 + x y) = x + x 2 x 3 5 = x 2 4 = x 2 (x + x 2 x 3 ) = x 2 (x + x 3 ) 6 = x = x 3 + x 2 (x + x 3 ) = x 3 + x x 2. We see that 4, 5 and 6 do not depend upon the unknown value. Thus, we compute = x 6 = x (x 3 + x x 2 ) = x (x 2 + x 3 ) 2 = x 2 + = x 2 + x (x 2 + x 3 ) = x 2 + x x 3 3 = x 3 2 = x 3 (x 2 + x x 3 ) = x 3 (x + x 2 ). Each output depends on the current input values, not on the prior values, and so the circuit is Boolean. Unlike the circuit in Figure 3, the one in Figure 5 computes something useul. The six output unctions are distinct, and each depends on all three input We use the standard arithmetical convention that addition represents disjunction (OR) and multiplication represents conjunction (AND). Also, when writing arithmetical expressions, we assume that multiplication has precedence over addition, so x + yz represents x + (yz). 5

6 x x2 x3 x x2 x3 y g g 2 g 3 g 4 g 5 g Figure 6: Analyzing the circuit o Figure 5. variables. Moreover, we can show that this cyclic circuit has ewer gates than any equivalent acyclic circuit. To see this, note that any acyclic coniguration contains at least one gate producing an output unction that does not depend on the output o any other gate producing an output unction. (I this were not the case, then every output gate would depend upon another and so the circuit would be cyclic.) x 2 x 3 OR x AND x x + ) ( 2 x3 Figure 7: With an-in two gates, two gates are needed to compute x (x 2 + x 3 ). With an-in two gates, it takes two gates to compute any one o the six unctions by itsel. This is illustrated in Figure 7. We conclude that an acyclic implementation o the six unctions requires seven gates, compared to the six in the cyclic circuit. The circuit in Figure 5 was presented by Rivest in 977, in a paper less than a page long (Rivest, 977). His work on the topic, as well as that o a ew others in the 960s, seems to have gone largely unnoticed by theoreticians and practitioners alike. And yet his example hints at a undamental misconception in the ield, namely that Boolean circuit and acyclic are synonymous terms. In this paper, we demonstrate not only that it is easible to design Boolean circuits with cyclic topologies, but it is generally advantageous to do so. 6

7 Given an upper bound on the time that it takes each gate to compute a value, the delay o a circuit is an upper bound on the time that it takes or the circuit to compute the values o the output unctions. The delay is generally determined by the length o the longest path rom an input to an output, called the critical path. In any circuit cyclic or acyclic there may exist alse paths, that is to say, topological paths that are never sensitized. I the longest path is alse, it does not impinge upon the delay. The critical path o the circuit then is the longest true path. For a cyclic circuit, we can say that it is Boolean i all cycles are alse; the sensitized paths in the circuit never bite their own tail to orm true cycles. The delay o a cyclic circuit is not necessarily greater that than that o an acyclic circuit. It is simply the length o the longest true path..3. Prior and Related Work In 963, McCaw presented a thesis or his Engineer s Degree at Stanord titled Loops in Directed Combinational Switching Networks (McCaw, 963). He demonstrated the cyclic circuit shown in Figure 8 consisting o two AND gates and two OR gates, with ive inputs and two outputs. His analysis o the circuit was in the same vein as that given in the previous section. He concluded that the circuit is Boolean and computes the unctions: = a + b + x(c + d + x ) = a + b + x(c + d) 2 = c + d + x(a + b + x 2 ) = c + d + x(a + b). As with circuit in Figure 5, McCaw argues that his circuit has ewer AND and OR gates than is possible with an acyclic circuit implementing the same unctions. Even earlier, in 960, Short applied an abstract graphical model to the study o switching networks with directional switches (Short, 96). He argued that networks must be cyclic or some minimal orms. In 970, Kautz, Short s Ph.D. advisor at Stanord, presented a short paper on the topic o eedback in circuits with logic gates (Kautz, 970). He described a cyclic circuit consisting o 6 an-in two NOR gates with three inputs and three outputs. Although plausible, his circuit is not Boolean according to the rigorous model that we propose. (It assumes that all wires have deinite Boolean values at the outset.) 7

8 x a b x c d AND OR AND OR 2 Figure 8: A cyclic Boolean circuit due to McCaw. In 97, Human discussed eedback in linear threshold networks. He claimed that an arbitrarily large number o input variables can be complemented in a network containing a single NOT element, provided that eedback is used (Human, 97). This improved upon an earlier result by Markov, demonstrating that k NOT elements suice to generate the complements o 2 k variables (Markov, 958). As with Kautz s example, Human s doesn t quite work. Still, in an insightul commentary on his and Kautz s work, he hinted at the possible implications, At this time, these [cyclic] examples are isolated ones. They do, however, provide tantalizing glimpses into an imaginable area o uture research. In 977, Rivest presented a general version o the circuit in Figure 5 and proved that it is optimal (Rivest, 977). For any odd integer n greater than, the general circuit consists o n an-in two AND gates alternating with n an-in two OR gates, with input variables x,..., x n arranged as in Figure 5. It produces 2n distinct output unctions, each o which depends on all n input variables. He proved that any acyclic circuit implementing the same 2n output unctions requires at least 3n 2 an-in two gates. Thus, asymptotically, his cyclic implementation is at most two-thirds the size o the best possible acyclic implementation. In 978, Khrapchenko was the irst to recognize that depth and delay in a circuit are not equivalent concepts (Khrapchenko, 978). With alse paths, the delay o a circuit can be less than that o the longest path. 8

9 In more recent work, we advocated the design o cyclic circuits in practice. We discussed techniques or validating cyclic circuits (Riedel and Bruck, 2003a, 2004; Backes et al., 2008). We proposed strategies or synthesizing cyclic circuits with computeraided design tools (Riedel and Bruck, 2003b; Backes and Riedel, 2009). Our synthesis tool, CYCLIFY, optimizes the designs o circuits by introducing cycles in the restructuring and minimization phases o logic synthesis. It reduces the number o gates needed by overlapping the computation o multiple unctions (as Rivest s example hinted at). It reduces the delay o circuits by moving computation o o critical paths (as Khrapchenko s work hinted at)..4. Overview In this paper, we study cyclic Boolean circuits rom a theoretical perspective: we exhibit amilies o cyclic circuits that are optimal in the number o gates and we prove lower bounds on the size o equivalent acyclic circuits. First, we present a cyclic circuit with only two gates and argue that an equivalent acyclic circuit requires three gates. Next, we present a cyclic circuit with three gates and argue that an equivalent acyclic circuit requires ive gates. Finally, we present a amily o cyclic circuits with n gates and prove that an equivalent amily o acyclic circuits requires at least 2n gates. Accordingly, we conclude that the cyclic complexity o unctions can be as little as one-hal o the acyclic complexity. Our lower bound is based on a an-in argument: in order to compute a unction that depends on a certain number o variables using gates with a certain an-in, we require a tree o at least a certain size. We show that this is largest gap that can be obtained with this an-in lower bound technique. 9

10 2. Framework 2.. Notation Algebraically, we use the standard notation: addition (+) denotes disjunction (OR), multiplication ( ), denotes conjunction (AND), and an overbar ( x) denotes negation (NOT). The restriction operation (also known as the coactor) o a unction with respect to a variable x reers to the assignment o a constant value to x in the expression or. We use the notation x to denote the restriction o x to and x to denote the restriction o x to 0. A unction depends upon a variable x i x is not identically equal to x. Call the variables that a unction depends upon its support set. We will oten represent unctions in so called Reed-Muller orm, a canonical orm consisting o exclusive-o (XOR) and conjunction (AND) operations. We denote XOR with the symbol. As early as 929, Zhegalkin showed that this representation is canonical (Zhegalkin, 929): i we multiply out all parentheses, perorm the simpliications x x = 0 and x x = x, and sort the product terms, the resulting expression is unique. For instance, the unction = x ( x 2 + x 3 ). is represented as = x x 2 x 3 x x 2 x 3. Note that x = x. When writing arithmetical expressions, we assume that AND has precedence over XOR, so x yz represents x (yz). The Reed-Muller representation has distinct advantages when manipulating expressions algebraically. In particular, the dependence o a unction on its variables is explicit: i a variable appears in the expression, then the unction depends on it Circuit Model Graphically, a circuit consists o gates connected by wires. Each gate has one or more inputs and a single output. The symbols or common gates are shown in Figure 9. A bubble is used to indicate that an input or output is negated, as illustrated in Figure 0. 0

11 AND OR XOR NOT Figure 9: Symbols or dierent types o gates. Figure 0: Here z = x + y. Bubbles on the inputs or the output o a gate indicate negation. An example o a circuit is shown in Figure. Even though a wire may split in our diagrams, as is the case with wire w 8 in Figure, conceptually there is a single instance o it. In general, A circuit accepts signals x,..., x m, ranging over {0, }, called the primary inputs. Each primary input is ed into one or more gate inputs. Even though the symbol or a primary input may appear in several places, as is the case with x, x 2 and x 3 in Figure, conceptually there is a single instance o it. The gates in the circuit produce internal signals, w,..., w n ranging over {0,, }. (We discuss the third value,, in Section 2.4.) A subset o the set o internal signals is designated as the set o primary outputs. A gate implements a Boolean unction, i.e., a mapping rom Boolean inputs to a Boolean output value, g : {0, } d {0, }. The set o inputs to a gate are called its an-in set. When we say a an-in d gate, we mean a gate with an-in set o cardinality d. The set o gates that are attached to a gate output are called its an-out set.

12 w x 3 g w 5 g 5 x 2 x w 7 g 7 g 2 w 2 x g 8 w 8 x g 3 w 3 g 4 x 3 w 9 g 9 w 6 g 6 x 2 x w 4 input signals: x, x 2, x 3 internal signals: w,..., w 9 output signals: w, w 4, w 8 gates: g,..., g 9 Figure : An example o a circuit, consisting o gates and wires. 2

13 2.3. Gate Model Any discussion o circuit complexity is predicated on a restricted gate model o some kind. Otherwise, with gates o arbitrary size and complexity, any unction can be implemented with a single gate. We restrict the scope o gates in two ways. The irst way is to bound the an-in, as shown in Figure 2 (a). Each gate can have at most d inputs, or some integer d. The second way is to restrict the type o gate. For instance, we can limit ourselves to so-called AND-OR-NOT (AON) gates, i.e., AND gates with the inputs and output possibly negated. An example o such a gate is shown in Figure 2 (b). The general orm o the Boolean unction realized by an AON gate is g(x, x 2,..., x d ) = (x c ) (x 2 c 2 ) (x d c d ) c d+, where c,..., c d+ are arbitrary choices o 0 and. x x 2 x d x x 2 x 3 (a) (b) Figure 2: Restricting the scope o gates. (a) Bound the an-in. (b) Use AND gates (with the inputs and output possibly negated) Boolean Circuits Analysis o an acyclic circuit is transparent. We irst evaluate the gates connected only to primary inputs, and then gates connected to these and primary inputs, and so on, until we have evaluated all gates. The previous values o the internal signals do not enter into play. In a cyclic circuit, there are one or more strongly connected components. Recall that in a directed graph G, a strongly connected component is an induced subgraph S G such that 3

14 there exists a directed path between every pair o nodes in S ; or every node s in S and every node n outside o S, i there exists a path rom s to n (rom n to s) then there is no path rom n to s (rom s to n, respectively). We can analyze each strongly connected component separately. We adopt a ternary ramework or analysis. We assume that, at the outset, all wires in a circuit have unknown or possibly undeined values, which we denote with the symbol. We apply deinite values to the inputs, and track the propagation o signal values. With only the primary inputs ixed at deinite values, each gate in a strongly connected component has some unknown/undeined inputs, valued. Nevertheless, or each such gate we can ask: is there suicient inormation to conclude that the gate output is 0 or, in spite o the values? I yes, we assign this value as the output; otherwise, the value persists. For instance, with an AND gate, i the inputs include a 0, then the output is 0, regardless o other inputs. I the inputs consist o and values, then the output is. Only i all the inputs are is the output. This is illustrated in Figure 3. Input values that determine the gate output are called controlling. 0 AND 0 AND AND Figure 3: An AND gate with 0,, and inputs. Consider the circuit ragment in Figure 4. One might be tempted to reason as ollows: the output o the AND gate g is ed in complemented and uncomplemented orm into the OR gate g 2. Thus, one o the inputs to the OR gate must be, and so its output must be. And yet, by deinition, designates an unknown, possibly undeined value. (For instance, in an actual circuit, it could indicate a voltage value exactly hal way between logical 0 and logical.) In our analysis, we remain agnostic: the output o the OR gate is. In the analysis, we track the propagation o well-deined signal values. Once a 4

15 g AND g 2 OR Figure 4: An illustration unknown/undeined values. deinite value is assigned to an internal wire, this value persists or the duration (so long as the input values are held constant). For any input assignment, a circuit reaches a so-called ixed point in the ternary ramework: a state where no urther updates o controlling values are possible. This ixed point is unique (Brzozowski and Seger, 995). We adopt the ollowing deinition. A circuit is Boolean i, or every assignment o input values, with all the wires initially set to, the circuit reaches a ixed point that does not contain any values on the outputs. We illustrate the analysis with two cyclic examples: one that is not Boolean and one that is. Example Consider the circuit shown in Figure 5, consisting o an AND gate g, an OR gate g 2, and an AND gate g 3, in a cycle. By inspection, note that i x = 0 then assumes value 0; i x 2 = then 2 assumes value ; and i x 3 = 0 then 3 assumes value 0. But what happens i x =, x 2 = 0 and x 3 =? In this case, all the outputs equal, as illustrated in Figure 6. The outcome or all eight cases is shown in Figure. We conclude that the circuit is not Boolean. Example 2 Consider the circuit in Figure 7. Suppose that we apply inputs x =, x 2 = 0, x 3 =. Gates g, g 3, g 5 and g 7 produce outputs o, 0, 0, and, respectively. Gate g 2 produces an output o. Gate g 8 produces an output o 0. Gate g 9 produces an output o 0. Gate g 6 produces an output o 0. Finally, gate g 4 produces an output o 0. These values are shown in Figure 7. The analysis or all eight input combinations is summarized in Table 8. We conclude that the circuit is Boolean. 5

16 x x2 x3 g g 2 g 3 AND OR AND 2 3 Figure 5: A cyclic circuit that is not Boolean. Figure 6: The circuit o Figure 5 with x =, x 2 = 0 and x 3 =. x x 2 x Table : Analysis o the circuit in Figure 5. 6

17 g 0 x 3 g 5 x 2 0 g 7 x 0 g 2 g g 6 0 g 8 g 9 0 x g 4 x 3 x 2 0 Figure 7: The circuit o Figure with inputs x =, x 2 = 0, x 3 =. x x 2 x 3 g g 2 g 3 g 4 g 5 g 6 g 7 g 8 g Figure 8: Analysis summary or the circuit o Figure. 7

18 3. Optimality and Lower Bounds Our general strategy in the ollowing constructions is to present a cyclic circuit that is optimal in the number o gates, and then prove a lower bound on the size o any acyclic circuit implementing the same unctions. (For what ollows, when we say circuit size, we mean the number o gates.) The argument or the optimality o the cyclic circuit rests on two properties: Property Each o the output unctions depends on all the variables. Property 2 The output unctions are pairwise distinct. The cyclic circuit is shown to be optimal according to the ollowing trivial claim (true regardless o the gate model): Claim A circuit implementing m distinct unctions consists o at least m gates. Lower bounds on circuit size are notoriously diicult to establish. In act, such proos are related to undamental questions in computer science, such as the separation o the P and NP complexity classes. (To prove that P NP it would suice to ind a class o problems in NP that cannot be computed by a polynomially sized circuit.) Much o the recent work in circuit complexity has been spurred by these open problems. All existing lower bounds on circuit size are linear in the number o variables (Vollmer, 999). In 949, Shannon showed by a straight orward counting argument that nearly all unctions require circuits with an exponential number o gates (Shannon, 949). Yet there is no known explicit example (Wegener, 987). We prove that some cyclic Boolean circuits are smaller than equivalent acyclic circuits based on a an-in lower bound. We show that this is largest gap that we can prove using the an-in lower bound technique. 8

19 3.. Fan-in Lower Bound Our lower bound on the size o an acyclic circuit is ormulated as a an-in argument. The essence o the argument was presented by Rivest (Rivest, 977), although we present it in a more general orm. A circuit can only compute a unction o a given set o input variables i it sees all o them. For example, in Figure 9, gate g 2 can compute a unction o x, x 2 and x 3 ; gate g cannot compute a unction o x 3 since it does not see x 3. In an acyclic Figure 9: A gate can only compute unctions o variables that it sees. circuit, there is a partial ordering among the gates: i a gate g i depends on a gate g j, directly or indirectly, then g j cannot depend on g i, directly or indirectly. With a partial ordering on the output unctions, there must be at least one output unction at the top which depends upon no other. I this unction depends on v input variables, the gate producing it must be the root o a tree that sees all these v variables as leaves. The lower bound is based on a calculation o the minimum number o gates in this tree. Claim 2 An acyclic circuit implementing m distinct output unctions, each depending on v input variables, consisting o gates with an-in at most d has at least v + m d gates. This is true or any an-in value d 2. 9

20 Proo: Consider a connected directed acyclic graph (DAG). Call nodes with no incoming edges leaves, and all other nodes internal nodes. We show, by a simple inductive argument, that a connected DAG with k internal nodes, each with in-degree at most d, has at most k(d ) + leaves. Obviously, a graph consisting o a single such internal node has at most d leaves. Suppose an internal node with in-degree at most d is added to a connected DAG. I the resulting graph is to be a connected DAG, the new node can replace an existing lea or it can be attached to an existing internal node. The ormer case is illustrated with node g in Figure 20, and the latter with node g 2. In both cases there is a net gain o at most d leaves. We conclude that connected DAG with k internal nodes has at most d + (k )(d ) = k(d ) + leaves, as expected. Suppose that a connected DAG has v leaves. Since v k(d ) +, the number o internal nodes k is bounded by v k. d Now, in an acyclic circuit implementing m output unctions, at least one o the output unctions depends on no other. By the argument above, this output unction requires at least v d gates. With distinct output unctions, each output unction must emanate rom a dierent gate, so at least m gates are required to implement the remaining m unctions Improvement Factor Suppose that we have a cyclic circuit with m gates, each with an-in at most d, that implements m distinct unctions, each o which depends on all v input variables. 20

21 Figure 20: Adding a node with in-degree d to a connected DAG results in net gain o at most d leaves. Call the improvement actor the ratio o size o the cyclic circuit to the lower bound on the size o the acyclic circuit: size o cyclic size o acyclic = v d m. + m With an improvement actor o C, we can say that our cyclic circuit is C times the size o any equivalent acyclic circuit. Claim 3 The improvement actor is bounded below by 2. Proo: For a given d, the improvement actor is minimized i the term v d in the denominator is maximized. Now, the number o variables v in a cyclic circuit is at most m(d ), and this is achieved i all the gates have an-in d. For such a circuit, 2

22 the improvement actor is i d 3 and i d = 2. m m = m d + m 2m 2 m 2m Rivest s Circuit Consider the circuit shown in Figure 2, due to Rivest (Rivest, 977). This is the same circuit as in Figure 5, shown again or the reader s convenience; however, here we provide a slightly dierent analysis o it, based on controlling values. We irst veriy x x2 x3 x x2 x3 g g 2 g 3 g 4 g 5 g Figure 2: A cyclic Boolean circuit with 3 inputs, due to Rivest (Rivest, 977). that this circuit is Boolean. For gate g, an AND gate, x = 0 is a controlling value. Setting x = 0 we have x = 0, 2 x = ( ) x + x2 = x 2, 3 x = ( ) 2 x x3 = x 2 x 3, 4 x = ( ) 3 x + 0 = x2 x 3, 5 x = ( ) 4 x x2 = x 2 x 3, 6 x = ( ) 5 x + x3 = x 3. All outputs assume deinite Boolean values. For gate g 4, an OR gate, x controlling value. Setting x =, we have = is a 22

23 4 x =, 5 x = ( ) 4 x x2 = x 2, 6 x = ( ) 5 x + x3 = x 2 + x 3, x = ( ) 6 x = x2 + x 3, 2 x = ( ) x + x2 = x 2 + x 3, 3 x = ( ) 2 x x3 = x 3. Again, all outputs assume deinite Boolean values. Since x must either have value 0 or value, we conclude that the network is Boolean. We assemble the output unctions rom these two cases. Applying distributivity and absorption, we obtain = x x + x x = x 0 + x (x 2 + x 3 ) = x (x 2 + x 3 ) 2 = x 2 x + x 2 x = x x 2 + x (x 2 + x 3 ) = x 2 + x x 3 3 = x 3 x + x 3 x = x x 2 x 3 + x x 3 = x 3 (x + x 2 ) 4 = x 4 x + x 4 x = x x 2 x 3 + x = x + x 2 x 3 5 = x 5 x + x 5 x = x x 2 x 3 + x x 2 = x 2 (x + x 3 ) 6 = x 6 x + x 6 x = x x 3 + x (x 2 + x 3 ) = x 3 + x x 2. Rivest presented a more general version o this circuit. For any odd integer n greater than, the general circuit consists o n two-input AND gates alternating with n twoinput OR gates in a single cycle, with inputs x,..., x n repeated, as shown in Figure 22. Analyzing the general circuit in the same manner as above, we ind that it implements x x2 x x2 xn g g 2 g n+ g n+2 g 2n 2 n+ n+2 2n Figure 22: A cyclic Boolean circuit with n inputs (or any odd n 3) due to Rivest. 23

24 the unctions = x (x n + x n ( (x 3 + x 2 ) )) 2 = x 2 + x (x n + (x 4 x 3 ) ). 2n = x n + x n (x n 2 + (x 2 x ) ). Note that the unctions are symmetrical with respect to a cyclic permutation o the variables. More precisely, the unctions 3, 5,... 2n are obtained rom by the cyclic permutation o the variables x, x 2,... x n : 3 (x, x 2,..., x n ) = (x 2, x 3,..., x ), 5 (x, x 2,..., x n ) = (x 3, x 4,..., x 2 ),.. 2n (x, x 2,..., x n ) = (x n, x,..., x n ). Similarly, the unctions 4, 6,..., 2n are obtained rom 2 through a cyclic permutation o the variables Optimality To show that Rivest s circuit is optimal, we must show that it satisies Properties and 2.. To show that each unction depends on all n input variables, we note that in the parenthesized expression, each variable appears exactly once. Without loss o generality, consider the i-th unction i in the list, or an odd i, and consider the j-th variable appearing in its expression, rom the let-hand side. To show the dependence on this variable, set each variable preceding a product to, and each variable preceding a sum to zero, beginning on the let-hand side, until we arrive at x j. Set the variable ollowing x j to and all variables ollowing that to 0. The result is i = (0 + (0 + + x j ( + 0(0 + 0( ))))) = x j. 24

25 2. To show that all the unctions are distinct, we exhibit an assignment that sets any chosen unction to 0 i it is odd-numbered (to i it is even-numbered), while setting all the other unctions to (to 0, respectively). Without loss o generality, consider unction i, or an odd i n. This unction is the output o an AND gate with input x i. Set x i to 0 and set all the other the variables to. Clearly, i has value 0 while all the other unctions have value in this case. (Rivest stated these conditions without proo.) Acyclic Lower Bound Note that the Rivest circuit has n input variables and implements 2n distinct output unctions with 2n an-in 2 gates. According to Claim 2, an acyclic circuit implementing the same unctions requires at least n + 2n = 3n 2 2 an-in 2 gates. For large n, the improvement actor is size o cyclic size o acyclic = 2n 3n Rivest s cyclic circuit is two-thirds the size o any acyclic circuit implementing the same unctions. Given a circuit with a single cycle, we can always obtain a corresponding acyclic version by breaking the eedback and doubling the length o the chain, as shown in Figure 23. (The input indicates any constant value.) In general, this will not yield an optimal acyclic circuit. However, in the case o Rivest s circuit, the bound o 3n 2 is, in act, tight. To obtain an acyclic circuit with 3n 2 gates, we break the cycle and prepend a copy o the last n 2 gates. For n = 3, we simply prepend an OR gate with inputs x 2 and x 3, as shown in Figure 24. Rivest s circuit is also optimal seen rom a dierent perspective. The circuit consists o AON gates, and yet none o the output unctions are implementable with a single AON gate, regardless o the an-in. Thus, any acyclic circuit implementing the unctions requires at least one more gate. 25

26 Cyclic Circuit g g n n Acyclic Circuit g g n g g n copy n Figure 23: Obtaining an equivalent acyclic circuit rom a cyclic circuit A Generalization We note that Rivest s circuit can be generalized to AND and OR gates with arbitrary an-in. The circuit shown in Figure 25 consists o 2n an-in d AND and OR gates, with n(d ) inputs repeated, or n 3, n odd, and d 2. This circuit produces outputs = y (y n + y n ( (y 3 + y 2 ) )) 2 = y 2 + y (y n + (y 4 y 3 ) ). 2n = y n + y n (y n 2 + (y 2 y ) ), where y = x x d y 2 = x d + + x 2d 2. y n = x (n )(d )+ + + x n(d ). 26

27 x x2 g g 2 x 3 g 3 x2 2 g 4 x3 3 g 5 x 4 g 6 x2 5 g 7 x3 6 Figure 24: An acyclic circuit implementing the same unctions as the circuit in Figure 2. x x d x d x 2d 2 x x d x d x 2d 2 x ( n )( d ) x n(d ) g g 2 g n+ g n+2 g 2n 2 n+ n+2 2n Figure 25: A generalization o Rivest s circuit to gates with an-in greater than 2. 27

28 It may be shown that all 2n unctions are distinct, and that each depends on all n(d ) input variables Variants We note that many dierent circuits o the same general orm as Rivest s example exist. In Figure 26, we show a circuit with 4 variables and 8 gates in a single cycle. As with Rivest s circuit, this one produces distinct output unctions each o which depends on all our variables. = x( x2 + x3 + x4) 2 = x + x2 + x3x4 3 = xx 2x4 + x3 4 = ( x + x2) x3x4 5 = x + x2x3x4 6 = x + x2 + x3x4 7 = ( x + x2 + x4) x3 8 = ( x + x2) x3x4 Figure 26: A circuit with the same properties as Rivest s example. A more intriguing example is shown in Figure 27. It consists o two copies o Rivest s circuit with the outputs o the irst ed as inputs into the second. Although not 28

29 shown here, we assert that this circuits produces 20 unctions that are distinct, and each depends on all ive variables. a b c d e a b c d e g g 2 g 3 g 4 g 5 g 6 g 7 g 8 g 9 g g g 2 g 3 g 4 g 5 g 6 g 7 g 8 g 9 g Figure 27: A pair o Rivest circuits, n = 5, stacked A Minimal Cyclic Circuit with Two Gates We provide an example o a circuit with the same property as Rivest s circuit, but with only two gates. The circuit shown in Figure 28 consists o two an-in 4 gates o the orm g(w, x, y, z) = wx yz. connected in a cycle with 5 inputs, a, b, c, d, e. The circuit computes and g: = ab gc g = c de. To veriy that the circuit is Boolean, note that i c = 0, then and g assume deinite values. We have c = ab (g c ) 0 = ab g c = ( c ) de = ab de. Similarly, i c =, then and g also assume deinite values. We have g c = ( c ) 0 de = de c = ab (g c ) = ab de. 29

30 Assembling the output unctions, we obtain = c ( c ) + c ( c ) = cab c(ab de) = cab abc cde = ab cde, g = c (g c ) + c (g c ) = c(ab + de) cde = cab + cdee + cde = ab c de. With the unctions thus written in Reed-Muller orm, we can readily assert that and g are distinct and that each depends on all 5 variables. Now, consider an acyclic circuit, also with an-in 4 gates, that computes the same unctions. Since a single an-in 4 gate cannot possibly compute a unction o 5 variables, we conclude that the acyclic circuit must have at least 3 gates. Figure 28: A cyclic circuit with two gates A Cyclic Circuit with Two Cycles We continue the exposition o examples o cyclic Boolean circuits. We present an example with two cycles. This will be generalize to examples with multiple cycles, 30

31 culminating with the main result o the paper: a cyclic circuit that is one-hal the size o any equivalent acyclic circuit. Consider the circuit shown in Figure 29, written in a general orm. The inputs are x,..., x n, grouped together in the igure as X. (A diagonal line across a wire indicates that it represents multiple wires.) There are three gates, connected in a coniguration consisting o two cycles: = α β 3 2 = α 2 β = α 3 β 3 γ 3 2 δ 3 2 where the α s, β s, γ s, and δ s are arbitrary unctions o the input variables. X g = α β 3 X g 3 3 = α3 β3 γ 3 2 δ3 2 X g 2 2 = α2 β2 3 Input variables: X = x, x2,, K x n Figure 29: A cyclic circuit with two cycles. We analyze this circuit with the goal o obtaining a necessary and suicient condition or it to be Boolean, as well as expressions or the gate outputs in terms o the inputs. We proceed on a case-by-case basis. For what ollows, when we speak o values o α i, β i, γ i and δ i, or i =, 2, 3, we mean the values evaluated at X. 3

32 Case I Suppose that or some X, we have that β = 0. In this case assumes the deinite value α. This situation is shown in Figure 30. Now suppose urther that γ 3 δ 3 α = 0. In this X g = α X g 3 α β α ( γ δ α 3 = ) 2 X g 2 2 = α2 β2 3 Figure 30: The circuit o Figure 29 i β = 0. case, 3 assumes a deinite value o α 3 β 3 α. Given this value or 3, it ollows that 2 assumes the deinite value o α 2 β 2 α 3 β 2 β 3 α. This situation is shown in Figure 3. We conclude that the unctions assume deinite values i β = 0 and γ 3 δ 3 α = 0. Case II Similarly, it can be shown that the unctions, 2 and 3 assume deinite values i β 2 = 0 and β 3 δ 3 α 2 = 0. Case III Suppose that or some X, we have β = 0 and β 2 = 0. In this case and 2 assume deinite values o α and α 2, respectively. Given these values or and 2, it ollows that 3 assumes the deinite value o α 3 β 3 α γ 3 α 2 δ 3 α α 2. This situation is shown in Figure

33 X g = α X g 3 3 = α3 β3α X g 2 2 = α2 β2α 3 β2β3α Figure 3: The circuit o Figure 29 i β = 0 and γ 3 δ 3 α = 0. X g = α X g 3 3 = α3 β3α γ 3α 2 δ3αα 2 X g 2 2 = α 2 Figure 32: The circuit o Figure 29 i β = 0 and β 2 = 0. 33

34 Case IV Suppose that β 3 = γ 3 = δ 3 = 0. In this case 3 assumes the deinite value α 3. Given this value or 3, it ollows that and 2 assume the deinite values α β α 3 and α 2 β 2 α 3, respectively. This situation is shown in Figure 33. X g = α βα 3 X g 3 3 = α3 X g 2 = α β 2 2 2α 3 Figure 33: The Circuit o Figure 29 i β 3 = γ 3 = δ 3 = 0. The characteristic unctions or the our cases are: c (X) = β (γ 3 δ 3 α ), (2) c 2 (X) = β 2 (β 3 δ 3 α 2 ), (3) c 3 (X) = β β 2, (4) c 4 (X) = β 3 γ 3 δ 3. (5) We conclude that the circuit is Boolean i and only i c (X) + c 2 (X) + c 3 (X) + c 4 (X). 34

35 I this condition holds, then the unctions have values (X) = c α + c 2 (α β α 3 β γ 3 α 2 ) + c 3 α + c 4 (α β α 3 ) (6) 2 (X) = c (α 2 β 2 α 3 β β 3 α ) + c 2 α 2 + c 3 α 2 + c 4 (α 2 β 2 α 3 ) (7) 3 (X) = c (α 3 β 3 α ) + c 2 (α 3 γ 3 α 2 ) + c 3 (α 3 β 3 α γ 3 α 2 δ 3 α α 2 ) + c 4 α 3. (8) 3.6. A Circuit Three-Fiths the Size Let s make the circuit o Figure 29 somewhat more concrete. Suppose that the inputs are a, b, x, x 2,..., x n, y, y 2,..., y n, z, z 2,..., z n. Suppose that the gates are deined by α = āx, α 2 = by, α 3 = Z, where and X = x x 2, x n, Y = y y 2, y n, Z = z z 2, z n β = a, β 2 = b, β 3 = ā, γ 3 = b, δ 3 = ā b. The resulting circuit is shown in Figure 34. For this circuit, the conditions deined in Equations 2 5 evaluate to: c = ā(b + X), c 2 = b(a + Y), c 3 = ā b, c 4 = ab. It may easily be veriied that or every combination o values assigned to a and b, one o c, c 2, c 3, c 4 is true. The unctions deined in Equations 6 8 are (a, b, X, Y, Z) = X a(x Y Z) aby, 2 (a, b, X, Y, Z) = Y b(x Y Z) abx, 3 (a, b, X, Y, Z) = X Y Z XY a(x XY) b(y XY) abxy. 35

36 a, x x 2 K g = a X a 3 a, b, z z, 2 K g 3 3 = Z a b 2 ab 2 b, x x 2 K g 2 = by b 2 3 X Y Z ( x x x 2 n ( y y y 2 n ( z z z 2 n ) ) ) Figure 34: Variant o the circuit o Figure 29. With the unctions expressed in Reed-Muller orm, we can assert that they are distinct and that each depends on all the variables. To make the situation more concrete, suppose that X = c e g i, Y = d h j, Z = k l. There are a total o 2 variables (a through l). Each gate has an-in 6. This situation is shown in Figure 35. According to Claim 2, an acyclic circuit implementing the same unctions requires at least v + m d gates, where v = 2 (the number o variables), d = 6 (the an-in) and m = 3 (the number o unctions). Thus v d + m = = 5. 6 We conclude that the circuit in Figure 35 is at most 3 5 the size o any equivalent acyclic circuit. 36

37 a,c,e,g,i g = a ceg i) ( a 3 g 3 a,b,k,l 3 = k l a b 2 a b 2 b,d,,h,j g 2 2 = b d h j) ( b 3 Figure 35: Circuit o Figure 34 with 2 variables A Circuit One-Hal the Size Consider the circuit shown in Figure 36, a generalization o the circuit in Figure 29 to k gates. We argue the validity o this circuit inormally. On the one hand, or each variable x i, i x i = 0 then i does not depend on k+. On the other hand, i x i =, then k+ does not depend on i. We conclude that none o the k cycles can be sensitized, and so the circuit is Boolean. Now consider the unction i implemented by each gate. With x i = 0, we see that i depends on the variables y,,..., y,d. Since k+ depends on i, it also depends on these variables. Thus k+ depends all the variables y i, j or i =,..., k and j =,..., d. With x i =, we see that i depends on k+ ; hence it also depends on all these variables. We conclude that each unction depends on all the variables. With the an-in o the gates set to d, the number o variables is v = k(d ) + d 2k = (k + )d 3k and the number o gates is m = k +. 37

38 x, y,,, K, y, d g = xy x k+ x 2, y2,, K, y2, d g 2 2 = x2y2 x2 k+ k + x, K, xk, z, K, z d k g k + x k, yk,, K, yk, d g k k = xkyk xk k + Y ( y L y ) i,, k Z i = i,, d = L ( z z d k ) k+ = Z x x2 2 L xk k xl xk L k Figure 36: A generalization o the circuit o Figure

39 According to Claim 2, an acyclic circuit implementing the same unctions requires at least v + m d gates. The improvement actor is, v d m = + m k + = + k (k+)d 3k d k + k + 2k d + k gates. Suppose that d = 2k + and that k is large. Then the ratio is k + 2k 2. We conclude that the circuit o Figure 36 is at most one-hal the size o any equivalent acyclic circuit. According to Claim 3, this is the best possible improvement actor that we can obtain with the an-in lower bound o Section

40 4. Discussion In related work, we have explored the practical implications o cyclic Boolean circuits. We have described an eicient approach or analyzing cyclic circuits, and we have provided a general ramework or synthesizing such circuits. Our synthesis tool, called CYCLIFY, is built within the Berkeley SIS and ABC environments (Sentovich et al., 992; Mishchenko et al., 2007). Timing analysis is perormed with binary decision diagrams (BDDs) and Boolean satisiability (SAT)-based techniques (Riedel and Bruck, 2003a, 2004; Backes et al., 2008). Synthesis is perormed by introducing cycles through the incremental application o restructuring and minimization operations (Riedel and Bruck, 2003b). We have explored the technique o Craig interpolation or synthesizing cyclic unctional dependencies (McMillan, 2003; Backes and Riedel, 2009). Perhaps the most salient result to report is that cyclic solutions are not a rarity. On trials with industry-accepted benchmark circuits, we improved the design o many circuits signiicantly in terms o area and delay by introducing cycles. In theoretical computer science, one o the main goals is to prove lower bounds on the resources, such as time and space, required or computation. The Boolean circuit model is oten postulated as a representative model or computation with digital circuits. Unlike more abstract models o computation, such as Turing machines, Boolean circuits can be viewed as bit-level implementation o a computational procedure in a sense, the most basic way that one can compute something. A lower bound on the circuit size is taken as a true measure o the computational requirements o a problem. For instance, lower bounds on circuit size have be used to justiy the security o cryptographic algorithms (Rothe, 2002). Complexity theorists invariably deine a Boolean circuit as a directed acyclic graph (DAG) (Papadimitriou, 995, p. 80) and (Vollmer, 999, p. 8). It is conceivable that some o the proos o lower bounds on circuit size depend on this deinition. We hope that this paper will help promulgate the view that a Boolean circuit is not necessarily a DAG; rather it is a directed graph that may have cycles. This distinction is a undamental one. We have demonstrated that, both in theory and in practice, it is not only easible to design Boolean circuits with cyclic topologies, but this may well be the best way to design them. 40

41 Backes, J., Fett, B., Riedel, M. D., The analysis o cyclic circuits with Boolean satisiability. In: International Conerence on Computer-Aided Design. pp Backes, J., Riedel, M. D., The synthesis o cyclic dependencies with Craig interpolation. In: International Workshop on Logic and Synthesis. pp Brzozowski, J., Seger, C.-J., 995. Asynchronous Circuits. Springer-Verlag. Human, D. A., 97. Combinational circuits with eedback. In: Mukhopadhyay, A. (Ed.), Recent Developments in Switching Theory. Academic Press, pp Katz, R., 992. Contemporary Logic Design. Benjamin/Cummings. Kautz, W. H., 970. The necessity o closed circuit loops in minimal combinational circuits. IEEE Transactions on Computers C-9 (2), Khrapchenko, V., 978. Depth and delay in a network (in Russian). Soviet Mathematics Doklady 9, Markov, A., 958. On the inversion complexity o a system o unctions. Journal o the ACM 5, McCaw, C., 963. Loops in directed combinational switching networks. Ph.D. thesis, Stanord University. McMillan, K. L., Interpolation and SAT-based model checking. In: International Conerence on Computer Aided Veriication. pp. 3. Mishchenko, A., et al., ABC: A system or sequential synthesis and veriication. URL alanmi/abc/ Papadimitriou, C. H., 995. Computational Complexity. Addison-Wesley. Riedel, M. D., Bruck, J., 2003a. Cyclic combinational circuits: Analysis or synthesis. In: International Workshop on Logic and Synthesis. pp Riedel, M. D., Bruck, J., 2003b. The synthesis o cyclic combinational circuits. In: Design Automation Conerence. pp

42 Riedel, M. D., Bruck, J., Timing analysis o cyclic combinational circuits. In: International Workshop on Logic and Synthesis. Rivest, R. L., 977. The necessity o eedback in minimal monotone combinational circuits. IEEE Transactions on Computers 26 (6), Rothe, J., Some acets o complexity theory and cryptography. ACM Computing Surveys 34 (4), Sentovich, E. M., et al., 992. SIS: A system or sequential circuit synthesis. Tech. rep., University o Caliornia, Berkeley. Shannon, C. E., 949. The synthesis o two terminal switching circuits. Bell System Technical Journal 28, Short, R., 96. A theory o relations between sequential and combinational realizations o switching unctions. Ph.D. thesis, Stanord University. Vollmer, H., 999. Introduction to Circuit Complexity. Springer. Wakerly, J. F., Digital Design: Principles and Practices. Prentice-Hall. Wegener, I., 987. The Complexity o Boolean Functions. John Wiley & Sons. Zhegalkin, I., 929. The arithmetization o symbolic logic (in Russian). Matematicheskii Sbornik 36,