Network Analysis at IIT Bombay

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Martin Jared Bryan
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1 H. Narayanan Department of Electrical Engineering Indian Institute of Technology, Bombay October, 2007

2 Plan Speed-up of Network Analysis by exploiting Topological Methods. Adaptation of standard linear algebraic algorithms to networks (eg. Cholesky, CG) by interpretation of elementary steps as electrical processes. Development of new iterative methods for electrical networks (e.g. hybrid analysis with modified CG). Iterative methods at the non-linear constraint level (suitable for circuits with well defined direction of action, eg. digital circuits with long loops) 1. 1 This idea was used in BREMICS

3 Applications Applied to various situations, such as... Optimization Partitioning Linear Equation Solution Circuit Simulators Biological Systems CS Algorithms

4 Approach We concentrate on networks with Resistors, Voltage Sources, Current Sources and Ideal Diodes. Why? 1 Speeding up this analysis will give some clues towards solving more general circuits. These are related to convergence of Newton Raphson iterations as well as the inner loop conjugate gradient iterations which can be large because of high condition number of the coefficient matrix. 2 Can solve some standard Computer Science problems approximately. (e.g: min cost flow, shortest path, partitioning).

5 Where have we reached at present 1 Can solve 700, 000 node min-cost flow problem within 0.1% of optimum. If cost and capacity have large range ( ), speeds are competitive with available computer science softwares. 2 Can solve RVJ circuits upto 8.2 million nodes and 16.2 millions edges in 2475 seconds using 10/100 Mbps unmanaged Ethernet switch for interconnecting PIV 3.0 GHz processors (1 master and 8 slaves) each having 1.0GB RAM. 3 Can solve million node non-planar RVJ circuits in a few minutes (1 million nodes and 3 million edges RVJ electrical network in 61 seconds). We use both LU (direct) and CG (iterative).

6 DC-Analyzer vs. Spice3 comparision Circuit t commsim t dcana g10k g20k g30k g40k g50k g70k g90k g100k Table: Simulation results: DC analyzer v/s fastest commercial simulator for planar RVJ circuits

7 Figure: Comparison between FCS and DC analyzer

8 Recent Improvements with Cholesky Cholesky vs. LU vs. CG for planar and non-planar cases a a AMD64/Opteron/4GB, LU: SuperLU, Cholesky: CHOLMOD, time: secs Network Type non-planar 1 non-planar 2 n e t LU t CHOL t DpCG t InCholpCG t LU t CHOL t DpCG t InCholpCG 30k 90k k 120k k 150k k 200k k 600k k 1500k Table: Resistance Range: , Percentage of J = 20%, V = 20%

9 RVJ networks with V = J = 20% and R-Range = Ω Network Type Dense grid planar n e t LU t CHOL t DpCG 200k 600k k 1500k M 3M M 15M Network Type Uneven window planar n e t LU t CHOL t DpCG 100k 125k k 188k k 250k k 625k M 1.25M 3.3

10 Major Issues SPARSE PLANAR NON-PLANAR CG good excellent LU excellent terrible Cholesky better than LU far better than LU CG fails if the range of conductances in the circuit is too large ( 10 8 ). Works well in 10 4 range.

11 Workarounds: Hybrid Analysis CG failure can be handled by (we believe, based on numerical evidence) using Hybrid Analysis. Trick Conductances in the range are scaled to and treated as Resistance, in the range (Loop equations) Conductances, in the range (Nodal analysis) Modified CG behaves like it would have in range.

12 Hybrid Analysis (contd) Difficulties Matrix can be dense, so storage could be expensive. Solution We need, given ( x1 x 2 ) [ ] A H, find H T. B The matrix is stored implicitly. Graph partition into resistances and conductances.

13 Question: How to Speed up CG? part of it through hardware (particularly, multiplication) more elaborate part (involving intricate algorithms), through Software. Ax = b KGK T x = b K: reduced incidence matrix of a graph(stored as a graph), G: diagnal x K T x G(K T )x K(GK T x) software (hardware) (software graph theoretic) graph theoretic

14 DC-analyzer vs. MCF-v1.3 fgraph mcf-1.3 DC Analyzer C MCF t MCF C DCF S t DCF S Error(%) Fg10k Fg50k Fg100k Fg150k Fg200k Fg250K Fg300k Fg350k Fg400k Fg450k Fg500k Fg600k Fg700k Table: Random nonplanar flow graph results 2 with 10% of Max Flow 2 P4 3.0Ghz/4GB

15 N AL -N BK Results a a P4 2.4Ghz/4GB Circuit size t P CG 1k k k k k k k k k k k million t LU dcana Table: Nonplanar circuit analysis using LU-dcAnalyzer and diagonal PCG for conductance range 1 mho to mho and resistance range 1 ohm to ohm

16 N AL -N BK Results Ckt size 3 t SpecialpCG Iterations t DpCG Iterations 1k k k k k k k k k k k million Table: Nonplanar circuit analysis using block preconditioned Incomplete Cholesky and diagonal PCG for conductance range 1 mho to mho and resistance range 1 ohm to ohm 3 incomplete-cholesky approximate block-diagonal preconditioning

17 Past work: BREMICS and BITSIM Bremics Bitsim Point relaxation based circuit simulator for digital circuits with long loops Built in 1990 General pupose circuit simulator (like spice) built for testing the use of CG method through Hybrid Analysis (MNA unsuited for CG) Built in 1991

18 How is/was the work done? Through M. Tech., Dual Degree and Ph. D. projects. Number of students since 1998 on network analysis projects M.Tech. + Dual Degree : 15+1 completed PhD : 1 completed Earlier work (BITSIM, BREMICS), , M.Tech. : 10 completed PhD : 2 completed Presently, 3 Dual Degree students 2 M.Tech. students

19 Thank You.

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