Instruction Selection

Transcription

1 Compiler Design Instruction Selection Hwansoo Han

2 Structure of a Compiler O(n) O(n) O(n log n) Scanner words Parser IR Analysis & Optimization IR Instruction Selection Either fast or NP-Complete asm asm asm regs Instruction Scheduling NP-Complete regs Register Allocation NP-Complete k regs The hard stuff is mostly in code generation and optimization Conventional wisdom says that we lose little by solving these three problems independently 2

3 Big Picture of Code Generation Instruction selection Maps IR into assembly code Assumes a fixed storage mapping & code shape Assume enough registers or target important values Can make locally optimal choices, but global optimality is NP- Complete Use some form of pattern matching Combine operations & use address modes 3

4 The Problem Modern computers (still) have many ways to do anything Consider register-to-register copy Obvious operation is i2i r i r j Many others exist addi r i,0 r j subi r i,0 r j lshifti r i,0 r j multi r i,1 r j divi r i,1 r j rshifti r i,0 r j ori r i,0 r j xori r i,0 r j and others Human would ignore all of these Algorithm must look at all of them and Find low-cost encoding Take context into account (busy functional unit?) 4

5 The Goal Want to automate generation of instruction selection Front End Middle End Back End Infrastructure Machine description Back-end Generator Tables Pattern Matching Engine Description-based retargeting Need pattern matching techniques Must produce good code (some metric for good ) Must run quickly 5

6 Simple Treewalk Simple treewalk code generator runs quickly How good is the code? Tree Treewalk Code Desired Code IDENT <a,arp,4> x IDENT <b,arp,8> loadi 4 r 5 loadao r 0,r 5 r 6 loadi 8 r 7 loadao r 0,r 7 r 8 mult r 6,r 8 r 9 loadai r 0,4 r 5 loadai r 0,8 r 6 mult r 5,r 6 r 7 6

7 Example: Quality of Treewalk Code Tree Treewalk Code Desired Code IDENT <a,arp,4> x NUMBER <2> loadi 4 r 5 loadao r 0,r 5 r 6 loadi 2 r 7 mult r 6,r 7 r 8 loadai r 0,4 r 5 multi r 5,2 r 7 Must combine these This is a nonlocal problem IDENT <c,@g,4> x IDENT <d,@h,4> Common offset r 5 loadi 4 r 6 loadao r 5,r 6 r 7 r 7 loadi 4 r 8 loadao r 8,r 9 r 10 mult r 7,r 10 r 11 7 loadi 4 r 5 loadai r 5,@G r 6 loadai r 5,@H r 7 mult r 6,r 7 r 8

8 Tree-Pattern Matching Many compilers use tree-structured IRs Abstract syntax trees generated in the parser Trees or DAGs for expressions These systems might well use trees to represent target ISA Consider add operators If we can match these pattern trees against IR trees, r i + r j r i + c j Operation trees add r i,r j r k addi r i,c j r k 8

9 AST Example Low-level AST for w x - 2 * y VAL ARP + NUM 4 REF REF + - NUM 2 * REF + ARP: r arp NUM: constant LAB: ASM label w: at ARP+4 (local var) x: at ARP-26 (call-by-ref) Y: (global var) VAL ARP NUM -26 NUM 12 9

10 Notation For Operation Tree To describe these trees, we need a concise notation + +(r i,c j ) r i c j + +(r i,r j ) Linear prefix form r i r j 10

11 Notation for Tree-Pattern AST To describe these trees, we need a concise notation + GETS - -(REF(REF(+(VAL 2,NUM 2 ))), *(NUM 3,(REF(+(LAB 1,NUM 3 )))))) *(NUM 3,(REF(+(LAB 1,NUM 3 )))))) VAL ARP NUM 4 REF * +(VAL 1,NUM 1 ) REF + NUM 2 REF + REF(REF(+(VAL 2,NUM 2 ))) VAL ARP NUM -26 NUM 12 GETS(+(VAL 1,NUM 1 ), -(REF(REF(+(VAL 2,NUM 2 ))), *(NUM 3,(REF(+(LAB 1,NUM 3 )))))) 11

12 Inst. Selection via Tree-Pattern Matching Goal is to tile AST with operation trees A tiling is collection of <ast, op > pairs ast is a node in the AST op is an operation tree <ast, op > means that op could implement the subtree at ast A tiling implements an AST Cover every node (overlap is limited to a single node) Compatible trees (if two operation trees meet, expect the value in the same location) 12

13 Example: Tiling the Tree GETS Tile 6 + VAL Tile 1 NUM ARP 4 REF REF + - Tile 5 * NUM Tile 4 2 REF + Each tile corresponds to a sequence of operations Emitting those operations in an appropriate order implements the tree. - Postorder or - Bottom-up walk VAL ARP Tile 2 NUM -26 Tile 3 NUM 12 13

14 Finding Matches to Tile Compiler relates operation trees to AST subtrees Provides a set of rewrite rules Encode tree syntax, in linear form Associated with each is a code template Production Rule Cost Code Template 1 Goal Assign 0 2 Assign GETS(Reg 1,Reg 2 ) 1 store r 2 r 1 3 Assign GETS(+(Reg 1,Reg 2 ),Reg 3 ) 1 storeao r 3 r 1,r 2 4 Assign GETS(+(Reg 1,NUM 2 ),Reg 3 ) 1 storeai r 3 r 1,n 2 5 Assign GETS(+(NUM 1,Reg 2 ),Reg 3 ) 1 storeai r 3 r 2,n 1 6 Reg LAB 1 1 loadi l 1 r new 7 Reg VAL Reg NUM 1 1 loadi n 1 r new 14

15 Rewrite Rules Production Rule Cost Code Template 9 Reg REF(Reg 1 ) 1 load r 1 r new 10 Reg REF(+ (Reg 1,Reg 2 )) 1 loadao r 1,r 2 r new 11 Reg REF(+ (Reg 1,NUM 2 )) 1 loadai r 1,n 2 r new 12 Reg REF(+ (NUM 1,Reg 2 )) 1 loadai r 2,n 1 r new 13 Reg + (Reg 1,Reg 2 ) 1 add r 1,r 2 r new 14 Reg + (Reg 1,NUM 2 ) 1 addi r 1,n 2 r new 15 Reg + (NUM 1,Reg 2 ) 1 addi r 2,n 1 r new 16 Reg - (Reg 1,Reg 2 ) 1 sub r 1,r 2 r new 17 Reg - (Reg 1,NUM 2 ) 1 subi r 1,n 2 r new 18 Reg - (NUM 1,Reg 2 ) 1 rsubi r 2,n 1 r new 19 Reg x (Reg 1,Reg 2 ) 1 mult r 1,r 2 r new 20 Reg x (Reg 1,NUM 2 ) 1 multi r 1,n 2 r new 21 Reg x (NUM 1,Reg 2 ) 1 multi r 2,n 1 r new 15

16 Finding Matches (1) Multiple possible tilings Need an algorithm to associate AST subtrees with the rules REF NUM 12 What rules match? 6: Reg LAB 1 tiles the lower left node 8: Reg NUM 1 tiles the bottom right node 13: Reg + (Reg 1,Reg 2 ) tiles the + node 9: Reg REF(Reg 1 ) tiles the REF We denote this match as <6,8,13,9> Of course, it implies <8,6,13,9> Both have a cost of 4 16

17 Finding Matches (2) Many Sequences Match Our Subtree Cost Sequences REF + 2 6,11 8,12 3 6,8,10 8,6,10 6,14,9 8,15,9 4 6,8,13,9 8,6,13,9 NUM 12 In general, we want the low cost sequence Each unit of cost is an operation (1 cycle) We should favor short sequences 17

18 Finding Matches (3) Low Cost Matches REF Sequences with Cost of 2 + 6: Reg LAB 1 11: Reg REF(+(Reg 1,NUM 2 )) r i loadai r i,12 r j NUM 12 8: Reg NUM 1 12: Reg REF(+(NUM 1,Reg 2 )) loadi 12 r i loadai r i,@g r j These two are equivalent in cost 6,11 might be better, may be longer than the immediate field 18

19 Inst. Selection via Peephole Optimization Compiler can discover local improvements locally Look at a small set of adjacent operations Move a peephole over code & search for improvement Original code Improved code storeai r 1 r 0,8 storeai r 1 r 0,8 loadai r 0,8 r 15 i2i r 1 r 15 < Store-load > addi r 2,0 r 7 mult r 4,r 7 r 10 mult r 4,r 2 r 10 < identical value > jumpi L 10 L 10 : jumpi L 11 L 10 : jumpi L 11 < jump chain > 19

20 Implementation of Peephole Optimization Implementation Early systems used limited set of hand-coded patterns Window size ensured quick processing Modern peephole instruction selectors (e.g. GCC) Break problem into three tasks IR LLIR LLIR ASM Expander Simplifier Matcher IR LLIR LLIR LLIR LLIR ASM LLIR: lower-level IR 20

21 Peephole Optimization Implementation Expander Turns IR code into a low-level IR (LLIR) such as RTL Operation-by-operation, template-driven rewriting Simplifier Looks at LLIR through window and rewrites Uses forward substitution, algebraic simplification, local constant propagation, and dead-effect elimination Performs local optimization within window Matcher Compares simplified LLIR against a library of patterns Picks low-cost pattern that captures effects Must preserve LLIR effects, may add new ones (e.g., set cc) 21

22 Example : Expand (1) Original IR Code OP Arg 1 Arg 2 Result mult 2 Y t 1 sub x t 1 w Expand LLIR Code r r 12 r 0 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 r 0 + r 15 r 17 MEM(r 16 ) r r 20 r 0 + r 19 MEM(r 20 ) r 18 Template-driven rewriting (e.g. TreeWalk) 22

23 Example : Simplify (2) LLIR Code r r 12 r 0 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 r 0 + r 15 r 17 MEM(r 16 ) r r 20 r 0 + r 19 Simplify MEM(r 0 r 18 LLIR Code r 13 MEM(r 0 r 14 2 x r 13 r 17 MEM(r 0 MEM(r 20 ) r 18 Local optimization within a window 23

24 Example : Match (3) MEM(r 0 r 18 LLIR Code r 13 MEM(r 0 r 14 2 x r 13 r 17 MEM(r 0 Match Final Code loadai r 0,@y r 13 multi 2 x r 13 r 14 loadai r 0,@x r 17 sub r 17 - r 14 r 18 storeai r 18 r 0,@w Compare against pattern library and find best match Turned out pretty good code 24

25 Example: Details of Simplifier (1) LLIR Code r r 12 r 0 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 r 0 + r 15 r 17 MEM(r 16 ) r r 20 r 0 + r 19 MEM(r 20 ) r 18 r r 12 r 0 + r 11 3-operation window 25

26 Example: Details of Simplifier (2) LLIR Code r r 12 r 0 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 r 0 + r 15 r 17 MEM(r 16 ) r r 20 r 0 + r 19 MEM(r 20 ) r 18 r r 12 r 0 + r 11 r 12 r 0 r 13 MEM(r 12 ) 26

27 Example: Details of Simplifier (3) LLIR Code r r 12 r 0 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 r 0 + r 15 r 17 MEM(r 16 ) r r 20 r 0 + r 19 MEM(r 20 ) r 18 r 12 r 0 r 13 MEM(r 12 ) r 13 MEM(r 0 r 14 r 10 x r 13 27

28 Example: Details of Simplifier (4) LLIR Code r r 12 r 0 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 r 0 + r 15 r 17 MEM(r 16 ) r r 20 r 0 + r 19 MEM(r 20 ) r 18 r 13 MEM(r 0 r 14 r 10 x r 13 r 13 MEM(r 0 r 14 2 x r 13 r 28

29 Example: Details of Simplifier (5) LLIR Code r r 12 r 0 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 r 0 + r 15 r 17 MEM(r 16 ) r r 20 r 0 + r 19 r 13 MEM(r 0 r 14 2 x r 13 r 1 st op it has rolled out of window r 14 2 x r 13 r r 16 r 0 + r 15 MEM(r 20 ) r 18 29

30 Example: Details of Simplifier (6) LLIR Code r r 12 r 0 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 r 0 + r 15 r 17 MEM(r 16 ) r r 20 r 0 + r 19 MEM(r 20 ) r 18 r 14 2 x r 13 r r 16 r 0 + r 15 r 14 2 x r 13 r 16 r 0 r 17 MEM(r 16 ) 30

31 Example: Details of Simplifier (7) LLIR Code r r 12 r 0 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 r 0 + r 15 r 17 MEM(r 16 ) r r 20 r 0 + r 19 MEM(r 20 ) r 18 r 14 2 x r 13 r 16 r 0 r 17 MEM(r 16 ) r 14 2 x r 13 r 17 MEM(r 0 +@x) 31

32 Example: Details of Simplifier (8) LLIR Code r r 12 r 0 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 r 0 + r 15 r 17 MEM(r 16 ) r r 20 r 0 + r 19 MEM(r 20 ) r 18 r 14 2 x r 13 r 17 MEM(r 0 +@x) r 17 MEM(r 0 +@x) r 32

33 Example: Details of Simplifier (9) LLIR Code r r 12 r 0 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 r 0 + r 15 r 17 MEM(r 16 ) r r 20 r 0 + r 19 MEM(r 20 ) r 18 r 17 MEM(r 0 +@x) r r r 20 r 0 + r 19 33

34 Example: Details of Simplifier (10) LLIR Code r r 12 r 0 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 r 0 + r 15 r 17 MEM(r 16 ) r r 20 r 0 + r 19 MEM(r 20 ) r 18 r r 20 r 0 + r 19 r 20 r 0 MEM(r 20 ) r 18 34

35 Example: Details of Simplifier (11) LLIR Code r r 12 r 0 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 r 0 + r 15 r 17 MEM(r 16 ) r r 20 r 0 + r 19 MEM(r 20 ) r 18 r 20 r 0 MEM(r 20 ) r 18 MEM(r 0 r 18 35

36 Example: Details of Simplifier (12) LLIR Code r r 12 r 0 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 r 0 + r 15 r 17 MEM(r 16 ) r r 20 r 0 + r 19 MEM(r 20 ) r 18 r 20 r 0 MEM(r 20 ) r 18 MEM(r 0 r 18 36

37 Example: Details of Simplifier (13) LLIR Code r r 12 r 0 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 r 0 + r 15 r 17 MEM(r 16 ) r r 20 r 0 + r 19 Simplify MEM(r 0 r 18 LLIR Code r 13 MEM(r 0 r 14 2 x r 13 r 17 MEM(r 0 MEM(r 20 ) r 18 37

38 Summary Simple treewalk Potentially poor code quality Tree-Pattern Tiling AST with operation trees Find possible tiles Match with the lowest cost tile Peephole match Expand into LLIR (such as RTL) that is machine independent Simplify using peephole optimizations (key strength of this scheme) Match with ASM Use a hand-coded pattern matcher Turn patterns into grammar & use LR parser (gcc) 38