X X. f 00. f 0. f 11. f 10. f 1. (b) pd. (a) S. (c) nd. f 110. f 101. f 010. f 011. f 01. f 100. f 000. f 111. f 001

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1 A Desgn Method for Look-up Table Type FPGA by Pseudo-Kronecker Expanson Tsutomu asao Kyushu Insttute of Technology Izuka 80, Japan Jon T. Butler Naval Postgraduate chool Monterey, CA 99, U..A. Aprl 15, Introducton. Feld programmable gate arrays (FPGA's) are very useful n rapd prototypng as well as small volume producton []. A look-up table (LUT) type FPGA shown n Fg. 1.1 conssts of LUT's and programmable nterconnecton. Both LUT's and programmable nterconnectons are controlled by statc RAMs. We assume that each FPGA has q LUT's, and each LUT can realze an arbtrary logc functon of k bnary varables. We also assume that nterconnecton resources are sucent,.e., any logcal network wth q LUT's can be realzed. Note that wrng s mplemented by pass transstors, and the delay tme for nterconnecton wll often be larger than for the LUT's. Consder the realzaton of a moderately complex functon. If k s small, e.g., k = or, the LUT's are ecently used, but the nterconnectons wll be complex. Ths wll be especally necent snce nterconnectons are often more expensve than logc. If k s large, e.g., k = 7 or 8, the nterconnectons wll be smpler, but the LUT's are not ecently used. Thus, there exsts an optmum value for k between and 7. One study [0] shows that when k = or, FPGA's requre the smallest chp area. However, these results have not been used by manufacturers. For example, for the XILINX 000 eres FPGA's, k =5,andfor the AT&T ORCA FPGA's, k = [1]. Varous desgn methods for LUT-based FPGA's are known: 1) Technology mappng from AND-OR mult-level logc crcuts []. ) Technology mappng from bnary decson dagrams (BDD's) []. ) Functonal decomposton [7, 1, ]. Commercally avalable FPGA's contan many LUT's, but the nterconnectons are much slower than other standard mask type gate-arrays. Thus, t s often more mportant to reduce the propagaton delay than to reduce the number of LUT's [5, 1]. To reduce the propagaton delay, wehave to reduce the number of the levels n the networks. Also, f the nterconnectons and layout are regular, then the propagaton delay wll be smaller. In ths paper, we propose a desgn method for LUTbased FPGA's that produces LUT networks havng the Fgure 1.1: LUT type FPGA X r- valued valued X X Fgure 1.: LUT network X 1 structure shown n Fg. 1.. We assume that each LUT has bnary nputs. By parng varables of twovalued nput functons, we can obtan four-valued nput functons. By usng four-valued logc, we can reduce the number of varables to consder, and can desgn a network havng a regular structure. We use the pseudo- Kronecker expanson for four-valued nput two-valued output functons to desgn compact and regular LUT networks. The proposed method s also promsng for the four-valued LUT based FPGA's [, 1, 1]. Realzaton of Two-Valued Input Functons Wth -nput LUT's Before studyng the realzaton of logc functons wth -nput LUT's, t s convenent to revew the f

2 f 0 X X X f 0 X1 f 0 f f X f 00 f 01 0 X 1 (a) (b) (c) nd X X X X Fgure.1: Logc crcuts correspondng to three types of expansons f 000 f 001 f 010 f realzaton for two-valued nput functons by -nput LUT's. Consder three expansons: f =x1f0 8 x1f1; (.1) f = f0 8 x1f; and (.) f = f1 8 x1f; where f = f0 8 f1: (.) (.1), (.), and (.) are called the hannon expanson, the postve Davo expanson, and the negatve Davo expanson, respectvely. Fg..1 shows the logc crcuts realzng these three expansons; they are denoted by,, and nd, respectvely. Note that a -nput LUT drectly realzes these crcuts. When the hannon expansons are used to expand f0 and f1, wehave f0 =xf00 8 xf01; and f1 =xf10 8 xf11; respectvely: In the smlar way, we can expand the new subfunctons as follows: f00 =xf000 8 xf001; f01 =xf010 8 xf011; f10 =xf100 8 xf101; and f11 =xf110 8 xf111: Fg.. s the bnary decson tree correspondng to the above expanson. If we replace each nodebya two-nput multplexer (Fg..1(a)), we have the network shown n Fg... To reduce the number of the multplexers, we use the followng rules: 1) If a sub-functon s a constant 0 or 1, termnate that branch. ) If two sub-functons are the same,.e., f f0 = f1, then extend the branchdown to the next level (.e., do not use a multplexer). ) If the current sub-functon (f ) s the same as one already generated (f j ), move the current branch (for f )over to the other branch (f j ). For example, f f01 s the same as f10, move the f10 branch over, thus mergng the two nodes. A decson dagram smpled by the above rule s called a (reduced ordered) bnary decson dagram (BDD). For a gven functon and a gven order of the nput varables, the BDD s unque. Fgure.: Representaton of logc functons usng the hannon expanson X X f 001 f 000 X1 f 011 f Fgure.: Realzaton of a logc functon usng multplexers If we use the postve Davo expanson nstead of the hannon expanson, then we have (.). When we use the same expanson for f0 and f, wehave f0 = f00 8 xf0; and f = f0 8 xf: Fg.. s the tree correspondng to ths expanson. Also, n ths case, we can reduce the dagram. uch a dagram s called the functonal decson dagram (FDD) [11]. For a gven functon and a gven order of the nput varables, the FDD s unque. In a smlar way, we can consder the expanson usng only the negatve Davo expanson. Also, we can consder an expanson usng ether the postve or negatve Davo expansons for each varable [1]. Next, consder the expanson where any one of the three expansons s permtted for each varable. For example, n Fg..5, the hannon expanson s used for x1, the postve Davo expanson s used for x, and the negatve Davo expanson s used for x. uch an expanson s called a Kronecker expanson [, 8]. The reduced dagram s the Kronecker decson dagram (KDD) [18]. For a gven functon and a gven order of the nput varables, there are at most n dfferent KDD's. A mnmum KDD s one wth the fewest nodes.

3 f 0 X1 f f 0 X1 f 00 X f 0 f 0 X f f 00 X f 0 1 X nd X X X X X X X nd X f f f f f f f f f 000 f 010 f f f f Fgure.: Representaton of a logc functon usng the postve Davo expanson Fgure.: Representaton of a logc functon usng the Pseudo-Kronecker expanson f 0 X1 BDD PKDD KDD FDD f 00 X f 0 0 X X nd X nd X nd X nd Fgure.7: Relaton among BDD's, FDD's, KDD's and PKDD's f f f f f f f f Fgure.5: Representaton of a logc functon usng the Kronecker expanson Furthermore, we can consder the followng expanson: Any one of the three expansons s permtted for any node. For example, n Fg.., the hannon expanson s used for x1, the postve and negatve Davo expansons are used for x, and all the three expansons are used for x. uch an expanson s called a pseudo-kronecker expanson [, 8], and the reduced dagram s called a pseudo-kronecker decson dagram (PKDD). For a gven functon f and the gven order of the nput varables, the PKDD wth the mnmum number of nodes (LUT's) s the mnmum PKDD for f. There are at most 01) (n derent PKDD's. The relaton among BDD, FDD, KDD and PKDD s shown n Fg..7. Ths shows that KDD's are a specal case of PKDD's, and that BDD's and FDD's are each a specal case of KDD's. It follows that when we realze a gven functon by -nput LUT's, a method based on a PKDD requres the fewest LUT's. Fg..8 s a realzaton of the functon n Table.1 by -nput LUT's. In ths case, we used only the hannon expanson for each LUT. However, n general, we can use any one of the three expansons to reduce the number of LUT's. Dentons and Basc Propertes We assume that functons to be realzed have n =r nputs. Let X =(x1;x; 111;x n ) be the nput varables, where x ( =1; ;::;n)takes on two values. Denton.1 Let Q = f0; 1; ; g and B = f0; 1g. f: Q r! B s a four-valued nput two-valued output functon. An arbtrary logc functon of n varables f(x) can be converted nto a four-valued nput two-valued output functon as follows: f(x1;x; 111;X r ) = f(x), where X = (x01;x) takes ether 0,1,, or (x01;x) = (0,0), (0,1), (1,0), or (1,1), respectvely. Example.1 The logc functon shown n Table.1 can be converted nto the four-valued nput two-valued output functon n Table., where X1 =(x1;x) and X =(x;x). From now on, a four-valued nput two-valued output functon wll be smply called a functon, and an ordnary two-valued nput functon wll be called a twovalued nput functon. Denton. Let Q. X s a lteral of X, where X = 0 f X= 1 f X : When contans only one element, X fg s denoted by X. A product of lterals X 1 1 X 111Xn n s a product term that s the AND of the lterals X1 1 ;X ; 111; and X n n.asumofproducts _ ( 1; ;111; n) X1 1 X 111Xn n

4 x f = x 1. f 0 x 1. x 1 f 0 Lemma. f s unquely represented as f = _ (a 1 ;a ;111;a n ) f(a 1;a; 111;a n )X a 1 1 Xa 111Xa n n ; where _(a 1 ;a ;111;a n ) s the nclusve-or for all the combnatons such that a Q, and f(a1;a; 111;a n )=0 or =1. f can be also unquely represented by an expresson: x x f 00 f f 000 f Fgure.8: Realzaton of the functon n Table.1 Table.1: x1 x x x f Table.: X1 X f s a sum-of-products expresson (OP), where _( 1 ; ;111; n ) denotes the nclusve-or of product terms. If the nclusve-or s replaced by exclusve-or, the result s an exclusve-or of products X 8 X 1 1 X 111X n n ; ( 1; ;111; n) whch s called an exclusve-or sum-of-products expresson (EOP). Lemma.1 An arbtrary r-varable functon can be expanded as f(x1;x; 111;X r )=X 0 1 f(0;x; 111;X r ) _X 1 1 f(1;x; 111;X r ) _ X 1 f(;x; 111;X r ) _X 1 f(;x ; 111X r ): (.1) Ths s the hannon expanson wth respect to X1. X f = 8 f(a1;a; 111;a n )X1 a1 Xa 111Xan n ; (a 1 ;a ;111;a n ) P where 8 (a1 ;a ;111;a n ) represents the exclusve-or for all the combnatons of a Q. Desgn of FPGA's Usng the hannon Expanson Frst, we wllshow a nave method to desgn LUT networks, where each LUT has sx nputs. We can realze a functon f by usng the hannon expanson, f(x1;x;x;x) =X 0 1 f 0_X 1 1 _X 1 f _X 1 f : (:1) Fg..1 shows a realzaton of the expanson n (.1). It conssts of one LUT that drves the output (called the output LUT) and four other LUT's, each realzng f. It s convenent tovewthetwo bnary control nputs as a sngle four-valued nput. In ths example, the control nput of the output LUT s drven by X1, whle X drves the control nputs of the other four LUT's. Fg..1 shows that some combnaton of X and X drves the prmary nputs of these four LUT's. The followng observatons wll reduce the number of LUT's: 1. If f ( =0; 1; ; or ) s a constant functon, then the correspondng LUT's are not needed. That s, no specal hardware s necessary for the constants.. If f = f j ( = j), then one LUT can be used for both f and f j. The dagram correspondng to the LUT network s called a QDD (Quarternary Decson Dagram). We can desgn an LUT network usng an algorthm that s smlar to that used for Bnary Decson Dagrams (BDD's): If two sub-functons are the same, realze only one sub-functon. If a sub-functon nvolves or fewer varables, stop (t s realzed by a sngle LUT). Example.1 Let f be the followng functon: f(x1;x;x;x) =X 0 1(X 8 X ) _ X 1 1(X 8 X ) _X 1(X 8 X ) _ X 1 X ; where 8 s the modulo sum: If f s represented n the form (.1), we have f0 = X 8X ; = X 8X ;f = X 8X ;f = X : In ths case, all the sub-functons are non-constant and dstnct. Fg..1 shows a realzaton for f.

5 X X X X X X f 0 f f X 1 Fgure.1: Realzaton of a logc functon by the hannon expanson 1 1 x x 5 1 x x 5 1 x x 1 1 f x x 1 Fgure.: Network structure for k = 5 Enumeraton of LUT's to Realze Gven Functons. Here, we consder the queston of how manylut's are requred n the realzaton of a gven functon. Theorem 5.1 Let f be an arbtrary r-varable fourvalued nput two-valued output functon. When r, f can be realzed by a sngle LUT wth sx two-valued nputs. When r, f can be realzed wth at most r0 01 LUT's. (Proof) Because an LUT realzes any functon wth nputs, a sngle LUT s sucent. Any r-varable functon, where r can be realzed by an LUT tree structure of the type shown n Fg.., where one four-valued varable s appled at each level, except the f leftmost level, where three varables are appled. The number of LUT's requred s at most r0 = r0 0 1 : Q.E.D. The above theorem gves an upper bound. However, n many cases, gven functons can be realzed wth fewer LUT's. Theorem 5. Gven a functon f(x1;x; 111;X r ), let be the number of dstnct functons of the form f(a1;a; 111;a r0;x r0;x r01;x r ), where a Q, = 1; ; 111;r0. Then,f can be realzed wth at most r0 0 1 (Proof) f can be expanded as f(x1;x; 111;X r )= + LUT's: _ X1 a1 Xa 111Xa r0 r0 f(a 1;a; 111;a r0;x r0;x r01;x r ); where a Q; =1; ; 111;r0 : We can realze a selector crcut that selects one out of r0 nputs by usng r0 01 LUT's. Because there are dstnct functons of the form f(a1;a; 111;a r0;x r0;x r01;x r ), we need to realze only such functons. Q.E.D. A Desgn Method Usng the Pseudo- Kronecker Expanson. The desgn method usng the hannon expanson s smple, but requres many LUT's. Ths s because each LUT s only used as a multplexer, whle t can realze any of derent functons. To reduce the number of LUT's, we can use the theory of pseudo-kronecker expansons, whch was developed for the optmzaton of EOPs wth four-valued nputs [, ]. Denton.1 Let be a set of logc values, where Q. The characterstc vector of s a = (0;1;;), where j s a logc value such that = 0 f = 1 f : Denton. A matrx M M = a 0 a 1 a a of characterstc vectors a s non-sngular f there exsts a unque matrx M 01 such that MM 01 = = I; 0001 where multplcaton s AND and addton s exclusve- OR.

6 If one expands a gven functon f: Q r! B about varable X usng the hannon decomposton, f = X 0 f0 8 X 1 f1 8 X f 8 X f; then f0, f1, f, and f are unque. The next theorem [] shows that for certan other forms of X, the subfunctons are also unque. The same theorem can be also found n [19] and []. Theorem.1 (Expanson Theorem) An arbtrary functon f : Q r! B can be expanded wthrespect to a varable X as f = X 0 h0 8 X 1 h1 8 X h 8 X h; (:1) where h0, h1, h, andh are unque f and only f M s non-sngular, where M = a 0 a 1 a a 7 5,and a ( =0; 1; ; ) are the characterstc vectors of : (Proof) By (.1), we have f = X 0 h0 8 X 1 h1 8 X h 8 X h: (:) On the other hand, by the hannon expanson of f, we have f = X 0 f0 8 X 1 f1 8 X f 8 X f: Let I be the unt matrx. nce the two expansons above represent the same functon, [h0;h1;h;h]m =[f0;f1;f;f]i: (f) When M s non-sngular, the nverse matrx M 01 exsts, and the functon can be unquely represented wth [h0;h1;h;h] =[f0;f1;f;f]m 01 : (only f) When M s sngular, [h0;h1;h;h] cannot be unquely represented. Q.E.D. Corollary.1 Let A, B, C, D, A 0, B 0, C 0 and D 0 be subsets of Q = f0; 1; ; g, and let a, b, c, d, a 0, b 0, c 0 and d 0,respectvely, be the characterstc vectors for them. Let M = R = [a 0t ; b 0 t ; c 0t ; d 0t ], and MR = I (unt matrx). Then, an arbtrary four-valued nput two-valued output functon f can be unquely represented n the forms f = X f0g f f0g 8 X f1g f f1g 8 X fg f fg 8 X fg f fg or a b c d 7 5 ; = X A f A 0 8 X B f B 0 8 X C f C 0 8 X D f D 0; where f A 0 = X A 0 8f fg ;f B 0 = X B 0 8f fg ;f C 0 = X C 0 8f fg ;f D 0 = X D 0 8f fg : Example.1 Consder the four-valued nput twovalued output functon f n Table.. By the hannon expanson, t can be represented as f = X f0g f f0g 8 X f1g f f1g 8 X fg f fg 8 X fg f fg: Let us consder the expanson of the form f = X A f A 0 8 X B f B 0 8 X C f C 0 8 X D f D 0. In ths case, the subfunctons obtaned by EXORng sub-functons are as follows: f f0g = X f0;g ;f f1g = X f0;g ; f fg = X f1;g ;f fg = X f0;1g ; f f0;1g = X f;g ;f f0;g = X f0;1g ;f f0;g = X f1;g ; f f1;g = X f0;1;;g ;f f1;g = X f1;g ;f f;g = X f0;g ; f f1;;g = X f;g ;f f0;;g =0; f f0;1;g = X f0;1;;g ;f f0;1;g = X f1;g ; f f0;1;;g = X f0;g : The number of products needed torepresent the above sub-functons are 0 for f f0g, and 1 for the others. The characterstc vectors for the four sub-functons f f0g, f f1g, f fg and f fg are (1011), (0100), (0010), and (0001), respectvely. Note that these vectors are lnearly ndependent of each other. Hence, f can be unquely represented by these four sub-functons. Because R = f can be represented as and M = R 01 = 1001 f = X A 1 f A 0 8 XB 1 f B 0 8 XC 1 f C 0 8 X D 1 f D 0; ; 1001 = X f0g 1 f f0;;g 8 X f1g 1 f f1g 8 X f0;g 1 f fg 8 X f0;g 1 f fg; = X f1g 1 X f0;g 8 X f0;g 1 X f1;g 8 X f0;g 1 X f0;1g : Note that ths expanson has only three product terms. (End of Example) A computer enumeraton shows that, out of the ( ) = 1 possble matrces, 010 are nonsngular []. If we gnore the labelng of logc values for one of the varables, there are essentally 010! = 80 derent expansons, of whch the hannon expanson s one. Ths leads to the queston of whch expanson reduces the complexty ofthenetwork. We can select an expanson that reduces the complexty ofthenet- work. Denton. Pseudo-Kronecker decson dagrams (PKDD's) of n-varable four-valued nput twovalued output functons are dened recursvely as follows:

7 1) A PKDD s a termnal node v labeled by value(v), where value(v) f0; 1g. ) A PKDD s a non-termnal node v that has four chldren, h0(v), h1(v), h(v), and h(v), that are also PKDD's, where v s labeled by (a) ndex(v), where ndex(v) f1; ; 111;rg, and by (b) a regular matrx M, where M s dened n (.). The correspondence between a PKDD and a Boolean functon s dened as follows: APKDDG havng a root node v denotes a functon f v dened recursvely as: ) If v s a termnal node: (a) If value(v) =1,thenf v =1. (b) If value(v) =0,thenf v =0. ) If v s a nontermnal node wth ndex(v) =, then f v s a functon X 0 such that f h0 (v) 8 X 1 M = a 0 a 1 a a f h1 (v) 8 X 7 5 s non-sngular, f h (v) 8 X f h (v), where a s a characterstc vector for ( =0; 1; ; ). X s called thedecson varable for node v. Denton. A reduced ordered PKDD s a PKDD such that: 1) In Denton., for any non-termnal node v, f h (v) s also nontermnal, then ndex(v) <ndex(h (v)). ) No two subgraphs n the PKDD are dentcal. The PKDD for f s sad to be mnmum f t contans the least number of nodes. It s very dcult to obtan an exact mnmum PKDD, so we wll consder a heurstc method whch obtans a good soluton quckly. In ths case, we have to consder the followng 15 sub-functons: f f0g; f f1g; f fg; f fg; f f01g = f f0g 8 f f1g; f f0g = f f0g 8 f fg; f f0g = f f0g 8 f fg; f f1g = f f1g 8 f fg; f f1g = f f1g 8 f fg ;f fg = f fg 8 f fg; f f01g = f f0g 8 f f1g 8 f fg; f f01g = f f0g 8 f f1g 8 f fg; f f0g = f f0g 8 f fg 8 f fg; f f1g = f f1g 8 f fg 8 f fg; f f01g = f f0g 8 f f1g 8 f fg 8 f fg: Algorthm.1 (Generaton of a PKDD : mple method) 0) For =1to r 0 do the followng: 1) Let f be the functon. Expand t n the form f = X 0 h0 8 X 1 h1 8 X h 8 X h that mnmzes the cost of the expanson, where X COT(f) = COT(h j ); and j=0 8 >< 0 f h j s constant 0 f h COT(h j )= j s already realzed k f h >: j s not realzed prevously : and depends on k varables ) Create the nodes for new functons f they do not exst. Record that they are realzed. ) Expand the remanng nodes n the same way. Example. Consder the -valued nput functon f n Example.1. f(x1;x;x;x) =X f0g 1 (X 8 X ) _ X f1g 1 (X 8 X ) _X1 fg (X 8 X ) _ X1 fg X : Ths expanson has four non-zero sub-functons. However, we can reduce the number of non-zero subfunctons by consderng an expanson wth the form f = X A 1 f A 0 8 X B 1 f B 0 8 X C 1 f C 0 8 X D 1 f D 0: To nd a good expanson, we calculate the costs for all the 15 sub-functons. f f0g = f f1;g = X 8 X ; cost =: f f1g = f f0;g = X 8 X ; cost =: f fg = f f0;1g = X 8 X ; cost =: f fg = f f0;1;;g = X ; cost =1: f f0;g = f f1;;g = X 8 X 8 X ; cost =: f f1;g = f f0;;g = X ; cost =1: f f;g = f f0;1;g = X ; cost =1: f f0;1;g =0 ;cost=0: Note that f A 0, f B 0, f C 0,andf D 0 have smaller costs, where A 0 = f; g, B 0 = f1; g, C 0 = fg, andd 0 = f0; 1; g. The characterstc vectors for A 0, B 0, C 0, and D 0 are: (0,0,1,1), (0,1,0,1), (0,0,0,1), and (1,1,1,0), and they are lnearly ndependent. Thus, we have R and M as follows: R = and M = R 01 = : 1000 Because A = f0; g, B = f0; 1g, C = f1; ; g, and D = f0g, f can be represented as f = X A 1 f A 0 8 XB 1 f B 0 8 XC 1 f C 0 8 X D 1 f D 0; = X f0;g 1 f f;g 8 X f0;1g 1 f f1;g 8 X f1;;g 1 f fg 8X f0g 1 f f0;1;g; = X f0;g 1 X fg 8 X f0;1g 1 X fg 8 X f1;;g 1 X fg :

8 Note that the last expanson contans only three nonzero subfunctons. (End of Example) 7 Expermental Results [9] 7.1 For -nput LUT's (-valued case) Table 7.1 compares the number of non-termnal nodes for BDD's, FDD's, KDD's, and PKDD's. For FDD's, the column headed wth "" denotes the case where only postve Davo expansons are used, and "both" denotes the case where both postve and negatve Davo expansons are used. For each dagram, we obtaned an orderng of nput varables that reduce the number of nodes. The orderngs of the nput varables are obtaned by a smulated annealng method smlar to [8]. Note that the orderngs that mnmze the sze of BDD's do not always mnmze the sze of FDD's, KDD's or PKDD's. Let sze(bdd), sze(fdd), sze(kdd) and sze(pkdd) be the numbers of non-termnal nodes for optmzed BDD, FDD, KDD and PKDD for a functon, respectvely. The expermental results show that sze(pkdd)sze(kdd)sze(bdd), sze(kdd)sze(fdd:both)sze(fdd:), sze(fdd:both)sze(fdd:nd). These results are consstent wth the relaton of decson dagrams n Fg..7. The bottom row of the Table 7.1 shows the relatve szes of the dagrams. On the average, PKDD's requre 9% fewer nodes than BDD's. However, the nodes for BDD's and FDD's are comparable. 7. For -nput LUT's (-valued case). The bt parng algorthm [] for PLA's wth decoders was used to produce four-valued nput twovalued output functons. Table 7.1 also compares the number of non-termnal nodes for QDDs (Quarternary Decson Dagrams) and -valued PKDD's. QDDs were obtaned by the -valued extenson of hannon Expanson n (.1). Detals of the optmzaton algorthm s shown n Appendx. On the average, QDDs requre 7% fewer nodes than BDD's, and -valued PKDD's requre 51% fewer nodes than BDD's. Also, -valued PKDD's requre % fewer nodes than QDDs. 8 Conclusons and Comments In FPGA desgn, nterconnectons are often more expensve than logc. FPGA's usng -nput LUT's requre many logcal levels and complex nterconnectons. On the other hand, FPGA's usng -nput LUT's requre fewer nterconnectons and fewer logcal levels. In ths paper, we showed a method to represent logc functons by usng pseudo-kronecker dagrams (PKDD's). Expermental results show that -valued PKDD's requre 9% fewer nodes than BDD's, and - valued PKDD's requre % fewer than QDDs, the - valued extenson of BDD's. Thus, ths method s useful for the desgn of FPGA's wth -nput LUT's. However, when LUT's have less than nputs, ths method s not applcable. In the practcal desgn of FPGA's, we can further reduce the number of LUT's as follows: 1) Use complement edges [15, 7]. Consder the decson dagrams where each edge can complement the sub-functon. Ths corresponds the fact that LUT's can complement the nputs wth no extra cost. In the case of -valued BDD's, complement edges can reduce the number of nodes by 0 to 50% [15]. ) Remove redundant LUT's. For a -nput LUT, f both of two sub-functons are constants, then t realzes a varable or ts complement. Thus, ths LUT can be removed, and the varable s used as the output. If an LUT depends on at most three varables, then t can be realzed wth one LUT. For a -nput LUT, f t depends on at most sx varables, then t can be realzed wth one LUT. ) Merge several LUT's nto one. For -nput LUT's, f any of the sub-functons s a constant, then the functon s realze by an LUT wth 5 or fewer nputs. In AT&T ORCA seres FPGA's, an LUT can be congured to realze ether a -nput functon, or a par of 5-nput functons, or four -nput functons. Thus, LUT's wth fewer nputs can be merged. Except for the -nput case, some of the nputs must be shared among the functons. We assumed that the FPGA's are all bnary, but the control nputs for LUT's can be four-valued nputs nstead of pars of bnary varables. Ths wll sgnfcantly reduce the connectons. Thus, ths method s also useful for a desgn of multple-valued LUT type FPGA's. [9] shows a method to realze a logc functon by usng multple-valued multplexers, where only crcuts wth tree type structure are generated. Also, nterconnectons are more complex, snce each level may have derent control varables. Acknowledgments Ths work was supported n part by a Grant n Ad for centc Research of the Mnstry of Educaton, cence and Culture of Japan, and the Naval Research Laboratory, Washngton, DC through drect funds at the Naval Postgraduate chool, Monterey, CA U..A. M. Matsuura, K. Hara, and Y. Yamashta developed software and dd experment. Appendx Algorthm 8.1 (-valued PKDD mplcaton) 1. mplfy QDDs by permutng the nput varables (Algorthm 8.).. mplfy -valued KDD's by changng the method of expanson for each varable (Algorthm 8.).. mplfy -valued PKDD's by changng the method of expanson for each node (Algorthm 8.). Algorthm 8. (Optmzaton of nput orderng for QDDs).

9 Table 7.1: Number of nodes n Decson Dagrams functon n out BDD FDD KDD PKDD -valued both QDD PKDD 9sym add adr alu apla bw clp co con dc dst dk dk duke f51m nc msex msj 5 1 mlp radd rd rd rd rsc rot sao sex sqr t tal ts xor z5xp total rato Let X1, X, 111, X r be the orgnal orderng for the QDD.. For =1to r 0 1 ffor j =to r exchange X wth X j, and count the number of nodes n QDD. Adopt the ones that mnmze the number of nodes g. Repeat. whle the number of nodes s reduced. Algorthm 8. (mplcaton of -valued KDD's). 1. Let X1, X, 111, X r be the orderng obtaned by Algorthm 8... Construct a PDD (Pentadecmal Decson Dagram) that has 15 chldren for each non-termnal node, where each chld corresponds to one o5 sub-functons.. Let QDD be the ntal -valued KDD.. For =1to r 0 1 Expand the sub-functons wth respect X n 80 derent ways, and nd one that mnmzes the number of nodes. 5. Repeat. whle the number of nodes s reduced. Algorthm 8. (mplcaton of -valued PKDD's). 1. Let X1, X, 111, X r be the orderng. Let the - valued KDD obtaned by Algorthm 8. be the ntal -valued PKDD.. For =1to r 0 1 For each node for X, expand the sub-functons n 80 derent ways, and nd ones that mnmzes the number of nodes.. Repeat. whle the number of nodes s reduced.

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