Galois Field Hardware Architectures for Network Coding

Transcription

1 Ashwarya Nagarajan Departent of Electrcal and Coputer Engneerng Unversty of Wsconsn-Madson Wsconsn, USA Galos Feld Hardware Archtectures for Network Codng Mchael J Schulte Departent of Electrcal and Coputer Engneerng Unversty of Wsconsn-Madson Wsconsn, USA schulte@engr.wsc.edu Paraeswaran Raanathan Departent of Electrcal and Coputer Engneerng Unversty of Wsconsn-Madson Wsconsn, USA paresh@engr.wsc.edu Abstract- Ths paper presents and analyzes novel hardware desgns for hgh-speed network codng. Our desgns provde effcent ethods to perfor Galos feld (GF) dot products and atrx nversons, whch are portant operatons n network codng. Encoder desgns that that perfor GF dot products and vary wth respect to the nuber of essages cobned, Galos feld sze, and nput essage sze are pleented and analyzed to evaluate desgn tradeoffs. We nvestgate sngle cycle, ult-cycle, and ppelned desgns wth and wthout feedback echanss for encodng ultple sets of essages. The decoder s pleented as a ult-cycle desgn and perfors GF atrx nverson followed by ultple GF dot products. Our desgns are syntheszed wth a 6n standard cell lbrary and copared n ters of area, clock perod and throughput. Desgns cobnng four essages acheve throughputs of ore than 3 Gbps. Our desgns can scale to acheve uch hgher throughput through the use of addtonal hardware. Keywords: Network codng, Content Dstrbuton Networks, Galos feld arthetc, Matrx nverson, Gauss- Jordan elnaton, Router desgns I. INTRODUCTION About ten years ago, Ahlswede et al. publshed a landark paper n whch they proposed a novel technque called network codng []. In a conventonal network, a router sply forwards ts ncong packets on approprate outgong lnks. In contrast, n network codng, a router lnearly cobnes a specfed nuber of ncong packets before forwardng the on the approprate outgong lnks. The recevers of such network coded packets recover the orgnal packets through a lnear decodng operaton on the approprate set of the cobned packets. Ahlswede et al. showed that, by usng ths technque, one can sgnfcantly ncrease the data rate achevable n a ultcast applcaton, where a sngle source node sends a strea of packets to ore than one recever. Snce the work by Ahlswede et al. [], hundreds of papers have shown that the basc dea of network codng can be extended to enhance perforance n both wred and wreless networks. For exaple, network codng can sgnfcantly reduce the delay of nforaton exchange n peer to peer networks [, 6]. Network codng can also prove the perforance of uncast councaton n wreless ad hoc networks [3] and can be used for avalable bandwdth estaton n overlay networks [7, 8]. Software pleentatons of network codng have been nvestgated for graphcs processng unts [8] and ult-core processors wth vector extensons []. Although these pleentatons are flexble, snce they are pleented usng prograable processors, they requre sgnfcant power and area, and do not acheve the Ggabt throughputs needed for hgh-speed routers. Despte the treendous prose of network codng, dedcated hardware pleentatons of network codng have not yet been nvestgated. Hardware pleentatons for network codng have the potental to allow network codng to occur at router lne speeds, wth uch greater perforance and energy effcency than software pleentatons. The an bottlenecks n network codng are Galos feld (GF) dot products durng network encodng and decodng, and GF atrx nverson durng network decodng. We focus on these two key operatons to accelerate network codng. Ths paper presents the desgn and evaluaton of dedcated hardware archtectures that perfor GF dot products and GF atrx nverson for network codng. It ncludes a detaled analyss of tradeoffs n area and perforance as the GF sze, nubers of essages cobned, and ethod for cobnng essages are vared. Our archtectures have been syntheszed usng the TSMC 6n standard cell lbrary. Our synthess results for a four essage network coder ndcate that throughputs of ore than 3 Gbps are achevable wth an area of roughly 2 µ 2 for encodng, and, µ 2 for decodng. Thus, the proposed hardware desgns have the potental to provde network codng capabltes n hgh-speed routers wth low area overhead. Furtherore, by utlzng addtonal parallel hardware, our desgns can scale to acheve uch hgher throughput. Novel contrbutons of ths paper nclude: The frst dedcated hardware archtectures for network codng Detaled area-perforance tradeoff analyss of GF dot product unts Novel dedcated hardware archtecture for GF atrx nverson, and Applcaton and tradeoff analyss of the

2 GF dot product and atrx nverson unts to hgh-speed network codng. Ths paper s organzed as follows. Secton II provdes background nforaton and dscusses related work on network codng and Galos feld arthetc. Secton III presents our novel archtectures for network encodng and decodng. Secton IV gves results fro our desgns and analyzes desgn tradeoffs. Secton V concludes the paper. II. BACKGROUND AND RELATED WORK A. Galos Feld Arthetc Galos Feld (GF) arthetc s a powerful algebrac tool, eployed n any codng technques, ncludng network codng and Reed-Soloon codng. A bref explanaton of key concepts and operatons n GF arthetc follows. Further detals appear n [6]. A GF(2 ) feld s an extenson of the feld GF(2), wth eleents {, }. The operatons defned n GF(2) are addton and ultplcaton, each perfored odulo 2. When GF(2) s extended to GF(2 ), the result s a vector feld of denson over GF(2). Eleents of GF(2 ) can thus be represented as -bt bnary words. The feld s characterzed by the rreducble polynoal, f(x), where f ( x) x f x... fx f, () wth f n GF(2). All 2 eleents n GF(2 ) can be represented by eans of the vector bass {α -,.., α, α }, where α s a root of the rreducble polynoal f(x) and s called a prtve eleent of the feld. Ths bass allows an eleent A n GF(2 ) to be expressed as A a... a a, (2) wth a n GF(2). Thus, eleents of GF(2 ) can be assocated wth polynoals that have coeffcents n GF(2), where the bt n the th poston represents the coeffcent of α. For exaple wth GF(2 4 ), the eleent () corresponds to α 3 + α 2 + α + α. Addton and ultplcaton n GF(2 ) can be vewed as polynoal addton and ultplcaton. Snce the polynoal s coeffcents belong to GF(2), operatons at the coeffcent level are taken odulo-2. Thus, addton n GF(2 ) s perfored by btwse XORng the coeffcents of the two polynoals beng added. Slarly, ultplcaton s coputed as the odulo-2 su of shfted partal products, where the su s coputed usng btwse XOR operatons. The result of a GF(2 ) ultplcaton s a (2-)-bt word that represents a degree (2-2) polynoal, n what s called extended for. To acheve closure, the extended for polynoal s reduced odulo f(x). Ths s equvalent to calculatng the reander fro the extended for polynoal dvded by f(x). Early desgns for GF ultplcaton used a seral approach [22]. Although seral GF ultplers have low hardware requreents, ther delay ncreases lnearly wth the sze of the nput operands. Consequently, several parallel desgns for GF ultplers have been developed, ncludng Mastrovto ultplers [9, 2], Systolc GF ultplers [2], parallel array GF ultplers [] and tree GF ultplers [4]. Gao and Parh nvestgate VLSI desgns for low latency and low power GF ultplers []. They present and dscuss the logc structure, crcut desgn and physcal appng of GF ultplers. Wth ther proposed archtectures and physcal appng, an rregular balanced parallel tree GF ultpler can be pleented as easly as a regular GF ultpler. The custo VLSI pleentatons of these ultplers over GF(2 8 ) show that the rregular GF tree ultpler has 3% less delay and 8% less power consupton than a regular GF ultpler. Gao and Parh also present an algorth to parallelze the polynoal reducton of the extended for polynoal []. We eploy ther algorth, called Parallel Polynoal Reducton (PPR), n our GF ultpler desgns to reduce the extended for polynoal odulo f(x). Garca and Schulte present the desgn of a cobned 6-bt bnary and dual Galos Feld ultpler, capable of perforng ether a 6-bt two s copleent or unsgned ultplcaton, or two ndependent 8-bt GF(2 8 ) ultplcatons n SIMD fashon [4]. The cobned ultpler s desgned by odfyng a conventonal bnary tree ultpler. It uses a novel wrng ethodology to provde two sultaneous GF(2 8 ) ultples wth a nor pact on area and delay. Csanky presents technques for fast atrx nversons, but does not exane atrx nverson over Galos felds [2]. Ltow and Davda ntroduce Boolean crcuts that nvert a sngle Galos feld eleent [3]. As descrbed n Secton III, our desgns use the Gauss-Jordan Elnaton ethod [7] to perfor GF atrx nverson and parallel technques to perfor GF dot products. They eploy hgh-speed optzed odules for ultplcaton n GF(2 ) to pleent GF atrx nverson and GF dot products. B. Network Codng In the dscusson that follows, all the vector eleents are ndcated n bold text. Lnear network codng usng a chosen GF, GF(2 ), s pleented as follows. A essage b, n can be vewed as a vector of k -bt blocks, b j, j k, where each b j belongs n GF(2 ). Gven n nput essages b, b 2,,b n lnearly cobned to obtan an encoded essage 2

3 n e c j.b j (3) j where each c j belongs n GF(2 ), and where the addton and ultplcaton are perfored over GF(2 ). The decodng proceeds when the node receves n lnearly ndependent encoded essages [e, e 2,., e n ] T. An n n coeffcent atrx C s fored, usng the coeffcents ncluded n each essage.. The orgnal essages [b, b 2,., b n ] T are obtaned as: T b,b,..., b C e,e,..., T (4) 2 n 2 en Thus, coputng the nverse of C s the frst step to obtan b j. C s only nvertble when t s full rank,.e., when ts rows are lnearly ndependent. The next step s the GF atrx-vector ultplcaton of C - and [e, e 2,., e n ] T, whch can be perfored usng n GF vector dot products. Shojana and L use off-the-shelf processors to accelerate network codng through ultthreaded processng and SIMD vector nstructons []. They later extend ther work by pleentng network codng wth coodty off-the-shelf any-core GPUs, usng a fraework that they call Nucle [8]. They show that a cobned CPU-GPU encodng approach acheves encodng rates of up to 6 MB/second. Ther desgn s orented towards eda streang servers, n whch hundreds of peers are served concurrently. Wth respect to decodng, Shojana and L recognze that owng to ts hgher coputatonal coplexty and lted opportunty for parallels, the perforance s poorer [8]. Decodng nvolves atrx nversons n the Galos feld, and decodng a partcular block cannot begn untl the prevous block s decoded, provded all the source blocks are lnearly ndependent. They utlze a software-based Gauss-Jordan Elnaton technque for atrx nverson that executes on the GPU. Ther decodng occurs progressvely, wheren each coded block along wth ts assocated coeffcents s decoded partally. They also consder the scenaro where the n coded blocks are buffered and then decoded. Unlke prevous work on network codng, our approach uses dedcated hardware, rather than software runnng on CPUs or GPUs. Our desgns are scalable wth respect to sze of the Galos feld and the nuber of nput essages used to for the fnal encoded essage. -bt blocks of the n nput essages. The decodng output s n k-bt essages, where each -bt block n an output essage s the network decodng of the correspondng - bt blocks of the n nput essages. The overall Encoder and Decoder Archtectures are llustrated n Fgures and 2, respectvely. In the rest of ths secton, we focus on the hardware to copute one of the -bt blocks n the output encoded essage and the n -bt blocks n the output decoded essages. Message b e x k x 2 x Encodng Matrx C nxn b k b 2 b Message b j b jk b j2 b j c c j c n ENCODING HARDWARE x k x 2 x Encoded Message e Fgure : Overall Encoder Archtecture e j x k x 2 x DECODING HARDWARE e n x k x 2 x Message b n b nk b n2 b n Encoded Messages III. DESIGN b k b jk b nk In the dscusson to follow, n s the nuber of essages beng encoded or decoded and s the sze of the Galos Feld. Each essage s assued to be of sze L = k bts for soe postve nteger k. The encodng output s a sngle k-bt essage, where each -bt block of the output s a network encodng of the correspondng b 2 b b b j2 b n2 b j b n b j b n Fgure 2: Overall Decoder Archtecture Decoded Messages 3

4 Our encoder and decoder archtectures are desgned prarly for network routers, but they should also be useful n perforng hgh-speed network codng n other types of systes, such as eda servers. A. Encoder Archtecture Fgure 3 shows a block dagra of our network encoder, whch coputes GF dot products, as specfed n Equaton (3). A sngle GF dot product unt takes one - bt block fro each essage, ultples the wth correspondng GF coeffcent and then sus the usng a XOR tree. The output s one block of the encoded essage. If ore than n essages need to be cobned, the network encoder can be expanded to nclude addtonal GF ultply-reduce unts and XOR operatons. Alternatvely, a feedback regster can be added and ultple passes through the network encoder can be used to copute a larger dot product. Wth the feedback approach, coputng the dot product of n pars of vector eleents wth p ultply-reduce unts and a (p+)-nput XOR tree takes n/p teratons. The optonal feedback regster and feedback path are ndcated wth dashed lnes n Fgure. To encode one k -bt essage, k dot products are perfored over GF(2 ). To prove the throughput of the encoder, ultple dot product unts can be used to copute ultple essage blocks n parallel. b c b j c j Multply- Reduce Unt Multply- Reduce Unt b n c n Multply- Reduce Unt the extended polynoal P(α) can be separated nto two parts, such that: 22 P( ) p p, () PPR uses Equaton (2) and the followng dentty (6) A ( ) j j a, j, 2 2 where A (α) s the canoncal representaton of the su of the feld eleents α that appear n the frst suaton n Equaton (). A (α) can be added wth the second suaton n Equaton (), whch represents one feld eleent n canoncal for, to produce the fnal result. As an exaple wth = 4, suppose f(x) = x 4 +x+ () and the extended for polynoal s P(α) = x 6 +x +x 2 + = (). For ths f(x), α 4 = (); α = (); α 6 = (). The fnal result after odulo reducton, for P(α) = (), s coputed usng GF addton as α 6 + α + α 4 + () = () Snce the rreducble polynoal s known, our desgn (llustrated n Fgure 4) utlzes pre-coputed values for α, for 2-2, and perfors the polynoal reducton n a tree wth logarthc delay usng the technque by Gao and Parh []. The reducton unt requres (-) AND gates to deterne the eleents of the frst suaton and (-)-bt XOR gates to copute the reduced polynoal usng a tree structure usng the followng equaton. P( ) 22 p p XOR Suaton Tree Feedback Regster (optonal) p p X p X p 2 2 X 22 x Fgure 3: Block Dagra of the Galos Feld Dot Product Unt Each GF(2 ) ultpler takes n an -bt block b j fro a essage queue, ultples t wth an arbtrary - bt coeffcent c j and produces a (2 - )-bt extended for polynoal. Our GF(2 ) ultpler utlzes the equvalent of 2 parallel AND gates to generate -bt partal products, followed by a tree of ( ) XOR gates to su the partal products usng GF addton. After GF ultplcaton, the PPR technque descrbed below s used to reduce the (2 - )-bt extended for polynoal and produce a fnal -bt product. In PPR [], XOR Suaton Tree Reduced Polynoal P(α) Fgure 4: Block Dagra of the Reducton Unt In Fgure 3, the dot product unt frst perfors n ultply-reduce operatons n GF(2 ) and then XOR sus the reduced products to produce x j. An alternatve approach, whch produces the sae results, s to frst perfor n ultply operatons wthout reducton n GF(2 ), then XOR su the n extended for polynoals, 4

5 and fnally perfor one polynoal reducton of the result to produce x j. Although the second approach requres n x (2-)-bt extended products to be added n the XOR tree, t only requres a sngle reducton unt. We evaluate both types of GF dot product desgns n Secton IV. B. Decoder Archtecture Network decodng, whch nvolves GF atrx nverson followed by GF atrx-vector ultplcaton to pleent Equaton (4), has hgher coputatonal coplexty than network encodng. The atrx-vector ultplcaton of an n x n atrx wth an n-eleent vector requres n dot product operatons. Once the atrx nverson has been perfored, the nverse atrx can then be used to decode blocks fro all essages that were encoded usng those coeffcents. Ths s depcted n Fgure a. In real systes, the GF atrx nverson can occur ore slowly than the GF dot product, snce the results of one atrx nverson s used to decode n k-bt essages, whch requres nk dot product operatons. Our network decoder desgn utlzes Gauss-Jordan Elnaton to perfor atrx nverson wth atrx eleents n GF(2 ). Gauss Jordan Elnaton [6, 7] s a wdely used technque for fndng the nverse of a square atrx. The square atrx s augented wth the dentty atrx of the sae densons. Eleentary row operatons are then perfored on the augented atrx untl t reaches reduced row echelon for, fro whch the nverse atrx can be obtaned, as per the followng equaton: CI => C CI => [IC ], (7) where C s the orgnal atrx, C - ts nverse, and I s the dentty atrx. Eleentary row operatons nclude cobnatons of pvotng, ultplcaton, and addton on the rows and coluns of a atrx, such that they change the atrx age but not ts kernel,.e, the soluton set of the syste of lnear equatons represented by the atrx. A atrx s n reduced row echelon for f All nonzero rows (rows wth at least one nonzero eleent) are above any rows of all zeros. The pvotng eleent (the frst nonzero nuber fro the left) of a nonzero row s always strctly to the rght of the leadng coeffcent of the row above t. Every leadng coeffcent s and s the only nonzero entry n ts colun. Further detals are found n [7]. The atrx nverson odule, shown n Fgure b, takes n the atrx of coeffcents used n the encodng process, C, and obtans C - n GF(2 ) usng Gauss-Jordan elnaton. The regster fle stores the augented atrx eleents. Each cycle, one atrx eleent s suppled as an nput to a ultply-reduce unt. The other nput to t can ether be a value fro the regster fle, or the ultplcatve nverse value of an eleent fro the regster fle. Ths s deterned by the control FSM usng the sgnal nverse_sel = ((cycle % n) == ), where cycle s the cycle count startng fro. The control FSM also deternes whch nputs fro the regster fle ust be used n a cycle by coputng the approprate ndexes. Once the ultply-reduce unts coputes ther results, these are suppled to the XOR gates. The second nputs to the XOR gates are also suppled fro the regster fle, whch also stores the result of the XOR. C Control FSM Matrx Inverson Module C - e e 2 e n Dot Product Unt Dot Product Unt 2 Dot Product Unt n Fgure a: Block Dagra of the Decoder Unt Index to Regster Fle (2n+) x (log 2 (n)+) n x 2n Regster Fle Stores augented atrx of coeffcents Table of nverse values n GF (2^) nverse_sel = ((Cycle % n) == ).n.n Multply Reduce Unts Fgure b: Block Dagra of the Matrx Inverson Unt b b 2 b n XOR gates We have desgned an n x n atrx nverter that takes n 2 clock cycles to nvert the atrx. It uses n ultplyreduce unts and n XOR gates. In clock cycle, the atrx nverter deternes the GF ultplcatve nverse of the pvotng eleent of row (typcally the dagonal eleent) va a table lookup. It then uses the n ultplyreduce unts descrbed earler to ultply the eleents of row wth the nverse of the pvot eleent, and obtan a new pvot row wth a n the pvot poston. In the subsequent (n - ) clock cycles, t processes the (n - ) other rows to get a n the postons above and below the pvot postons. Ths s accoplshed by ultplyng the eleent above/below the pvot eleent wth each eleent of the pvot row and then XORng each of these wth the correspondng eleent of the row beng processed. Fgure.n

6 6 shows the ultply-reduce unts and XOR gates that process each row. Based on the nverse_sel sgnal, ether the nverse of the pvot eleent or a value fro the regster fle s suppled to the ultply reduce unt. The other nput to the ultply-reduce unts s also suppled by the regster fle. The output of ths s suppled to the XOR gates. The other nput to the XOR gates also coes fro the regster fle, and the result s wrtten back to t. Ths procedure s repeated every n clock cycles wth the next pvot row and pvot poston. Durng these clock cycles, the control FSM checks f the pvot eleent s a, whch ndcates that a new pvot eleent ust be selected. In such a case, the pvot eleents of the subsequent rows are checked n parallel and the frst row found wth a nonzero pvot eleent s swapped wth ths row. If no such row can be found, the atrx s deeed non-nvertble and a flag s rased. We have desgned a atrx nverter that decodes n = 4 source essages encodng n GF(2 8 ),.e., = 8. We eploy four ultply-reduce odules and 32 2-nput XOR gates n ths odule. We can odfy the baselne desgn for saller area but wth a larger latency by reusng the sae ultply-reduce unts over ore clock cycles and processng dfferent portons of a row n each clock cycle. In order to use p ultply-reduce unts and p XOR gates to process a n x n atrx, where n > p, the desgn can process p eleents of a row n each clock cycle, and requre n/p clock cycles to process a row, and n 3 /p clock cycles to nvert the entre atrx. Alternatvely, a larger GF atrx nverson unt that takes fewer clock cycles than the baselne to nvert the atrx can be eployed. Ths approach utlzes p ultply-reduce unts and p XOR gates to process a n x n atrx, where p > n. It takes clock cycle to process p/n rows and n 3 /p clock cycles to nvert the entre atrx. c c j Multply- Reduce Unt c c c c j cj cj XOR Multply- Reduce Unt XOR ' ' c j c j c c jn Multply- Reduce Unt XOR ' c jn Fg. 6: Structure of the Man Datapath of the Matrx Inverson Module c j c n Once the nverted coeffcent atrx, C -, s obtaned, the desgn decodes the source essages by ultplyng the nverse atrx and the encoded essages over the chosen rreducble polynoal, as per Equaton (4), wth n GF dot product operatons. These GF dot products can be coputed usng the sae hardware that s used for encodng and s shown n Fgure 3. IV. RESULTS AND ANALYSIS To evaluate our network codng archtectures, we developed paraeterzed Verlog odules for GF dot products and atrx nverson unts. Our desgns were syntheszed usng Synopsys Desgn Copler and the TM 6n standard cell lbrary for an operatng voltage of. Volt and a teperature of 2 degrees Celsus. Input and Output delays were set to % of the clock perod. We optze our desgns for delay and drect the synthess tool to flatten (.e., the desgns are ungrouped and the desgn herarchy s reove to prove area and delay). We present results for area (n µ 2 ), clock perod (n ns) and throughput (n ggabts per second). The throughput for the encoders s calculated as the nuber of bts output per second, whch s calculates as throughput = /crtcal path delay. A. Galos Feld Dot Product Unts For our baselne desgns, we consdered hardware archtectures for a network router that encodes and decodes up to four essages, wth arbtrary coeffcents and a fxed, rreducble polynoal n GF(2 8 ). Thus, n our baselne desgn n = 4 and = 8. Fgures 7 through 9 show the area, clock perod and throughput respectvely for our baselne GF dot product unt. These fgures use the abbrevatons for Sngle Cycle, for Ppelned, RU for Reducton Unt, and OR for optze_regsters perfored n synthess. The optze_regsters coand n Synopsys Desgn Copler attepts to balance the delay between ppelne regsters at the expense of addtonal area. Our ppelned desgns take three cycles to produce the frst result. In GF dot product unts wth ultple GF reducton unts, the ppelne regsters are placed between the ultplcaton and reducton stages, and between the reducton stage and the XOR suaton tree. In GF dot product unts wth a sngle GF reducton, they are placed between the ultplcaton stage and the XOR suaton tree, and between the XOR suaton tree and the reducton stage. As shown n Fgures 7 to 9, ppelned desgns have a shorter clock perod and hgher throughput than nonppelned desgns, but have uch hgher area due to ppelne regsters. Utlzng the optze_regsters opton further proves the clock perod and throughput, but ncreases area copared to ppelned desgns that do not use ths opton. Wth our baselne desgn, a ppelned GF dot product unt that encodes four essages and utlzes optze_regsters has an area of roughly 2 2, a crtcal path delay of.26 ns, and a throughput of over 3 Gbps. In coparson, a 32-bt by 32-bt parallel ultpler 6

7 Area(µ 2 ) Crtcal Path Delay (ns) Area(µ 2 ) Throughput (Gbps) pleented n the sae technology and under the sae operatng condtons has an area of roughly and a crtcal path delay of.4 ns. The desgns wth a sngle reducton unt acheve slar or better crtcal path delays than ther counterpart desgns wth four reducton unts and also requre less areas. For ppelned desgns, encoders syntheszed wth optze_regsters acheve uch better throughputs than desgns syntheszed wthout optzed_regsters (3.77Gbps vs Gbps). Hence, for the subsequent results, we synthesze our desgns wth a sngle reducton unt, and the ppelned desgns use the optze_regsters feature. 2 2 Fg. 7: Coparson of areas for our baselne GF dot product unt (4 RU) (4 RU) ( RU) ( RU) (4 RU) (4 RU) ( RU) ( RU) (OR, RU) (OR, RU) Fg. 8: Coparson of crtcal path delays for our baselne GF dot product unt , RU, RU, OR Fg. 9: Coparson of throughputs for our baselne GF dot product unt We also nvestgated the pact of varyng the Galos feld sze,, on area, delay, and throughput, whle keepng the nuber of essages cobned the sae,.e., n = 4. As dscussed earler, n these desgns, a sngle reducton unt s used and optze-regsters s enabled for ppelned desgns. As shown n Fgure, the area of the GF dot product unts ncreases quadratcally as ncreases.. Fgure shows that for Sngle Cycle desgns, the crtcal path delay ncreases by a factor of around. when s doubled. For ppelned desgns, doublng has lttle pact on the crtcal path delay. Ths s because for values of fro 2 to 8 there are only a few gates on the crtcal delay path. As shown n Fgure 2, when s ncreented by, throughputs ncrease by roughly a factor of.2 for Sngle Cycle desgns and by roughly a factor of 2 for Ppelned desgns. However, despte havng saller area and crtcal path delays, saller felds ake t ore probable that the set of coeffcents correspondng to the set of receved encoded essages are lnearly dependent, preventng recovery of the orgnal essages [23]. 2 2 (=2) (=4) (=8) (=2) (=4) (=8) Fg. : Areas for GF dot product unts wth varyng 7

8 Throughput (Gbps) Throughput (Gbps) Crtcal Path Delay (ns) Crtcal Path Delay (ns) Area(µ 2 ) (=2) (=4) (=8) (=2) (=4) (=8) Fg. : Crtcal path delays for GF dot product unts wth varyng Fg. 3: Areas for GF dot product unts wth varyng n (=2) (=4) (=8) (=2) (=4) Fg. 2: Throughputs for GF dot product unts wth varyng (=8) To nvestgate the scalablty of our GF dot product unts, we deterned the pact on area, delay, and throughput of varyng the nuber of essages cobned, n, whle keepng the sze of the Galos Feld the sae,.e., = 8. We have pleented desgns wth n = 2, 4, 8 and 6. As dscussed earler, n these desgns, a sngle reducton unt s used and optze-regsters s enabled for ppelned desgns. Fgure 3 shows that area ncreases lnearly wth n for Sngle Cycle desgns and Ppelned desgns. As shown n Fgure 4, the crtcal path delays for both Sngle cycle and Ppelned desgns ncreases logarthcally wth n. As can be seen n Fgure, throughputs decrease as n ncreases, due to the ncrease n the crtcal path delay. The Ppelned desgns have hgher throughputs than the correspondng Sngle Cycle desgns. However, as n ncreases, ore essages can be cobned, whch can be used to prove network bandwdth. Fg. 4: Crtcal path delays for GF dot product unts wth varyng n Fg. : Throughputs for GF dot product unts wth varyng n We also copared the area and throughput of ppelned and sngle-cycle desgns wth and wthout feedback. As dscussed n Secton III.B, desgns wth feedback desgns utlze a feedback regster, p GF ultplers, a (p+)-nput XOR suaton tree, and n/p passes through the dot product unt to cobne n sybols fro n essages (one sybol per essage). 8

9 Throughput (Gbps) Throughput (Gbps) The results for sngle cycle and ppelned desgns are suarzed n Fgures 6 and 7, respectvely, where we plot the throughput of the desgns wth respect to the ther area for = 8 and varyng values of n and p. The top left porton of the chart corresponds to hgh throughput and low area. 2 2 p = 8 p = 8 p = 6 Fg. 6: Throughput vs. area for sngle cycle desgns wth and wthout feedback Area (µ 2 ) n=6 n=8 n=4 p = 8 p = 8 p = Area (µ 2 ) n=6 n=8 n=4 Fg. 7: Throughput vs area for ppelned desgns wth and wthout feedback These plots ndcate that, n general, Ppelned desgns acheve better throughputs than ther counterpart Sngle cycled desgns at the cost of larger area. For a gven value of n, ncreasng p ncreases both throughput and area. Lnes wth steep slopes ndcate stuatons n whch a relatvely sall ncrease n area yelds a large ncrease n throughput. Snce saller values of n have steeper lnes, ths ndcates that they acheve a larger ncrease n throughput for a gven aount of area, than desgns wth larger values of n. B. Galos Feld Matrx Inverson Unts Our GF atrx nverson unts use ultple cycles to perfor atrx nverson wth less area than a fully parallel pleentaton. For our baselne desgn wth = 8 and n = 4, the GF atrx nverson unt uses four ultply-reduce unts and 32 XOR gates over 6 clock cycles to generate the nverted atrx, ncludng perforng checks for lnear ndependence. The GF atrx nverson unt operates at a clock speed of.4ns and occupes an area of,4 cell unts. It takes 7.2ns to produce a vald result for a 4 x 4 atrx. The larger area for ths unt s due to the presence of a 32-entry by 8-bt regster fle for storng the augented atrx of coeffcents, as well as the state regsters for a 6-state FSM used for the nverson. To obtan the source essages followng the atrx nverson, the GF dot product unts are utlzes repeatedly to perfor GF atrx-vector ultplcaton. V. CONCLUSIONS Hgh-speed network codng has the potental to provde sgnfcant benefts to future networkng systes. We have presented and analyzed archtectures for network codng that pleent the portant operatons of GF dot products and GF atrx nverson. We have also nvestgated tradeoffs due to varatons n the encoder desgn. To acheve faster encodng and decodng, ultple odules ay operate n parallel, whch results n an ncrease n area. To obtan saller desgns, we can reuse odules over ultple clock cycles. The feedback echans for GF dot products n partcularly useful n that t provdes the ablty to vary the nuber of essages encoded at a fxed hardware cost. Consderng the nor area overheads and the coparable throughputs acheved, t would be benefcal to ncorporate these desgns n routers, content dstrbuton servers and other applcatons to provde the bandwdth and transsson effcency of network codng. REFERENCES [] R. Ahlswede, N. Ca, S.-Y. R. L, and R. W. Yueng, Network nforaton flow, IEEE Transactons on Inforaton Theory, vol. 46, no. 4, pp , July 2. [2] C.Fragoul, J. L. Boudec, and J. Wder, Network codng: an nstant prer, SIGCOMM Coputer Councatons Revew, vol. 36, no., pp , 26. [3] S. Katt, H. Rahul, W. Hu, D. Katab, M. Medard, and J. Crowcroft, XORs n the ar: practcal wreless network codng, n Proc of the ACM SIGCOMM, pp , Septeber 26. [4] J. Garca and M. J. Schulte, A Cobned 6-bt Bnary and Dual Galos Feld Multpler, n Proc. of 9

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