Backstepping Control of the Doubly Fed Induction Generator using Xilinx System Generator for Implementation on FPGA

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1 Backstepping Contol of the Doubly Fed Induction Geneato using Xilinx Syste Geneato fo Ipleentation on FPGA Maouane El Azzaoui, Hassane Mahoudi, Chafik Ed-dahani 3,,3 Electonics Powe and Contol Tea, Depatent of Electical Engineeing, Mohaadia School of Enginees, Mohaed V Univesity, Rabat, Moocco. Eail : aouane.elazzaoui@eseach.ei.ac.a, ahoudi@ei.ac.a, 3 chafik.eddahani@eseach.ei.ac.a Abstact This pape pesents how to geneate the VHDL code of the backstepping contol equied fo pogaing an FPGA without knowledge of VHDL pogaing. This contol stategy will be developed by the Xilinx Syste Geneato (XSG) tool integated in atlab/siulink envionent. The ipotance of this technique is to enjoy the benefits of Siulink and XSG. The fist siulates the poposed contol algoith and the second geneates the VHDL code of discete algoith that can subsequently be ipleented on FPGA. Keywods doubly fed induction geneato,, geneato, backstepping contol, FPGA. I. INTRODUCTION Xilinx Syste This pape pesents the backstepping contol of the DFIG and its developent by Xilinx Syste Geneato tool integated with Matlab / Siulink to geneate VHDL code fo FPGA pogaing. Backstepping contol is known as a constuction appoach in the sense that it has a systeatic way of constucting the Lyapunov function along with the contol input design [-]. To ensue stability o the negativeness of the deivative of the evey-step Lyapunov function, it usually equies the cancellation of the indefinite coss-coupling tes, while this cancellation esults in the pefect-looking of the deivative of the Lyapunov function, it does not ean that good pefoance is ensued [3]. This pape shows a siple, fast and effective ethod fo hadwae ipleentation of the backstepping contol of a doubly fed induction geneato using xilinx syste geneato. Syste geneato is a toolbox that can be integated into Siulink. Fo this tool, we can ceate blocks calculation (addition, subtaction, egiste, counte ) that ae siulated and tanslated into VHDL pogae to be ipleented on a Xilinx FPGA. This is an ipotant concept to undestand duing the design pocess using Xilinx Syste Geneato [5]. This pape is aanged as follows: the odeling of the DFIG with the stato field oientation is pesented in the second section. The backstepping contol of DFIG is shown in the thid section. Theeafte, the backstepping contol of DFIG is developed using Xilinx Syste Geneato (XSG) in the fouth section. Finally, the siulation esults ae depicted using Matlab/Siulink. II. EQUATION OF THE DFIG WITH STATOR FLUX ORIENTED Equations of the DFIG opeate unde stato flux oientation, in (dq) efeence fae, ae witten as follows: With: did Vd I d Rssd Iq dt L diq V I L I dt L dsd Rs Rs L sd I d dt d Tt f Te dt J J J R L R L s s L q q s sd d L L L s R L Electoagnetic toque of the DFIG is expessed by: III. T e sd q () pl I () BACKSTEPPLING CONTROL OF THE DFIG Backstepping contol of the DFIG will be done in two steps: Step : To calculate oto cuents efeences, we define the eos e and e, the fist epesents the eo between the actual echanical speed and its efeence, and the second epesents the eos between the diect stato flux and its efeence.

2 e e sd sd (3) e3 Iq I e4 Id I q d (0) Its deivative is given by: The elationship between e and e3, and e and e4 is given by: T f pl R R L e I t e sd Iq J J J s s sd sd d (4) pl e k e e Rs L e ke e4 sd 3 J () We define the fist Lyapunov function as: The deivative of (0) is: V e e (5) Its deivative is: V e e e e (6) Substituting (4) into (6), we obtain: T pl t V e sd Iq J J J R R L e s s sd sd d We choose the oto cuents as follows: f I (7) Whee: e 3 I f V e 4 I f V q q q L d d d L fq I q sd Id fd I d Rssd Iq The second Lyapunov function is defined by: () V e e e3 e4 (3) I JL T f s t Iq ke pl sd J J L k e R s s d sd sd Rs L With k and k ae positives, so the negativeness of Lyapunov function is veified: 0 (8) V k e k e (9) Step : the eos of cuents oto ae defined as: The deivative of this function give: V k e k e k e k e k3e3 I f V q q q L k4e4 I f V d d d L So we choose the oto voltage contol as follows: V L k e I f V L k e I f q 3 3 q q d 4 4 d d (4) (5)

3 Fig.. Block diaga of backstepping contol of the DFIG. Fig. shows the block diaga of the backstepping contol of the DFIG. IV. DEVELOPMENT OF BACKSTEPPLING CONTROL USING XILINX SYSTEM GENERATOR In this section, we focus on the softwae ipleentation of backstepping contol using Xilinx Syste Geneato that is a toolbox developed by Xilinx society to be integated into the Matlab/Siulink envionent. This toolbox contains blocks that can be inteconnected o connected to othe Siulink blocks. Once the odel is copleted, the VHDL code geneated by the tool XSG epoduces the sae behavio obseved on Matlab/Siulink [6-7]. It is easie to analyze the esults in Matlab that anothe utility associated with VHDL as Modelsi. The XSG tool is used to poduce a odel that will iediately wok on the equipent when copleted and validated [7]. The ain odel contains two blocks: A backstepping contol blocks that contains fou sub-blocks: - Speed contolle: it s a sub-block to calculate I q. - Flux contolle: it s a sub-block to calculate I d. - Quadatic cuent contolle: it s a sub-block to calculatev. - Diect cuent contolle: it s a sub-block to calculatev. A DFIG block in (dq) efeence. d q Fig.. Extenal view of backstepping contol with XSG. Fig. 3 pesents the intenal view of the backstepping contol with Xilinx Syste Geneato. This block contains fou subblocks: Speed contolle block, flux contolle block, quadatic cuent contolle, and diect cuent contolle. Fig. shows the backstepping contol using XSG.

4 V. SIMULATION RESULTS We pesent in this section a copaison between the siulation esults using Siulink and XSG. The paaetes of the DFIG and the gains of the backstepping contol ae given in Appendix. In the next we pesent the siulation esults using Siulink and XSG. A. Siulation using Matlab/Siulink The siulation esults show that contolling quadatic and diect oto cuents, can contol the echanical speed and stato flux espectively (Fig. 6 and Fig. 7). Fig. 8 shows that the echanical speed follows pefectly its efeence, and Fig. 9 shows also that the stato flux follows its constant efeence value Wb. Fig. 3. Intenal view of the backstepping contol with XSG. Fig. 4 shows the intenal view of the sub-block Speed contolle with XSG. Fig. 6. Response of quadatic oto cuent using Siulink. Fig. 4. Subsyste Speed contolle with XSG. Fig. 5 pesents the intenal view of the subsyste Quadatic cuent contolle with XSG. Fig. 7. Response of diect oto cuent using Siulink Fig. 5. Subsyste Quadatic cuent contolle with XSG. Fig. 8. Response of echanical speed and its efeence using Siulink.

5 Fig. 9. Response of flux stato using Siulink. B. Siulation using Xilinx Syste Geneato The siulation esults show that contolling quadatic and diect oto cuents, can contol the echanical speed and stato flux espectively (Fig. 0 and Fig. ). Fig. shows that the echanical speed follows pefectly its efeence, and Fig. 3 shows also that the stato flux follows its constant efeence value Wb. Fig. 0. Response of quadatic oto cuent using XSG. Fig. 3. Response of flux stato using XSG. By obseving the siulation of the echanical speed, the stato flux and the oto cuents, we conclude that the esults obtained by Siulink ae identical to those obtained by XSG, so ou objective has been eached, we can use this tool to poga ou FPGA. VI. CONCLUSION In this pape, we pesented a FPGA pogaing technique with a toolbox naed Xilinx Syste Geneato that is integated with MATLAB/Siulink to eplace the difficulties of VHDL pogaing. Taditional appoaches to the ipleentation of cicuits based on FPGA based on lowlevel languages (VHDL, Veilog) suffe fo poo flexibility and low poductivity, this is why the XSG tool is developed to ovecoe this poble. One of the biggest advantages of Syste Geneato is the apid tageting of digital signal pocessing (DSP) algoiths to field-pogaable gate aay (FPGA) and we can test the functioning of subsystes one by one. This technique is used to geneate the VHDL code of the backstepping contol of the DFIG. The next wok will be devoted to the expeiental ipleentation. APPENDIX Fig.. Response of diect oto cuent using XSG. TABLE I. DFIG NOMINAL PARAMETERS Rated powe 4Kw Rated stato voltage 0/380V Noinal fequency 50Hz Nube of pole pais p = Roto esistance R = 0.63Ω Stato esistance Rs =.47Ω Roto inductance L = 0.0H Stato inductance = 0.63H Mutual inductance L = 0.055H Moent of inetia J= 8kg. Daping coefficient f = 0.0N..s. d Fig.. Response of echanical speed and its efeence using XSG. TABLE II. K 00 K 40 K3 0 K4 50 BACKSTEPPING CONTROL PARAMETERS

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