EE 209 Lab 3 Mind over Matter

Transcription

1 EE 09 L 3 Min ovr Mttr 1 Introution In this l you will us th Xilinx CAD tools to omplt th sin o kis m ommonly rrr to s Mstrmin (simplii or sy implmnttion). In prtiulr, you will sin muxs, ristrs with nls, inrmntrs, ountrs, n 7-smnt or usin sum o mintrms (or-s sin) pproh. Not: In this l w hv provi th hih lvl sin, intiyin th omponnts n thir onntions n to implmnt th m. Your jo will to uil th iniviul omponnts. In utur ls you ll lso n to om up with som o th hihr lvl sin n w ll ssum you n thn uil th n omponnts on your own. Wht you will lrn This l is intn to show you th pross o usin n FPGA (Fil-Prormml Gt Arry) hip to implmnt iitl HW sins whil llowin you to prti your ility to implmnt n ritrry loi untion. 3 Bkroun Inormtion n Nots Th Mstrmin Gm: Th mstrmin m llows n "opponnt" to input srt omintion (in this s, inry omintion vi swiths) n thn lt th othr plyr input usss or th omintion proviin som kin o k (in this s ount o how mny swiths r in th riht oniurtion). Th norml m usully his th srt omintion n lts th plyr strt uss rom srth with only mximum numr o usss. Hr w llow ny numr o usss n you n rin will hv to tk turns sttin srt omintion whil th othr plyr osn't look n thn lippin th swiths to som rnom omintion to lt th othr plyr strt ussin. Th nrl low o th m is s ollows: Lst Rvis: 1/5/017 1

2 EE 09 L 3 - Min ovr Mttr CORRECT (Strt nw m) Init St Corrt Answr Comintion Wit For Usr to St Swiths n Prss Guss Button Compr Guss to Answr INCORRECT SETANS LD7 LEDs r unus in this l LD0 GUESSBTN BTNU BTNL B8 BTNR SW7 SW0 BTND # o Corrt Swiths in Us Swiths to st th omintion RESET Guss Fiur 1 - Swiths n us to st oth th srt omintion n th usss. Buttons n us to ptur th srt omintion or init uss is ry to sor. Th numr o orrt swith positions will isply on th 7-smnt isply. Gmply: 1. Plyr 1 shoul oniur th 8 swiths n prss th SETANS utton n thn rrrn th swiths in som rnom orr or Plyr strts to uss.. Plyr my now oniur th swiths howvr h/sh liks n thn prss th GUESS utton. This will trir th hrwr to ompr th swith oniurtion to th "nswr" (1-it t tim) n isply how mny swiths r in th riht pl (thouh not whih ons) 3. Plyr my rpt stp s muh s thy lik or i thy wnt to strt nw m simply strt t stp 1 (i.. oniur th swiths n prss SETANS). FPGAs: Fil-prormml Gt Arrys r hips tht hv mny hrwr rsours (.. ts, ristrs, t.) uilt on it ut n oniur or how to wir thm tothr. Th i is this on hip n oniur to wir th rsours tothr to implmnt on sin n thn roniur to wir th rsours tothr irntly to implmnt nothr sin. This is hny or our l sin w on't wnt to uy sprt hips or h l, ut inst rus th hip. Th sins you rw n sri in th Xilinx tools will onvrt (i.. synthsiz) to prou th pproprit oniurtion to implmnt tht xt Lst Rvis: 1/5/017

3 EE 09 L 3 - Min ovr Mttr sin on th FPGA. Your jo is just to prou th writ sin sription (i.. shmti in this s). Ovrll Dsin: A shmti o th ovrll HW sin is shown low n only onsists o hnul o omponnts (primrily ristrs, muxs, n ountr iruits). I you took EE 109 w wnt to rw omprison n hv you rliz you oul sily implmnt this in your Aruino ut it woul run siniintly slowr thn this HW vrsion n xut (thouh or humn usr intrtin t th sons/millisons lvl tht irn is unttl). But w simply wnt to point out tht wht n on in SW n on in HW n vi vrs. Howvr, lt's tk look t th hrwr sin. W on't xpt you to ully unrstn th oprtion n ll th omponnts yt ut within w wks you shoul l to n this my srv s ni xmpl/s stuy to rr k to. W strt t th top with th ANSWER[7:0] ristr. Whn you prss th SETANS utton, this will nl th nswr ristr n ptur whtvr is on th SWITCHES n sv it (rll ristrs sv vlus h tim you lok it). W thn wit until th Guss utton is prss whih strts ountr (prouin CNT[:0]) nrtin inry numrs (on pr lok). This 3-it squn (muh lik or loop ountr, i, n n rry) wlks throuh h urrnt swith, SWITCHES[i], (on th ottom mux) n th orrsponin ANSWER[i] it n omprs thm to s i thy r th sm n, i so, inrmnts ountr o how mny orrt positions th plyr hs. This CORRECT ount is thn isply on th 7-smnt isply. W n th 8-to-1 muxs to slt iniviul its to llow or squntil omprison n ountin sin omprin ll 8-its n ountin thm in prlll woul rquir itionl HW tht w lik to voi or now. swnt_n lk swnt_lr CNTR4 Q[3] Q[:0] SWITCHES[7:0] SW0 SW7 CNT[:0] 0 S[:0] 7 8-to-1 Mux ns_n CNT 7 uss_i SWITCHES[7:0] S[:0] ns_i D r8 Q ANSWER[7:0] 8-to-1 Mux Comprtor -its 0 orr_n rst orr_lr You omplt HIGHLIGHTED omponnts. inrmnt ntr_lr CNTR4 lk rst stns_tn uss_tn nt[:0] CORRECT(3:0) 7-Smnt Dor mmin_sm (Control) 7-S. 1 ns_n orr_n orr_lr swnt_n swnt_lr Fiur 1 Dtpth o th MstrMin Gm IMPORTANT: Kp omin k to this pitur n mp h omponnt hr to th omponnts in mmin.v Lst Rvis: 1/5/017 3

4 EE 09 L 3 - Min ovr Mttr Govrnin th vrious ontrol sinls to lok ristr, inrmnt ountr, rst ountr to 0, t. is stt mhin (whih you'v lso lrn out in EE 109) ut this stt mhin is implmnt in HW. You will lrn how to implmnt stt mhins in HW in w wks. Blow is th stt irm S i you n unrstn its si oprtion. RESET INIT stns_tn stns_tn CAPTURE ANS SWITCHES CNT 0 CORRECT 0 ~stns_tn stns_tn CHECK CNT CNT+1 orr_n 1 ~stns_tn uss_tn WAIT4GUESS i(uss_tn) CORRECT ~stns_tn nt!= 7 ~stns_tn nt==7 ~stns_tn ~uss_tn Your tsk: Your jo will to uil ll th iniviul omponnts. In oin this you shoul rviw how h omponnt is uilt. But nothr lrnin ol is to unrstn how to us hirrhy (tk 1 smll omponnt n omin thm with othrs to uil lr omponnts). This inlus: An 8-to-1 mux tht n us or th two muxs shown in Fiur 1 Dtrmin wht t n us in th lnk ovl tht is shown omprin th its rom th two muxs to s i thy r qul (i.. th omprtor o -its) n th AND t prouin th inrmnt sinl Th 7-smnt or tht will onvrt 4-it inry numr whos vlu is (0-8) to th pproprit smnts to liht up th 7-smnt isply. A 4-it inrmntr us in th 4-it ountr loks shown in Fiur 1. Complt th sin o r4 (4-it ristr with nl) tht will us in th 8-it ristr n th two ountrs shown in Fiur 1. Us hirrhy to rt th 8-it ristr with nl tht is us to stor ANSWER[7:0] rom two 4-it ristrs with nl. Importnt Nots: As you sin th 7-smnt or, it is importnt to not tht th tul isply is onnt in suh wy tht n output o 0 will liht up th smnt n 1 will turn it o. W rr to this s n tiv-low onvntion us th liht will turn on or tivt whn w output 0 (or low vlu). Th sist wy to l with this is to just sin th iruits normlly (prouin 4 Lst Rvis: 1/5/017

5 EE 09 L 3 - Min ovr Mttr outputs o 1 whn you wnt th LED to liht up) n thn us n invrtr riht t th output to lip th 1 you wnt to liht up th smnt to th tul 0 tht is n y th isply. Lst Rvis: 1/5/017 5

6 EE 09 L 3 - Min ovr Mttr Builin th omponnts 8-to-1 mux (mux8.v): This shoul strihtorwr. Do not us hirrhy hr (i.. o not s mny -to-1 muxs, t.). Inst, sin th 8-to-1 mux irtly rom AND, OR, NOT oprtions. 7-smnt Dor (svns_or.v): Givn 4-it input sin loi or th 7 outputs (-). Us th tth worksht t th n to hlp. Us sum-omintrm (or prout-o-mxtrm) pproh. Think out how you n just nrt ll th mintrms (or mxtrms) n shr thm to prou th 7 outputs (i.. you shoul not hv to rprou ll th mintrms or EACH o th 7 outputs). 4-it Ristr with Enl (r4.v): A ristr with nl is simply D lip-lops with -to-1 mux prou th D-FF s D input. Th mux llows us to hoos whthr w ryl th ol Q vlu n rtin it on th nxt lok yl OR i w shoul tk in n rmmr nw vlu (th ovrll D-inputs). Th shmti is shown low. Us th provi -to-1 mux in mux.v n th provi D-FF s to omplt th sin o th 4-it ristr with nl. (rst) onntions r not shown hr D0 0 1 Y S DFF1 D Q Q0 REG4E D[3:0] D1 0 1 Y S DFF1 D Q Q1 D 0 1 Y S DFF1 D Q Q D3 0 1 Y S DFF1 D Q Q3 4-it Inrmntr (in4.v): A 4-it ountr is iruit tht will ount up in inry on omintion pr lok yl. W n uil ountr s n inrmntr n 4-it ristr (with nl) tht you sin ov. Writ out truth tl or 4-it inrmntr whr h output is 1 mor thn th input omintion. Not tht th input omintion 1111 shoul us n output o 0000 (i.. th output wrps to 0). Us n pproh similr to th 7-smnt or y nrtin mintrms n thn prouin h output s untion o thos mintrms. 4-it Countr (nt4.v): Dsin th 4-it ountr y simply instntitin n wirin 4-it inrmntr n 4-it ristr with nl s shown in th shmti low. 6 Lst Rvis: 1/5/017

7 EE 09 L 3 - Min ovr Mttr CNTR4 INC4 X[3:0] F[3:0] REG4E D[3:0] 8-it Ristr w/ Enl: Dsin n 8-it ristr with nl y runnin two 4-it ristrs tothr in prlll. Us th inomplt shmti low to think out wht onntions r n. REG4E REG8E D[7:0] Q[7:0] D[7:0] D[3:0] REG4E D[3:0] Q[7:0] 4 Prl Non. 5 Prour 1. Downlo th projt sklton zip il rom our wsit n xtrt it to olr. Thn lo th projt il (th il with th.xis xtnsion) in Xilinx's Projt Nvitor. Opn th mmin.v Vrilo il (not th mmin_top.v). You will s struturl sription o th omponnts in our sin. You must now implmnt th missin sins. 3. Strt with th 8-to-1 mux. Opn mux8.v n omplt th loi y instntitin AND, OR, n NOT ts or usin ssin sttmnts. Do NOT us -to-1 muxs to uil th lrr 8-to-1 mux. Prti how to uil mux rom srth. 4. In th mmin.v il (this is th top-lvl sin il whr ll omponnts r instntit), sroll own to in th lnk r whr you shoul th t(s) tht r n to ompr th urrnt uss n nswr its n thn th AND t to prou th inrmnt sinl. B sur you us th pproprit sinl nms so tht th sin will orrtly wir th ts n ountr Lst Rvis: 1/5/017 7

8 EE 09 L 3 - Min ovr Mttr tothr. Your inputs shoul ns_i n uss_i. Th inl output o th AND t shoul inrmnt. 5. Now omplt th 7-smnt or sin y opnin th svns_or.v il.. Complt th truth tl or th outputs - in trms o th 4-it input on th tth sht whih you will sumit with your l rport.. In th Vrilo il, implmnt mintrms or inputs 0-9. Thn, or h output -, sum tothr th pproprit mintrms (us your truth tl to ui you) n prou tht output y NOR'in th pproprit mintrms tothr (w normlly OR mintrms ut rmmr th isply wnts 0's to liht up th smnt so w will just invrt t th output ) 6. Complt th implmnttion o r4.v to implmnt th 4-it ristr with nl. (You o not n to hv stui ristrs with nl to implmnt on. It is just wirin som -to-1 muxs n D lip lops tothr. S th rlir shmti). 7. Complt th implmnttion o in4.v to implmnt 4-it inrmntr. 8. Complt th implmnttion o ntr4.v to implmnt 4-it ountr. (You o not n to hv stui ountrs to implmnt on. It is just wirin ristr n inrmntr tothr. S th rlir shmti). 9. Finlly, implmnt th r8.v sin. Do so y wirin up two 4-it ristrs w/ nl. 10. Simult your sin usin th provi tstnh y likin th Simultion rio ox in th uppr riht o th winow, thn hoosin mmin_t.v in th Hirrhy r, n inlly Simult Bhviorl Mol in th Prosss r. W hv inlu wv oniurtion il tht will isply th most importnt sinls or you thouh you r wlom to mor. [Importnt] Th st wy to mk sur you unrstn th sin is to pinstkinly tr throuh th simultion wvorm n s wht hppns. Think out wht th input stimulus is: th swiths, th stns utton, th uss utton, t. Look or thos to t n i o wht snrio w r inputtin. Thn rom thr look t our iruit irm n think out wht th importnt sinls shoul o n whn. Conirm thm on th simultion wvorm. It tks tim to rlly unrstn wht is hppnin ut you will wll rwr with wht you lrn rom it n it will row your ility to u iitl iruits, so pls invst tht tim. 8 Lst Rvis: 1/5/017

9 EE 09 L 3 - Min ovr Mttr I you in th simultion osn t hv s intn, mor intrmit sinls, rrun your simultion, t. until you n iur out th prolm. 11. On you r stisi th sin sms to work in simultion w will now implmnt it on th FPGA. To o so, o to th Dsin/Hirrhy t in th top riht n slt th top-lvl il mmin_top.v. 1. Importnt: In th Prosss pn, riht-lik Gnrt Prormmin Fil, lik Proprtis n unr Strtup Options nsur tht th FPGA Strt-Up Clok is st to JTAG Clok. This is nssry or your sin to work proprly ut only ns to on on (th projt sttins will sv). 13. Now oul lik th Gnrt Prormmin Fil. It will tk som tim to synthsiz th sin n implmnt it ut whn it is on oul hk tht thr r no rrors (look t th rrors t in th ottom onsol r) or t th olor o th ion nxt to th Synthsiz n Implmnt prosss. Wrnins (yllow trinls) r in howvr. 14. At this point th hrwr oniurtion il (.it) il hs n nrt n is ry to oniur th hrwr on th FPGA ors. Gt Nxys- or rom your TA n onnt it vi USB to your lptop. I you r runnin on th Rmot Dsktop (VDI) you'll n hv th virtul mhin "tk ontrol" o th Nxys or y sltin "Connt USB Dvi" n thn hoosin "Diilnt Onor USB". 15. I you r runnin on your own PC you'll n to ownlo th Diilnt Apt sotwr usin th link on th Tools p o our ours wsit. 16. Strt th Diilnt Apt sotwr whih is us to ownlo th HW oniurtion. Mk sur th Connt il in th uppr riht sys Onor USB n th Prout is roniz s Nxys3. Finlly, in th FPGA row, slt th Brows utton n in th mmin_top.it il in your projt olr. Thn lik Prorm whih shoul oniur your hrwr n strt th prorm runnin. 17. Try plyin th m on th or n nsur th isply is showin pproprit iits. I you ot your loi wron o k n xmin it n try to ix it. You will thn n to rpt stps Dmonstrt your workin m to TA n t thir sinturs/initils. Sumit your ils onlin. Lst Rvis: 1/5/017 9

10 EE 09 L 3 - Min ovr Mttr 6 L Rport Nm: Sor: Du: (Dth n turn this sht lon with ny othr rqust work or printouts) Turn in th ollowin itms: 1. TA Sintur:. Sumit your mmin.v, in4.v, r4.v, ntr4.v, r8.v, mux8.v, n svns_or.v t th onlin sumission link on th l wp. 3. Complt truth tl low. BCD iit BCD to 7-smnt or COR[3] COR[] COR[1] COR[0] Lst Rvis: 1/5/017

11 EE 09 L 3 - Min ovr Mttr 7 EE 09 L 3 Grin Ruri Stunt Nm: Itm Outom Sor Mx. Dsin Corrt Truth Tls or - 1 Corrt mux8.v implmnttion Corrt r4.v implmnttion Corrt in4.v implmnttion Corrt ntr4.v implmnttion Corrt r8.v implmnttion Corrt svn smnt or implmnttion Corrt loi or omprin ns_i n uss_i 1 Ciruit works orrtly on th FPGA 1 SuTotl 15 Lt Dutions (-1 pts. pr y) Totl 15 Opn En Commnts: Lst Rvis: 1/5/017 11