for Heterogeneous III-V/Si Photonics Integration

Transcription

1 Study of Ultrathin SiO 2 Interlayer Wafer Bonding for Heterogeneous III-V/Si Photonics Integration Chee-Wei Lee*,Ying Shun Liang, Doris Keh-Ting Ng, Yi Yang, Yu Yu Ko Hnin, Qian Wang* Data Storage Institute, A*STAR (Agency for Science, Technology and Research), Singapore. ABSTRACT We demonstrated low-temperature bonding of III-V InP-based compound semiconductor on silicon via nano-thin SiO 2 interlayer down to thickness of 20 nm, with ultra-smooth surface for heterogeneous photonic integration. The bonding is achieved with chemical cleaning of the sample surface, followed by oxygen plasma surface activation, which gives high quality bonding between the two different materials. Detail analyses on the bonded samples are carried out. From the photoluminescence and the X-ray diffraction measurements, in which no significant peak shift and peak broadening are observed, we conclude that the crystalline quality of the bonded thin film is preserved. The cross-sectional high resolution transmission electron microscopy shows that bonded III-V-SiO 2 -Si interface has no observable defect. These results reinforce that the proposed bonding offers a promising technology for realizing versatile heterogeneous photonics integration. * lee_chee_wei@dsi.a-star.edu.sg, wang_qian@dsi.a-star.edu.sg

2 1 Introduction Wafer bonding is an important technique for heterogeneous integration of III-V photonic devices on silicon platform [1-4]. III-V material is excellent for active functionality, while silicon provides a low-cost and larger scale solution for passive functionality, and the wafer bonding technique allows us to combine the best of both worlds. As compared to the heteroepitaxial growth technique [5-6], integration through wafer bonding is a versatile technique that can be done either before or after the processing of photonic devices on individual material platform. Besides, it also reduces the threading dislocation and misfits at the bonding interface. In literatures, wafer bonding of III-V on Si is usually done either with an interlayer/interfacial layer, such as oxide [7-8] or nitride [9], or direct bonding [3,10]. Bonding through oxide interlayer has several merits over direct III-V to Si bonding as it eliminates the need for fabricating outgassing structures on the substrate for gas by-product diffusion and absorption during the bonding process [7], which reduces the fabrication process cycle time. The hydrophilic and porous oxide layer provides a medium for outgassing purpose and gives a strong bonding strength [7]. The interlayer also allows us to have flexibility in the choice of host substrate for bonding, regardless of any lattice matching, as long as a high quality oxide interlayer can be deposited. For example, the Si host substrate can be replaced with GaAs, SOI or glass. In terms of process, interlayer bonding eliminates the use of hazardous chemicals such as Piranha and hydrofluoric acid (HF) that are required in the direct III-V to Si bonding process [11]. However, despite the advantages that it offers, the existence of a low refractive index oxide interlayer will affect the up-down light coupling between III-V and silicon dramatically regarding the efficiency and coupling length. [1-2]. Hence, the oxide interlayer should be as thin as possible, but still be able to act as an outgassing medium during the bonding process.

3 In this paper, we report a low-temperature 220 C covalent bonding of InP-based epitaxial multiple quantum wells to silicon substrate through a nano-thin thermal oxide interlayer down to thickness of 20 nm, which is one of the thinnest interlayer proposed for heterogeneous photonics integration [7]. Thinner oxide interlayer was proposed [8] for microelectronics application but their annealing temperature is much higher at ~330 C, which worsens the thermal budget and may cause more dislocations in the bonded materials. Our SiO 2 interlayer is grown thermally on the silicon substrate only, but not on the III-V substrate, and this avoids the challenge to obtain high quality SiO 2 film on III-V substrate. Our bonding is also done at relatively low temperature, which reduces thermal budget and any implication on material or device pre-exist on the bonding substrates. The close proximity between the two substrates also allows more effective heat conduction as compared to bonding with thicker interlayer. In the next section, the experiment details of bonding process are illustrated. This is followed by the detailed analyses of the bonded samples, where we can see that the bonding does not affect the original material quality. The top surface quality of the thermal oxide and the III-V as grown layer are obtained via Atomic Force Microscopy (AFM) while X-ray Diffraction (XRD) and room temperature photoluminescence (PL) characterizations are used to inspect the material quality before (as-grown) and after bonding. Cross-sectional high resolution Transmission Electron Microscopy (HR-TEM) is then used to investigate the bonding interfaces. Finally, a conclusion is drawn, where we conclude that the bonding through nano-thin SiO 2 offers a better alternative to direct bonding. These are proven by XRD, PL and HR-TEM characterizations that show the bonded III-V film still preserved the original crystal quality of the as-grown sample. All these are possible through interlayer bonding process, which eliminates the use of hazardous chemicals and reduces the process steps for creating outgassing channels.

4 2 Experimental Our III-V based prime-grade epitaxial wafer is obtained commercially (IQE Inc.). The latticematched epitaxy layers are grown by metal-organic chemical vapor deposition (MOCVD) on an InP substrate. The active region consists of InGaAsP-based multiple quantum wells (MQW), with well and barrier each having thickness of 10 nm, and altogether they made up a total stack thickness of 350 nm. The active region is sandwiched in between an InP top cladding with thickness of 1000 nm and an InP substrate. Our silicon is prime-grade silicon wafer obtained commercially (Siegert Wafer GmbH). The Si wafer goes through dry thermal oxidation with First Nano CVD Horizontal Furnace for 16.5 minutes at 1000 C with an O 2 gas inflow of 2.5 SLPM. The oxidized silicon wafer is diced into pieces with 20 20mm 2 and the III-V wafer is cleaved into smaller die size of mm 2 for the die-bonding test. The bonding process starts with cleaning the two material substrates with organic solvents in ultrasonic bath. The solvents used are acetone, followed by isopropyl alcohol (IPA) and rinse with deionized (DI) water. The Si sample then goes through rigorous cleaning with diluted RCA solution of NH 4 OH : H 2 O 2 : H 2 O = 1 : 2 : 10 at 85 C for 20 minutes. Ordinary RCA solution is not used because the strong chemical reaction tends to roughen the oxide surface and makes the bonding difficult. After the diluted RCA clean, the Si sample is rinsed thoroughly with DI water. Meanwhile, the InP substrate is cleaned with NH 4 OH solution for 1 minute and rinsed with DI water. The two pre-bonding surfaces are then subjected to O 2 plasma surface activation via a Trion Sirus reactive ion etcher (RIE) with radiofrequency power of 50 W, O 2 gas flow of 20 sccm and process pressure of 250 mt for 1 minute. The O 2 plasma surface treatment helps to suppress interfacial void formation during the bonding process [12]. Right after the O 2 plasma treatment, the two substrates are then brought to close proximity and initial bonding is started from one edge to another slowly at room temperature to reduce the

5 air trapped between the substrates. The bonded pair is finally loaded on top with a metal block exerting pressure of 0.3 MPa and placed in a vacuum oven to anneal at 220 C for about 10 hours. After the bonding, InP substrate is removed with hydrochloric acid (HCl) : H 2 O = 3 : 1 solution for roughly 1 hour to release the InGaAsP thin film on the Si substrate. The etch solution etches InP but with no measurable etching depth on InGaAsP. The solution is also used for the same purpose in other works [1, 3]. The bonded pair is then rinsed with DI water and blow dried with nitrogen gun to complete the bonding process. Heating on the hotplate at above 100 C might be required before subsequent process to get rid of any water during the rinsing process. 3 Results and Discusssion Before any the wafer bonding is done, the surface quality of the bonding substrates is assessed. The roughness of the two bonding surfaces is measured by using tapping mode AFM. The measurements show that the root-mean-square (RMS) surface roughness of both thermal oxide on Si and InP samples are nm and nm, respectively, over a scanned area of 5 5 μm 2. The three dimensional scan profiles of the two surfaces are shown in Fig. 1. The surface smoothness is good enough for the bonding, with the surface smoothness of thermal oxide almost similar to the original prime-grade Si wafer. The AFM scan of the bonded III-V film is shown in Fig. 1(c) that indicates a RMS roughness of nm. This rougher surface could be due to the high concentration of HCl used in the InP substrate removal, which selectively attacks In and P in the InGaAsP etch stop layer slightly and causes the surface roughness. Nonetheless, the rough surface will not affect the device performance as it is above the top cladding and hence far from the waveguide core. It could even improve the adhesion of metal contact for some active devices.

6 In the wafer bonding process, the rigorous sample cleaning aimed to create hydrophilic surfaces for strong covalent bonding [11]. The thermal oxide as-grown by dry oxidation tends to be less hydrophilic, which is evident in the snapshot of water contact angle measurement in Fig. 2(a). The measurement is done with static sessile drop method. The water contact angle is 57.6 on the surface. After organic cleaning using acetone and IPA, the water contact angle reduces to 44.5, as shown in Fig. 2(b). As the SiO 2 surface is further cleaned with modified RCA solution, the hydrophilicity of the SiO 2 surface increases tremendously, hitting a water contact angle of 7.1 as seen in Fig. 2(c). Subsequent O 2 plasma surface activation does not improve the hydrophilicity of the surface substantially, but only reduces the water contact angle slightly to 6.4, as indicated in Fig. 2(d). On the other hand, the water contact angle of InP epitaxy substrate after NH 4 OH solution clean and O 2 plasma activation is 5.9. These highly hydrophilic surfaces have helped in the bonding of dissimilar materials, and proven that the rigorous cleaning and surface activation processes are instrumental in the bonding. After the bonding is done, characteristic photographs of the bonded pairs are shown in Fig. 3. The photographs show the bonding of III-V substrate onto a silicon substrate with 20 nm of SiO 2 interlayer. In Fig. 3(a), we show the bonded pair with the III-V substrate facing down to demonstrate the bonding force in action against the gravity. In Fig. 3(b), we show the bonded pair after the InP substrate is removed by HCl. Both photographs do not show significant defect on the bonded film. The defect at the edge of the III-V film as seen after InP substrate removal is caused by the tweezers for handling the sample during bonding process. In Fig. 3(c), we show a bonded pair for III-V substrate bonded on even thinner SiO 2 on silicon-on-insulator (SOI) substrate, with the InP substrate removed. We found that for such thickness of SiO 2, it is not able to absorb or dissipate the gas by-product from the

7 bonding process. Hence, significant amount of air voids are visible at region with no outgassing channels. In contrast, for region with outgassing channels etched on Si, the samples are well-bonded and there is no observable void. The outgassing channels are deliberately exposed for better illustration. Nevertheless, the need for outgassing channels diminishes the advantage of reducing fabrication process steps for interlayer bonding, and hence, it is not suitable in our context. It is also interesting to see whether the bonding can be done on full wafer scale. In Fig. 3(d), we show the photograph of a bonded 2-inch InP-based epi-wafer, with the InP substrate removed, on a 4-inch silicon wafer with 20 nm of thermal oxide. The photograph shows some defect on the bonded film. The defect at the edge of the III-V wafer film is caused by the tweezers for handling the sample during bonding process. The air-voids seen at the III-V film are probably caused by the large area bonding, which makes it harder for the air in between to escape during the initial bonding process. This problem could be overcome if commercial wafer bonder is used, where the bonding could be done under vacuum environment. A tensile pull test is conducted on another bonded pair prior to the InP substrate removal using INSTRON 5543 Standard system. The bonding fails at around 2.4 MPa, and this is much higher than the previous reported result [9]. In microscopic view of the bonding quality, we conduct cross-sectional HR-TEM on the bonding interface. Fig. 4 shows the cross-sectional TEM scan for the layers of III-V epitaxial sample that are bonded onto the SiO 2 -Si substrate. We can clearly see the MQW structures sandwiched by the top and bottom claddings. The two sides of the MQW consist of InGaAsP separate confinement heterostructures (SCH) with thickness of 25 nm. The AlInAs and the InGaAsP layers within the claddings are etch-stop layers. The topmost InGaAsP is

8 the highly-doped contact layer for electrically pumped devices. All these layers are for other work in the future. Figs. 5(a) and 5(b) presents TEM image of bonding interfaces between the III-V thin film and nano-thin SiO 2 interlayer on Si. We can observe sharp InP-SiO 2 -Si bonded interface, and InP and SiO 2 are bonded at atomic level. No observable structural defects and neither voids nor bubbles are being noticed at the interface. The grey dots in the SiO 2 layer in Fig. 5(b) are caused by the InP re-deposition during focus ion beam (FIB) milling for TEM sample preparation. The slightly thicker thermal oxide (~22nm) seen could be due to the inter-diffusion of SiO 2 and InP that are the in contact during the annealing step in the bonding process. The inter-diffusion is confirmed by the energy-dispersive X-ray spectroscopy (EDX) scan, as shown in Fig. 5(c), that reveals the existence of Si and O in InP and vice versa. In order to ensure that the transferred III-V thin film still preserved in original optical quality, the bonded III-V thin film is assessed by room temperature PL. Fig. 6 shows the room temperature PL spectra of the as-grown and the bonded III-V epitaxy layers, and both are from the same piece of wafer. From the measurement, we observe that there is no obvious peak shift and change of full-width-half-maximum (FWHM) for the bonded sample as compared with the as grown sample. These results indicate the robustness and feasibility of the thin film transferred and its readiness for subsequent device fabrication. The high quality of the transferred thin film is also confirmed by the high resolution XRD θ 2θ scans, as presented in Fig. 7. There is no peak shift or broadening for the transferred film as compared to the as-grown epitaxy sample. The almost unchanged XRD satellite order and FWHM of InP (004) peak indicate that the structural integrity of MQW is preserved and no significant defects are generated during the bonding process. This agrees with our TEM measurement as there is no defect propagating toward the MQW during the

9 bonding process. The silicon peak only exists in the bonded III-V film due to the existence of silicon substrate in the bonded pair. Conclusion We successfully demonstrated a low temperature interlayer wafer bonding process to transfer InP-based epitaxial film to Si substrate through nano-thin SiO 2 interlayer, which is a key enabling technology in heterogeneous photonic integration. The tensile pull test showed significant improvement in breaking pressure. The crystalline quality of the bonded thin film is preserved as compared to the as-grown film, and this is proven and examined by PL and HR-XRD characterizations. The HR-TEM characterization showed an atomically bonded interface with no observable defects generated at the bonding interface. The results proved that the technique is promising and advantageous to be implemented in heterogeneous photonic integration because of its flexibility and process simplicity. Acknowledgements The authors acknowledge the effort of Dr. Yadong WANG and Dr. Jing PU for initiating the work in wafer bonding. This work was supported by Data Storage Institute of Science and Engineering Research Council (SERC) of A*STAR (Agency for Science, Technology and Research), Singapore under grant no. DSI/ The fabrication and characterization were carried out in the A*STAR SERC Nano Fabrication, Processing and Characterization (SnFPC) facilities.

10 References 1. Pu, J.; Lim, K. P.; Ng, D. K. T.; Vivek, K.; Lee, C.-W.; Tang, K.; Kay, A. Y. S.; Loh, T. H.; Wang, Q. Heterogeneously integrated III-V laser on thin SOI with compact optical vertical interconnect access. Opt. Lett. 2015, 40, Keyvaninia, S.; Roelkens, G.; Thourhout, D. V.; Jany, C.; Lamponi, M.; Liepvre, A. L.; Lelarge, F.; Make, D.; Duan, G.-H.; Bordel, D.; Fedeli, J.-M. Demonstration of a heterogeneously integrated III-V/SOI single wavelength tunable laser. Opt. Exp. 2013, 21, Fang, A. W.; Park, H.; Cohen, O.; Jones, R.; Paniccia, M. J.; Bowers, J. E. Electrically pumped hybrid AlGaInAs-silicon evanescent laser, Opt. Exp. 2006, 14, Cao, Y.-L.; Hu, X.-N.; Luo, X.-S.; Song, J.-F.; Cheng, Y.; Li, C.-M.; Liu, C.-Y.; Wang, H.; Tsung-Yang, L.; Lo, G.-Q.; Wang, Q. Hybrid III V/silicon laser with laterally coupled Bragg grating. Opt. Exp. 2015, 23, Fehly, D.; Schlachetzki, A.; Bakin, A. S.; Guttzeit, A.; Wehmann, H. H. Monolithic InGaAsP optoelectronic devices with silicon electronics. IEEE J. Quantum Electron. 2001, 37, Prucnal, S.; Glaser, M.; Lugstein, A.; Bertagnolli, E.; Stöger-Pollach, M.; Zhou, S.; Helm, M.; Reichel, D.; Rebohle, L.; Turek, M. Zuk, J.; Skorupa, W. III V semiconductor nanocrystal formation in silicon nanowires via liquid-phase epitaxy. Nano Research 2014, 7, Liang, D.; Fang, A. W.; Park, H.; Reynolds, T. E.; Warner, K.; Oakley, D. C.; Bowers, J. E. Low-temperature, strong SiO 2 -SiO 2 covalent wafer bonding for III-V compound semiconductors-to-silicon photonic integrated circuits. J. Electron. Mat. 2008, 37, Yokoyama, M.; Iida, R.; Kim, S.; Taoka, N.; Urabe, Y. Takagi, H.; Yasuda, T.; Yamada,

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12 Figure Captions: Fig. 1. AFM scan of the (a) as grown III-V, (b) thermal oxide on Si, and (c) bonded III-V film over area of 5 5 μm 2 on the samples surfaces. Fig. 2. Snapshot of water contact angle measurement for (a) as grown SiO 2 surface, (b) SiO 2 surface after organic clean, (c) SiO 2 surface after organic clean and modified RCA clean, and (d) SiO 2 surface after organic clean, modified RCA clean and O 2 plasma surface activation. Fig. 3. Photographs of bonded pairs with (a) III-V substrate facing down and InP substrate not removed, (b) after the InP substrate is removed, (c) III-V bonded on SOI substrate through 20 nm SiO 2, and (d) full 2-inch InP epi-substrate bonded to 4-inch Si wafer with 20 nm SiO 2. Some reflections are seen on the substrates due to the mirror-polished surface. Fig. 4. Cross-sectional TEM scan of the different layers of the III-V epitaxial sample that are transferred to the SiO 2 -Si substrate Fig. 5. (a) TEM scan and (b) HR-TEM scans of the bonding interface between the III-V epitaxy sample and the SiO 2 interlayer on Si, and (c) EDX scan along the bonded interface, showing the material composition in the different layers. Fig. 6. Room temperature PL spectra of the as-grown (red) and the bonded III-V (blue) epitaxy samples. Fig. 7. XRD θ 2θ scan of as-grown and bonded epitaxial layers, showing the maintenance of strong InP peak and MQW satellite peaks. The (004) peak of Si and InP substrates are set as reference.

13 Fig. 1 µm 4 3 (a) 1 2 X µm/div Z nm/div µm 4 3 (b) 1 2 X µm/div Z nm/div µm 4 3 (c) 1 2 X µm/div Z nm/div

14 Fig (a) (b) (c) (d)

15 Fig. 3 (a) (b) Outgassing channels Region with air voids (c) Well-bonded region (d)

16 Fig. 4 InGaAsP InP MQW SCH AlInAs

17 Atomic % Fig. 5 InP SiO 2 (a) Si InP SiO 2 (b) Si In P Si O InP SiO 2 Si (c) Position (nm)

18 Fig. 6 Intensity (a.u.) After bonding Before bonding Wavelength (nm)

19 Intensity (a.u.) Fig InP Bonded As grown Si θ (deg)