The design of DSP/FPGA based maneuvering target tracking system

Transcription

1 Th dsign of DSP/FPGA basd manuving tagt tacing systm PAN-LONG WU, LIAN-ZHENG ZHANG, and XIN-YU ZHANG Dpatmnt of Automation Naning Univsity of Scinc and Tchnology No., Xiao Ling Wi Stt, Naning 94 PEOPLE S REPUBLIC OF CHINA plwu@63.com, fdomzlz@6.com, @qq.com Abstact: - Dbiasd convtd masumnt Kalman filt basd IMM (IMM-DCMKF) algoithm is a commonly usd manuving tagt tacing algoithm, which is combind with th intacting multipl modl (IMM) and th dbiasd convtd masumnts Kalman filt (DCMKF). Howv, th computation complxity of this algoithm is lag and th taditional alization of this algoithm using softwa can t mt th al-tim nds in actual application. This pap psnts th hadwa dsign of IMM-DCMKF algoithm basd on DSP/FPGA. In this tacing systm, th FPGA is usd as a floating point co-pocsso of th fixd point DSP, and th lag amount of calculation of IMM-DCMKF algoithm is alizd in FPGA. DSP is in chag of th schduling of th total tacing algoithm and th contol of th data stam, which solvs th poblm of th concuncy and al tim in th alization of th singl DSP schm. Th simulations of sults which show th hadwa dsign schm of IMM-DCMKF algoithm can mt th al-tim quimnt and simultanously nsu th accuacy of th data pocssing. Ky-Wods: -DSP, DCMKF, IMM-DCMKF, FPGA, Manuving tagt tacing. Intoduction Manuving tagt tacing is a hot topic in th fild of tagt tacing. Th y poblm of manuving tagt tacing is to stablish an accuat tagt s movmnt modl and a suitabl tacing filting algoithm. Tagt s manuving fs to th suddn chang in unpdictabl cicumstancs, such as pfoming som sot of tactic actions, including subduction, acclation, dclation, sting and so on. Th main challng of manuving tagt tacing is th tagt s movmnt unctainty. Now, th intacting multipl modl (IMM) algoithm is widly usd fo manuving tagt tacing []. In th systm of ada tagt tacing, th dynamic tagt is usually modld and tacd in th Catsian coodinats, whas th masumnts a povidd in tms of ang and angl with spct to th ada snso location in th pola coodinats. Thfo, th ada tagt tacing bcoms a ind of non-lin stimation poblm. On solution to this poblm is th xtndd Kalman filt (EKF) but would sults in filt distotion [-3]. Th oth solution is dbiasd convtd masumnt Kalman filt (DCMKF). Dbiasd convtd masumnt Kalman filt basd IMM (IMM-DCMKF) algoithm is a commonly usd manuving tagt tacing algoithm, which is combind with th intacting multipl modl (IMM) and th dbiasd convtd masumnts Kalman filt (DCMKF) [4-6]. Th IMM-DCMKF algoithm nds multipl filts woing in paalll, th computation complxity of th algoithm is lag. In th taditional softwa systm dsign, IMM-DCMKF is usually alizd by digital signal pocsso (DSP), which would b stictd by th sial instuction stam du to th complx computations of IMM-DCMKF and unabl to mt th high-spd al-tim signal pocssing nds. Howv, using th hadwa paalll achitctu fatu of fild pogammabl gat aay (FPGA) to aliz floating point of IMM- DCMKF can solv th poblm of high pcision and al tim [7-8]. Th innovation of this pap is utilizing FPGA as a floating point co-pocsso of th fixd point DSP to aliz IMM-DCMKF algoithm, which can satisfy th quimnt of high pcision and al tim in manuving tagt tacing systm, as wll as simplify th difficulty of systm dsign. Compad Matlab and Quatus II simulation data, both of th simulation sults a consistnt, this nsu that th computational accuacy and th liability of dsignd systm. Gnal systm dsign In this pap, w adopt DSP TMS3VC9A chip as a co pocsso of th ada tagt tacing E-ISSN: 4-66X 7 Volum 3, 4

2 systm. This fixd point DSP is sponsibl fo th schduling of th whol tacing algoithm and th contol of data stam. Th FPGA EP3CF484C8N chip is adoptd as floating point co-pocsso of fixd point DSP. DSP civs ada masumnts valus thn tansmits to FPGA. FPGA infoms DSP to tiv th filtd systm stat valus whn on fam data is pocssd.. Hadwa dsign of th systm SDRAM POWER Fig. shows th hadwa connction diagam btwn DSP and FPGA. Extnal mmoy intfac (EMIF) conncts DSP and FPGA. Whin, CE is chip lcting signal, AOE is asynchonous output nabl signal, AWE is asynchonous witing lcting signal, ARE is asynchonous ading nabl signal, INT[4 : ] is intupt nabl signal, D[7:] is data bus signal and A[7:] is addss bus signal. Whin, IO(D[7:]) is data bus signal,io( INT )is intupt nabl signal. Fig.3 shows th squnc diagam of witing opation btwn DSP and FPGA. AOE and ARE a st high whn witing. FLASH A DSP FPGA FLASH B SD 卡 UART(ST6C4) Fig. Th stuctu diagam of systm hadwa dsign. Th stuctu diagam of systm hadwa dsign is shown in Fig.. This systm is composd of DSP subsystm and FPGA subsystm. DSP subsystm consists of DSP, FLASH, synchonous dynamic andom accss mmoy (SDRAM), scu digital (SD) cad and som piphal intfac cicuits, FLASH is usd to sto pogam. SDRAM is usd to buff p-filtd and post-filtd data. SD cad is usd to sto both filtd and unfiltd data. FPGA subsystm consists of FPGA and lctically asabl pogammabl ad-only mmoy (EEPROM). FPGA is usd to aliz th complicatd IMM-DCMKF algoithm, EEPROM is usd to sto FPGA pogam[9]. Fig.3 Th squnc diagam of witing opation btwn DSP and FPGA.. Softwa dsign of th systm Calculation th initial Valu of DCM-IMM Tansmission intial Valu and th fouth Masud data to FPGA N N DSP civs ada data Data fams is gat than o qual to 3 Y Rciv data fams gat than 4 Y Tansf masumnt data to th FPGA Dsp civs intupt Signal fom FPGA Y Dsp ads th data fom FPGA Fig.4 Softwa dsign of th systm. Fig. Th hadwa connction diagam btwn DSP and FPGA. In softwa dsign of th systm, intnsiv data and highly ptitiv algoithm a pocssd by FPGA, whil low ptitiv algoithm is pocssd by DSP. In this ada tagt tacing systm, th initial valu of IMM-DCMKF nds to b calculatd only onc. E-ISSN: 4-66X 76 Volum 3, 4

3 Thfo, th initial valu of IMM-DCMKF is calculatd by DSP thn tansmits to FPGA. Howv, th subsqunt ach fam data nds to b filtd and consums a lag numb of pocssing tim. Thfo, w choos FPGA to complt IMM-DCMKF algoithm. Fig.4 shows th softwa bloc diagam of th ada tagt tacing systm. Th fist th fams data of coctly civd fom ada a calculatd fo initial valus of IMM-DCMKF. Aft th systm civs coctly th fouth fam data, DSP tansmits th calculatd initial valus and th masumnt valu to FPGA fo IMM-DCMKF filting. An intupt signal is tansmittd to DSP to tiv th filtd tagt stat valus aft FPGA pocssing ach fam data. 3 IMM-DCMKF algoithm pincipl In sphical coodinats, th location of th ada is fd as th oigin of coodinats, th actual ada masumnts of th tagt lativ to th ada is th tu azimuth angl θ m, lvation angl η m and adial distanc m, th cosponding nois vaianc is σ θ, σ η and σ spctivly. 3. Tagt tacing modl In this pap, th CV modl and CA modl a slctd to build in th IMM-DCMKF algoithm. Th tagt dynamic modl can b dscibd by X( + ) = Fi( ) X( ) + Gi( ) wi( ), i=,. () wh X( ) = [ x( ), y( ), z( ), x ( ), y ( ), z ( ), x( ), y( ), z( )] T d nots th stat vcto. x ( ), y ( ), z ( ) dnot th position in th xyz,, spctivly. x ( ), y ( ), z ( ) dnot th vlocity in th xyz,, spctivly. x ( ), y ( ), z ( ) dnot th acclation in th xyzspctivly.,, Th CV modl is usd to dscib th basic motion of th tagt, th CA modl is usd to dscib tagt manuv. Th matics F( ), F ( ), G ( ), G ( ), w ( ), w ( ) a spcifid as follows T T T F ( ) =, T T T T w G ( ) = T, w ()= w T w 3 T T T T T T T F ( ) = T, T T T T T w G ( ) = T, w ()= w T w 3 wh, T is th ada sampling piod. w ( ) is th acclation in th tim stp, w ( ) is th acclation incmnt in th tim stp. w, w, w3 a indpndnt Gaussian whit nois. Thfo, th masumnt quation aft coodinat tansfomation is as follows: E-ISSN: 4-66X 77 Volum 3, 4

4 H Z( ) = HX ( ) + V ( ) () = (3) wh, V( ) = v ( ), v ( ), v ( ) T is zo man x y z whit nois, th cosponding covaianc is R ( ). 3. IMM-DCMKF algoithm Th pocdu of IMM-DCMKF algoithm is shown in Fig.. X ˆ ( ) X ˆ ( ) ˆ X ( ) Modl Intaction µ ( ) o P ( ) i ˆ i = { P ( ) + [ X ( ) i= (6) ˆˆ o ( )][ X X ( ) ˆ ( )] ' X } u ( i ) (b) Modl-conditiond filting: Using ˆ o o X ( ), P ( ), th dbiasd convtd masumnt R ( ), Z ( ) as th inputs of modl in th tim stp, thn th nw stat stimation ˆ X ( ) and th cosponding stimation covaianc P ( ) can b achivd though Kalman filt. Masumnts in th Catsian coodinat Th dbiasd convtd masumnts Masumnts in th sphical coodinat Z ( ) ˆ O X ( ) ˆ O X ( ) filt filt filt M ( ) M ( ) M ( ) ˆ O X ( ) Modl Pobability Updat Λ( ) Stat Combination mcosηmcos θm Zc ( ) = Z ( ) µ ( ) = mcosηmsin θ m µ ( ) msinη m (7) x y z T µ ( ) = [ µ, µ, µ ] (8) xx xy xz R R R yx yy yz R ( ) = R R R (9) zx zy zz R R R X ˆ ( ) X ˆ ( ) X ˆ ( ) µ ( ) X ˆ ( ) Fig. Pocdu of IMM-DCMKF algoithm Th IMM-DCMKF algoithm consists of th following fou stps. (a) Modl intaction: Suppos th a modls, th tansition pobability fom modl i to modl is P i. P P P P P P P = (4) P P P Suppos ˆ X ( ) is th stat stimation of th filt in th tim stp, P ( ) is th stat covaianc matix, u ( ) is th pobability of th modl, i, =,,. Thfo, aft intactiv computing filt input in th tim stp th stat vcto is givn as follows. ˆˆ o ( ) X = X ( ) u ( i ) () i= wh u i = Pu i C = Pu i ( ) ( ), ( ) i i C i=. Th spcific fomula of µ ( ) and R ( ) can b found in fnc []. (c) Modl pobability updat: Dfining th filt siduals of th modl is v, th cosponding covaianc is S, thn th lilihood of th modl is: Λ = xp ( v)'( S) v π S () wh ( ) ( ) ˆ v = Z H X ( ) S H ( ) P ( ) H ( ) = + R( ). Th pobability updat of th modl is u( ) = Λ C () C wh C = ΛC. = (d) Stat Combination: Finally, all th sub-modl conditiond stat stimats and covaiancs a pobabilistically combind to find th ovall stimat X ˆ ( ) and its covaianc matix P ( ). E-ISSN: 4-66X 78 Volum 3, 4

5 ˆˆ( ) X = X ( ) u ( ) () = = ( ) { ( ) [ ˆ P = P + X ( ) ˆˆˆ( )][ X X ( ) X ( )]'} u (3) stat, covaianc, modl pobability and th loop filting valu, spctivly. At th fist fam, th tagt sphical coodinats valu, th initial stat valu, initial covaianc valu and th initial valu of th modl pobability a tansfd. Stating fom th scond fam, only th tagt sphical coodinats valus a tansfd. 4 FPGA alization of IMM-DCMKF algoithm In this pap, th MATLAB auxiliay Quatus II dsign mthod is usd to validat th pfomanc and accuacy of th FPGA alization of IMM- DCMKF algoithm. Fistly, th IMM-DCMKF algoithm is dcomposd into th scala fom, and alizd by MATLAB to validat th coctnss of th dcomposition. Thn th IMM-DCMKF algoithm is implmntd by using th VHDL languag accoding to th floating-point scala pogamming, and simulatd on th Quatus II platfom. Th floating-point data of Quatus II simulation sults a convtd to dcimal fomat data using th floating-point convsion softwa (IEE.x). Finally, th dcimal fomat data a compad with MATLAB simulation sults to vify th coctnss of th FPGA dsign. 4. Bloc-basd FPGA achitctu dsign Quatus II softwa-basd FPGA dsign pocsss includ top-down, bottom-up and bloc-basd dsign [-]. In this pap, th bloc-basd dsign pocss is adoptd. Th bottom-lvl is dsignd by VHDL languag, th top-lvl is dsignd by schmatic captu. Th input and synthsis tools of Quatus II a usd to dsign and synthsiz th vaious s, and ach is intgatd into th top-lvl dsign in th Quatus II softwa. Th dsign pocss including cicuit dsign with VHDL input, functional simulation, intgatd, comphnsiv post-simulation aft outing th main stps of th simulation and vification. Fig.6 shows th ovall stuctu diagam of th FPGA dsign of th IMM-DCMKF algoithm. Th figu includs a total of 8 s, s dsignd by VHDL languag, 3 fist in fist out (FIFO) s built-in FPGA, and 3 doubl-slction s. Th FIFO s a usd to sto th updatd stat valus, th updatd covaianc valus and th modl pobability updatd valus, spctivly. Ths stod data a ppad fo th nxt fam data filting. Th doubl-slction s a usd fo th initial valu slctd of Th tagt infomation of sphical coodinat s Covaianc in ciculation M U Th initial valu of X covaianc Th stat valus in th ciculation M U X initial valu of stat valus Th initial valu of Pobabilit M y modl U Pobability X modl in 3 th ciculation Th to xtact tagt infomation angl distanc Mixd covaianc stimatio n Mixd stat stimatio n Th invs matix of masumn t siduals mixd Modl pobability wight pdiction and mixd wight Modl pobability pdiction Th angl infomation squa Th modl Pobability Updat calculation Th on stp pdictio n Th stat avag tu bias Th on stp stat pdictio n Th Covaianc avag tu bias Th modl Pobability Updat calculation Th FIFO of stos th o Pobability updating valus Th tigonomtic function Th Gain matix modul Nw modu l tigonomt ic function Th invs matix of masumn t siduals Th modl Pobability Updat calculation Th Th tagt btwn th infomation sphical and of Catsian Catsian coodinats coodinats of convsion Th FIFO Th filting of o stos th covaianc o updat covaianc updating valus Th FIFO of stos th o stat updating Th valus stat Stat updat intactio Filt n output output modul Th invs matix 3 of masum Th masumnt nt sidual siduals matix dtminant Masumnt of sidual valu of th invs matix aay Th output of modl uss th pobabilistic Fig.6 Hiachical dsign of IMM-DCMKF algoithm basd on FPGA Alta Cyclon Ⅲ sis EP3SLH78 chip is chosn to aliz IMM-DCMKF algoithm on Quatus II platfom. Th floating point numb basd aithmtic opation s built in Quatus II consist of addition, subtaction, multiplication and division. Th basic floating point numb opation s a instantiatd and th cosponding paamts a st accodingly in th VHDL cod dsign, which would impov th dsign pfomanc, shotn th dsign tim and simply th data path alization of floating point data [3].Th synchonous cloc schm is intoducd into toplvl schmatic diagam duing th FPGA dsign of th IMM-DCMKF algoithm. In od to ma multipl s coodinatd, th nabl signal is st. Th stat of nabl signal of ach is dtctd to dtmin whth th cosponding opation can b implmntd [4]. In IMM- DCMKF algoithm som s nd th sult of th pvious s. Thfo, th IMM-DCMKF algoithm can not all paalll computing, In this pap, w adopt paalll computing in paalll computing s. Manwhil, nabld signal is dtctd in unabl paalll computing s to dtmin th appopiat opation. Th piplin tchnology is usd within ach to impov opation spd. E-ISSN: 4-66X 79 Volum 3, 4

6 4. Moduls dsign of IMM-DCMKF FPGA can only opat add, subtact, multiply, divid and oth simpl calculation, can not call function to cay out complx calculations. Thfo, IMM-DCMKF algoithm nds to dcompos into th scala fom, which can facilitat th alization of th cod, and ffctivly impov th FPGA souc utilization []. IMM-DCMKF algoithm nds to b dcomposd into simpl add, subtact, multiply, divid, indx and oot opation, ths opation can b alizd by th IP computing s which built in th Quatus II. Floatingpoint aithmtic dsign basd on FPGA will ta up mo soucs. Thfo, th tim multiplxd dsign ida is usd in basic aithmtic unit [6]. In od to aliz a balanc btwn spd and soucs of th FPGA, and sav soucs of floating-point multipli, this pap applis th following th optimizations. ) On th basis of th systm paalll computing, th CV modl and th CA modl a squnc filtd, and tim division multiplxd. Fistly, th CV modl is filtd, thn th CA modl is filtd. ) Th mging of simila itms to duc th us of th computing unit. 3) In th inn of computing s, th pvious-class itms which do not paticipat in th opation, a dlayd cosponding cycls by using th gists, and thn paticipat in th nxt-class computing. Taing th stat intactiv output as xampl, th Ox dnots th intaction output X ˆ ( ), Usx and Usx dnot th CV modl and CA modl updatd stat ˆ i X ( ), spctivly, Mp dnots th modl pobability µ () i.thfo,() can b dcomposd into th following scala fom: Ox = Usx* Mp + Usx* Mp Ox = Usx* Mp + Usx* Mp Ox = Usx* Mp + Usx* Mp Ox3 = Usx* 3 Mp + Usx* 3 Mp Ox4 = Usx* 4 Mp + Usx* 4 Mp Ox = Usx* Mp + Usx* Mp Ox6 = Usx 6* Mp Ox7 = Usx 7* Mp. Ox = Usx * Mp 8 8 Mp Usx RAM mmo y g_usx g_mp g_usx g_mp g_usx g_mp g_usx3 g_mp g_usx4 g_mp g_usx g_mp g_usx6 g_mp g_usx7 g_mp g_usx8 g_mp g_usx9 data g_mp g_usx distibutio g_mp n g_usx g_mp g_usx g_mp g_usx3 g_mp g usx4 piplin timing of multipli Piplin timing of addition Fig.7 Stuctual chat of stat intaction output Fig.7 is th bloc diagam of th stat intactiv output. Fistly, th civd data of th a stod in th synchonous RAM mmoy of FPGA whn dtcts th coct nabl signal. Thn, th data pocssing tim of pviousclass and nxt-class a qualizd though th ational dsign of data distibution. Th output of pvious-class dictly impot into th nxt-class input stag to paticipat in th piplind opations. In Fig.7, th piplin timing squnc of addition is simila to th piplin timing squnc of multipli. Th stat intactiv output nds a total of multiplis and add. In this pap, th piod paamts of floating point addition and multiplication units a st spctivly, which a st as 7 and cloc cycls in libay paamt (LPM) of Quatus II. Mp[3..] Usx[3..] cl st cl_nabl_mp cl_nabl_usx Ox Mp[3..] Usx[3..] cl st cl_nabl_mp cl_nabl_usx inst6 cl_nabl_ox Ox[3..] Ox cl_nabl_ox Ox[3..] Fig.8 Schmatic diagam of stat intaction output Fig.8 shows th top-lvl schmatic of th stat intactiv output. Wh, Mp dnots th data input pot of modl pobability valu, Usx dnots th data input pot of stat updat valu, cl is th cloc signal, st is th st signal, cl_nabl_mp and cl_nabl_usx a civ output data nabl signal of pvious-class, cl_nabl_ox is th nabl signal of th stat intactiv output data, Ox is th stat intactiv output data pot. Whn input pot civs th full stat valus and modl pobability valus on cloc cycl by anoth, th data distibution snds its cosponding multiplicand and multipli to th ight gist fo pocssing at ach cloc, and nabl computing. Th stat intactiv output output pocssd data at p cloc cycl aft (+7) cloc cycls [7]. Th input and E-ISSN: 4-66X 8 Volum 3, 4

7 output pots dsign of oth computing a simila. Taing th modl pobability updat as anoth xampl, bcaus modl pobability updat contains addition, multiplication, division and squa oot opations, its calculation is vy complx. In od to facilitat th dsign of VHDL languag, th () and () will b tansfomd into scala fom. Aftwads thy will b dcomposd into th s, spctivly. Th th s a dfind as modl pobability updat, modl pobability updat and modl pobability updat 3. In th dsign pocss, th output intmdiat vaiabl of modl pobability updat is Msm, th output intmdiat vaiabls of modl pobability updat is Ml. Z S_ RAM mmoy Data distib ution modul piplin opation Data distibu tion piplin opation Fig.9 Th dsign bloc diagam of th modl pobability updat Fig.9 is th dsign bloc diagam of th modl pobability updat, it uss th floatingpoint multiplis, six floating-point adds and a floating-point xponntiation. Duing th dsign of piplin opation, in od to ma th dsign data synchonization, using gists dlay and 7 cloc cycls involvd in th subodinat opation fo th itms, which a not involvd in th multiplication and addition opations. S Msm RAM mmo y Data distib ution modul piplin opation sq t 6 Fig.Th dsign bloc diagam of th modl pobability updat Fig. is th dsign bloc diagam of th modl pobability updat,it uss floating-point multipli, floating-point divid and oot opation. In th dsign of piplin opation, in od to ma th dsign data synchonization, using gists dlay and 6 cloc cycls involvd in th subodinat opation fo th itms, which a not involvd in th multiplication and addition opations. x p Ml Msm Ml Pmp RAM mmo y Data distib ution modul piplin opation 7 7 Data distibut ion piplin opation Fig. Th dsign bloc diagam of th modl pobability updat 3 Fig. is th dsign bloc diagam of th modl pobability updat 3, it uss floating-point multiplis, floating-point add and floatingpoint divid. Duing th dsign of piplin opation, in od to ma th dsign data synchonization, ight itms which a not involvd in th gists of th add us th 7 cloc cycls using gists of th add aft paticipating subodinat opation. Fig. Th top-lvl schmatic of pobability updat Fig. shows th top-lvl schmatic of pobability updat. Th input signal of includs th cloc signal cl,th st signal st, th innovation val ZK and it s input nabl signal cl_nabl_zk, th invs valu of th nw covaianc matix S_and it s input nabl signal cl_nabl_s_, th output signal is intmdiat vaiabls Msm and its output nabl signal cl_nabl_msm. Th input signal of is th cloc signal cl, th st signal st, th intmdiat vaiabls Msm and it s input nabl signal cl_nabl_msm, nw intstcovaianc matix of th dtminant of th valu S and its input nabl signal cl_nabl_s, th output signal is th intmdiat vaiabls M and output nabl signal cl_nabl_m.th input signal of 3 is th cloc signal cl, th st signal st, th intmdiat vaiabls M and it s input nabl signal cl_nabl_m,th modl pobability pdiction valu Pmp and its input nabl signal, th output signal is th modl pobability updat valu Mp and its output nabl signal. Th modl pobability updat valu is not only output to th Mp E-ISSN: 4-66X 8 Volum 3, 4

8 stat intaction Ox, but also output to th FIFO to stoag modl pobability updat valu fo th nxt data loop. Thfo, th a two output nabl signals, cl_nabl_mp_to_ox and cl_nabl_mp_to_fifo. Th nabl signal cl_nabl_mp_to_fifo will b closd whn all th modl pobability updat valus a stod in th FIFO. 4.3 Simulation wavfoms of FPGA Fig.3 and Fig.4 a intcptd pat of th input and output simulation wavfoms. Whin, Fig.3 is th initial valu and th fist fam of data input wavfom, th initial valu including th initial stat, th initial covaianc and th initial modl pobability. Th fist fam data a th adial distanc of th tagt, azimuth and lvation angl. Fig.4 is th stat intaction output wavfoms of th fist fam data. If cloc cycl is 4ns, on IMM-DCMKF filt cycl nds.88us.fig.3 and Fig.4 vify th timing simulation dlay is vy small. Fig.3Initial valu and th fist fam of data input wavfom Fig.4Th stat of intaction output wavfom of th fist fam of data Simulation and sults Fig.Hadwa cicuit boad Fig. shows th hadwa cicuit boad, this subsystm is composd of DSP, FPGA, SDRAM, FLASH, SD cad and oth componnts. Th pow supply fo th cicuit boad of DSP subsystm is DC V. Th pow supply fo th cicuit boad of FPGA subsystm is 4V DC. Fistly, th pow convt chip convts th DC 4V to DC V, thn supply to th DSP subsystm though th connction. In th FPGA subsystm, DC V is convtd to 3.3V,.V and.v spctivly. In this sction, a simulation scnaio is psntd to tac a manuving tagt. Th paamts of tagt a givn as follows: Th initial position is ( m,6 m, 4 m ), th initial vlocity is ( 3 m/ s, 3 m/ s, m/ s), Th sampling at is T = ms, th tagt flying tactoy is shown in Fig.6. Fom t=-s, tagt flis at constant vlocity, fom t=-3s, it mas S shapd acclation manuv, fom 3-3s it flis at constant vlocity. Th nois covaianc of th masud distanc, lvation η and azimuth θ a σ = / 36m, σ = π / 79ad, θ π / 34ad σ =. Th modl tansition pobability and th modl initial pobability a.99. P =..99, µ = [..]. In th pocss of simulation, th IMM-DCMKF algoithm is alizd spctivly in FPGA and Matlab platfom using th sam masumnts. Fig.7-Fig.9 a th position compaison in X, Y, Z dictions spaatly. Fom Fig.7-Fig.9, it is asily can b sn that th IMM- DCMKF is capabl of dnoising and smoothing fo tagt position. Fom Figs 6-9, it can b sn that th FPGA simulation sults a basically consistnt η E-ISSN: 4-66X 8 Volum 3, 4

9 with th MATLAB simulation sults, which povs th coctnss of th systm dsign noisy IMM-DCMKF(FPGA) IMM-DCMKF(Matlab) z/m 4 3 noisy IMM-DCMKF(FPGA) IMM-DCMKF(Matlab) z/m y/m x/m Fig.6Th tagt tactoy noisy IMM-DCMKF(FPGA) IMM-DCMKF(Matlab) 3 3 t/s Fig.9Compaison in Z diction Tabl. Opation tim compaison btwn DSP and FPGA Pocsso typ Modl Fquncy (MHz) Tim (ms) DSP TMS3 VC9A.687 FPGA EP3CF 484C8N.3 x/m t/s 7 6 Fig.7 Compaison in X diction noisy IMM-DCMKF(FPGA) IMM-DCMKF(Matlab) Tabl is opation tim compaison btwn DSP and FPGA. Fom Tabl., w can s th dsignd IMM-DCMKF algoithm basd on FPGA spnds.3ms to complt on filt pocss. Th opation tim is ducd ods of magnitud than singl DSP dsign schm. This tim fully satisfis th al tim quimnt in manuving tagt tacing systm. Expimntal sults pov th dsign of this pap is a good solution to th IMM-DCMKF algoithm pcision and altim quimnts in pactical ngining applications, and vify th supioity of this dsign. y/m t/s Fig.8 Compaison in Y diction 6 Conclusion In th manuving tagt tacing systm, th tacing pcision and al tim a highly quid. IMM-DCMKF algoithm includs a gat dal of matix aithmtic, such as matix addition, matix subtaction, matix multiplication, squa oot and invs, tc. Th computational tim fo calculating IMM- DCMKF algoithm in softwa is too long to mt th al tim of tagt tacing. In this pap, th FPGA is usd as a floating point copocsso of fixd point DSP. This softwa and hadwa asonabl dsign schm can solv th concuncy and spd poblms and guaant th tacing pcision. Thfo, it is an ffctiv E-ISSN: 4-66X 83 Volum 3, 4

10 appoach to complt manuving tagt tacing algoithm. Th dsign basd on FPGA has lag dg flxibility fo pogamming, updats cods at any tim, and lagly ducs th sach cost. Acnowldgmnt This wo is patially suppotd by th National Natu Scinc Foundation of China (NO. 6496), Natual Scinc Foundation of Jiangsu Povinc (No. BK33), Ziin sta Rsach Funding (NO. AB438). Rfncs: [] H. L. Han, X. C. Zhou, G. S Yuan, An impovd IMM algoithm of 3D manuving tagt tacing, Rada& ECM, Vol.3, No.4,, pp.9-3. [] P. L. Wu,Y. D. Cai, B. B. Wang, Satllit baings-only tacing using xtndd Kalman paticl filt, Infad and Las Engining, Vol.4, No.,, pp.8-3. [3] M. Alipazad, Kalman filt dsign fo tim dlay systms, WSEAS Tansactions on Systm,Vol.,No.,,pp.-6. [4] D. L. Liu, H. Q. Wang, X. Li, Manuving tagt tacing with non-lina masuing quations basd on IMM algoithm, Elctonics Optics & Contol, Vol.9, No.4,, pp.9-3. [] P. L. Wu, B. B. Wang, C. H. Ji, Dsign and alization of shot ang dfnc ada tagt tacing systm basd on DSP/FPGA, WSEAS Tansactions on Systm,Vol.,No.,,pp [6] C. H. Ji, P. L. Wu, S. Png, B. B. Wang, Dbiasd convtd masumnt IMM fo manuving tagt tacing algoithm alizd with hadwa, Elctonics optics & contol, Vol., No.4, 3, pp.-. [7] C. W. Wang, H. N. Cai, J. H. Wu, Alta FPGA/CPLD dsign (Basics), Posts & tlcom pss,. [8] S. Z. Zhong, C. H. Hou, C. A. Yang, Optimizd dsign of matix multipli basd on FPGA, Elctonic Masumnt Tchnology,Vol.3, No., 8, pp.9-. [9] L. Z Zhang, P. L. Wu, X. Y. Zhang, Ai dfns missil dtonation dlay contol basd on FPGA/DSP, WSEAS Tansactions on Systm,Vol., No. 4, 3, pp. -. [] N. N. Zhou, Y. L. Chn, A. Q. Li, Dsign and implmntation of floating point calculato basd on FPGA tchnology, Comput Engin and Dsign, Vol.6, No.6,, pp [] K. P. Chn, S. L. Zhu, Y. S. Lin, Implmntation of Psudo-Lina Kalman Filt fo Baings-only Tagt Tacing on FPGA, Fi Contol & Command Contol, Vol.3, No.3,, pp.-8. [] C. R. L, Z. Salcic, High-pfomanc FPGAbasd Implmntation of Kalman Filt, Micopocssos and Micosystms, Vol., No.4, 997, pp.7-6. [3] S. M. Shalini, Dsign and analysis of customizd mbddd Kalman filt, IE(I) Jounal-CP, Vol.88, No., 7, pp [4] H. P. Jiang, B. Li, Z. K. Shn, Dsign of adaptiv Kalman filt basd on FPGA implmntation,infad and Las Engining, Vol.34, No.,, pp [] G. Chn, L. Guo. Th FPGA Implmntation of Kalman Filt. Pocdings of th th WSEAS Int. Conf. on Signal Pocssing,, pp.6-6. [6] R. Pasicha, S. Shama. An FPGA-basd dsign of fixd-point Kalman filt, DSP Jounal. Vol.9, No., 9, pp.-9 [7] A. Bigdli, M. Biglai-Abhai, Z. Salcic, Y. T. Lai, A nw piplind systolic aay-basd achitctu fo matix invsion in FPGAs with Kalman filt cas study, EURASIP Jounal on Applid Signal Pocssing, Vol.6, Aticl ID 8986, 6, pp.-. E-ISSN: 4-66X 84 Volum 3, 4