MODELS TO ESTIMATE PRINTED CIRCUIT BOARD FABRICATION YIELD DURING THE DESIGN STAGE

Transcription

1 Journal of Electronics Manufacturing, Vol. 9, No. 3 (September, 1999) c World Scientific Publishing Company MODELS TO ESTIMATE PRINTED CIRCUIT BOARD FABRICATION YIELD DURING THE DESIGN STAGE RONALD E. GIACHETTI Department of Industrial & Systems Engineering, Florida International University, Miami, FL 33199, USA Received 6 November 1999 Accepted 16 December 1999 First pass yield is an important manufacturability measure of a printed circuit board (PCB) design. Designers need to strive to maximize process yield in order to improve product quality and reduce cost. To achieve this goal, the designer needs to understand the relationship between design decisions and their impact on process yield. The importance of process yield in electronics is bellied by the many studies dedicated to the topic; however there is a lack of a complete yield model of the PCB fabrication process that can be utilized during the early design stages. This paper aggregates the many studies and puts yield in the context of design so that yield can be estimated before board layout and routing. Early feedback on yield is important so that designers can explore different alternative technology sets before committing significant resources to the design. The application of the yield model is illustrated through a typical design session. Keywords: PCB fabrication, process capability, process yield, design-for-manufacturing. 1. Introduction The printed circuit board (PCB) fabrication industry is highly competitive in cost, quality, and timeto-market. In order to succeed in this environment, companies must consider manufacturing issues early in the design process. One critical manufacturing issue is process yield. Process yield is an important measure of the manufacturability of a design. It impacts PCB quality, cost, and lead time quotations. In quoting customer orders, PCB companies must estimate process yield since yield loss can be a significant component of the total cost. The process yield rates are also important so a company can determine how many PCBs to start an order in order to meet the order quantity and to estimate how much repair work may be necessary to fix defectives. Early estimation of process yield would allow designers the opportunity to assess the impact of process yield on cost and schedule and enable them to improve the PCB design with respect to process yield. Significant work has been conducted in estimating yield for PCBs; however much of it is proprietary research that is not publicly disseminated. Some of the approaches require input parameters that are not easily obtained, especially when a company wishes to quote a job immediately. Other methods are not amenable to estimation early in the design process because they require manufacturing data that is not available or they require historical data of the PCB that is by definition not available to the PCB fabrication company for new orders. In this work, we overcome these hurdles to rapid estimation of process yield by correlating the design features to the fabrication processes. Process yield models are developed as a function of these design features. Consequently, an estimation of yield can be obtained from the design specification and the manufacturing capability data of the fabrication facility. Moreover, the proposed yield estimation model utilizes design data available prior to layout and routing. The benefit is the designer can estimate yield before investing 191

2 192 R. E. Giachetti significant time in routing the PCB. Thus, the yield model is suitable for early manufacturability analysis since a designer can compare different design alternatives and assess the impact of design choices on process yield. The article is organized as follows. First the background of estimating process yield is discussed and different process yield models are examined. Section 3 presents an overall approach to modeling yield for PCB fabrication. We combine the results obtained by other researchers into a single model for the entire PCB fabrication process. The last section discusses the process yield model s implementation, presents an example design scenario, and draws conclusions for its utilization as a manufacturability evaluation tool early in the design process. 2. Background In the PCB industry as well as the semiconductor industry process yield is expressed using the Poisson function. Early work by Murphy 1 expressed yield as a Poisson function of critical area of the circuit and defect density. Defect density is modeled as a distribution as well which leads to a mixed Poisson yield model. Raghavachari et al. 2 review different Poisson mixture models when different distributions are used for defect density. Heineken and Maly 3 utilize the Poisson model for semiconductors and show that critical area can be accurately estimated based on average wire density and length estimates. Thus, they utilize the model prior to routing of the semiconductor. Winosky 4 adapts the semiconductor Poisson yield model to inner layer print and etch of PCBs and validates the model with experimental data. The Poisson yield model has also been applied to PCB assembly for modeling soldering. 5 In all these applications, the opportunities for defects is high while the occurrence of defects is low. It is under these circumstances that the Poisson model makes accurate predictions of yield. and thus appropriate for many processes within electronics manufacturing. Shih et al. 6 demonstrated that assembly yield of surface mount components onto a PCB could be modeled by writing an equation describing the failure condition, assigning probability distributions to the model parameters, and then sampling the parameters using a Monte Carlo simulation to predict the yield rate. This approach was also used later by Linn and Lam; 7 also for assembly. The Monte Carlo simulation approach lends itself to any process in which yield can be expressed as a geometric condition using mathematical equations. In PCB fabrication, this includes inter-layer registration and soldermask registration. Many experimental studies have been published investigating the yield of single processes within the entire PCB fabrication process. For example, Hinton 8 studies lamination processes and its affect on registration yield and Carhart and Murray 9 study inner layer processing yield obtained with different resist materials. These studies have the objective of investigating different manufacturing equipment, processes, and materials to determine their effect on process yield. Since the process yield models were developed with a specific objective they are not suitable for early estimation of process yield directly. Shina 10 reports that companies have used regression analysis to model process yield. These companies collect data of their process yield and plot it against complexity factors. Regression analysis is then used to derive functions for process yield versus the complexity functions. The benefit of this approach is the direct correlation between design parameters and process yield. The many experiments and studies of individual process steps are very useful for understanding the relationship between design parameters, manufacturing processes, equipment, and yield. However, for manufacturability analysis early in the design process the individual process yield models need to be consolidated into a single aggregate process yield model for the entire PCB fabrication process. Furthermore, the process yield models need to be a function of design parameters available early in the design process prior to routing. It is during this stage the yield model can have the greatest impact on guiding designers towards improved designs. This is advantageous since designers can explore many different alternative technology sets before committing resources to the design. The manufacturing data can be assumed to be invariant since in the short-term the supplier who is quoting a job order will not be modifying their manufacturing operations. 3. A Consolidated PCB Fabrication Yield Model The standard PCB fabrication process was modeled using the IDEF0 methodology 11 to identify the primary PCB processing steps that cause yield loss. The IDEF0 methodology utilizes a hierarchical decomposition to model processes. Instead of attempting to capture yield loss at the lower level,

3 Models to Estimate Printed Circuit Board Fabrication Yield During the Design Stage 193 Table 1. Fabrication process steps that contribute most to yield loss. Major Process Steps Individual Fabrication Yield Loss Issues Design Features Impacted Process Steps Inner layer Image transfer Image resolution Wire width/wire spacing processing Artwork registration Total inner layer wire length Particle contamination Board area Copper etching Over-etching Inner wire width Total inner layer wire length Lamination Lamination Material shift Layer count Layer registration Board area Interfacial delamination Innerlayer thickness Drilling Drilling Drill wander Hole count Mechanical damage Board thickness Lack of through-hole Hole diameter and annular ring condition allowance Connectivity of via holes Outer layer Image resolution Outer layer wire width/wire spacing processing Artwork registration Total outer layer wire length Particle contamination Soldermask Soldermask Mask on pads Hole diameter Insufficient web Annular ring where almost 30 distinct process steps are identified; process yield was modeled at aggregate process steps. Our studies indicate the major yield loss steps to be inner layer processing, lamination, drilling, outer layer processing, and soldermask which closely agree with Shina. 10 The aggregate process steps are shown in Table 1. The process yield models are developed separately for each of the five major processes listed in Table 1. Each process yield model correlates the appropriate design features to the process yield at that processing stage. The inner layer processing and outer layer processing yield models are adapted from the critical yield model presented by Winosky 4 and also used in semiconductor manufacturing. The drilling yield model is a Poisson model based on diameter size and number of holes. The yield models for hole to pad registration and soldermask registration are developed based on the manufacturing tolerances for these processes and a Monte Carlo simulation. The first-pass yield of the PCB is the product of the yield at these five major processing steps Inner layer processing yield Yield loss in inner layer processing is primarily caused by contaminants during print and etch. 4 These conditions result in open circuits (a broken line) on the inner layer, which can be detected during circuit testing. The yield depends on the circuit dimensions (line widths, spaces, and length) and the defect size. In order for the defect to cause a failure it must occur in a critical area on the circuit. If a contaminant deposits on the PCB where no circuitry is then it will not cause a failure (see Fig. 1). Consequently, critical area is a measure of the opportunities for defects on the PCB. The critical area (A c ) is a function of line width, line length, circuit geometry, and defect size. For a single line the critical area is, A c = L(x w). (1) For two parallel lines separated by space s the critical area is, where L(x + s) if x>2w+s A c = 2L(x w) if w x 2w+s 0 if x<w x = defect size w = wire width s = space width L = wire length (unit). (2)

4 194 R. E. Giachetti Conductor width Critical Area Open Occurs Here Defect (but no open) conductor Fig. 1. Critical area definition for a wire. 20 Critical Area (sq. Inch) Ac (1000 inc h) Ac (2000 inc h) Ac (500 in ch) line width (inch) Fig. 2. Critical area versus line width defect density defect density defect diameter Fig. 3. Defect density versus defect diameter.

5 Models to Estimate Printed Circuit Board Fabrication Yield During the Design Stage 195 Figure 2 shows the relationship between critical area and line width for three different total line lengths. The assumptions are parallel evenly distributed lines and the line width and spacing are equal. Two relationships between critical area and the design parameters become apparent in Fig. 2. First, as line width decreases the critical area increases. Second, as line length increases the critical area increases. Since critical area is a representation of the opportunities for defects then as critical area increases the yield will decrease. Critical area is also a function of the defect size. Each manufacturing facility can be characterized by a defect size distribution. Winosky 4 models the defect density as, 1 D(x) =D b n e( x/n) (3) where n is an adjustable parameter and D b scales the distribution. The relationship between defect density and defect size is shown in Fig. 3 for a representative facility. The Poisson yield model is applied to inner layer processing using critical area and defect size distribution as, Y il = e Ac(x)D(x). (4) Both the critical area and the defect density illustrate that smaller line widths will have a lower yield due to a greater opportunity for defects as measured by critical area and high density of defects to cause those failures Registration yield The primary mis-registration failure mode is hole break-out. Break-out occurs if the drill center deviates from the center of the capture pad so that the hole edge extends outside the pad boundary. The break-out condition is shown in Fig. 4. When the via hole passes through several pads then a defect will occur if the hole breaks out of any of the capture pads. There are two contributing factors to via break-out; the annular ring (clearance between the hole and capture pad) and the alignment of the multi-layers during lamination. The registration yield model presented here incorporates variations due to the manufacturing process and the design specifications in a Monte Carlo simulation to estimate yield. Sources of variation are hole diameter, pad diameter, hole registration, and pad registration. The equation for the annular ring on the top layer is, ( ) Dp1 D h A r1 = (P p1 + P h ). (5) 2 The second capture pad will have different variation due to separate processing and layer shift during lamination. Thus, a second equation is written for the second pad as, ( ) Dp2 D h A r2 = (P p2 + P h ) (6) 2 where D p = pad diameter D h = hole diameter P p = pad location P h = hole location. If either A r1 0orA r2 0 then a hole break-out failure occurs. The registration model can also incorporate anti-pads when a via requires a clearance ring to pass through a power or ground plane. Equations (5) and (6) are unchanged for this situation. If Capture pad Drill mis-registration Drilled via CENTER break-out occurs here pad mis-registration Fig. 4. Registration between hole and capture pad.

6 196 R. E. Giachetti the via hole connects more than two capture pads then Eq. (6) is calculated for A r3 and so on for each capture pad Monte carlo simulation of registration yield The main parameters of the model are described by normal distributions. A Monte Carlo simulation is used to estimate the registration yield based on the manufacturing process variation. Each run of the simulation samples a value from the distribution for each parameter and uses these values in Eqs. (5) and (6) to calculate the annular rings A r1 and A r2. If either annular ring fails the acceptance condition (A r1 0orA r2 0) then it is counted as a defect, otherwise it is acceptable. The simulation is run for all the instances of the holes in the design. A final yield is then calculated as the number of good holes over the total number of holes. where Y lm = N s N d N s (7) N s = total number of simulation runs N d = number of simulation runs with defects. Pad Width Clearance Mask Width Web Fig. 5. Soldermask surrounding two surface mount pads Outer layer processing The outer layer processing yield is modeled in the same manner as the inner layer processing. The model is, Y ol = e Ac(x)D(x). (10) In this model, the critical area and defect density are indicative of the outer layer processing work center Soldermask registration 3.3. Drilling yield model Drilling is a mechanical process and experiences failures due to either incomplete through hole condition or mechanical problems with the hole. The factors that influence drilling yield are drill diameter, board thickness, number of holes, and drilling accuracy. The primary design parameter impacting drill yield is hole diameter. Smaller holes are more difficult to drill and result in more defects. The relationship between defect density D d and hole diameter D is described by the following exponential equation, D d = bm D (8) where b and m are constants obtained from the regression analysis. The drilling yield is then obtained using a Poisson yield model as, where Y dr = e D dn h (9) N h = number of holes which is a measure of the opportunities for defects. Soldermask yield loss occurs when the soldermask screen is mis-registered with the outer layer circuitry. This becomes a critical yield issue when fine-pitch components are present in the design. In fact, Linn and Leung 12 cited soldermask mis-registration as a major quality problem where defect rates of 15 20% were commonly experienced by a particular company. There are two failure conditions for soldermask application; first if mask is screened on the surface mount pad, and second if the web between two adjacent pads is less than an established value. Figure 7 shows the geometry for the soldermask process. The clearance between the soldermask and its pad is, ( ) wm w p c = (P m + P p ). (11) 2 If c 0 then the failure condition of mask on pads occurs. The web between two adjacent pads is defined as, web = ρ w m1 2 w m2 2. (12)

7 Models to Estimate Printed Circuit Board Fabrication Yield During the Design Stage 197 If web web limit then the insufficient web failure condition occurs, which may lead to solderbridging during assembly. The same Monte Carlo simulation approach described in Sec is utilized to estimate soldermask registration as, 3.6. First-pass yield Y sm = N s N d N s (13) The first-pass yield of the entire PCB process, assuming no repairs is, Y total = Y il Y lm Y dr Y ol Y sm. (14) 3.7. Estimating wiring requirements Utilization of this model prior to component layout and routing requires the designer to estimate both circuit geometry and total wire length. These design features are not known prior to routing, but are required to estimate process yield. To estimate total circuit length the wireability model of Chiba et al. 13 is applied. The model is used to understand the wiring demands of advanced packaging; here it is adapted to a prediction of the total wire length. The model assumes all I/O pins and vias are located on a grid and that wireability is limited by two resources; wiring channels and via holes. The total wire length required to interconnect a circuit is, L = α(l x + L y )N p. (15) The coefficient α is empirically developed and is a proportionality coefficient nearly equal to 0.1. L x and L y are the PCB length and width in grid pitches. Equation (15) estimates the demand for wiring, a separate equation is used to estimate the supply of wiring. The available channel length for wiring is, L e = e l N l N c L x L y. (16) N e is the number of layers and N c is the number of lines per channel. Chiba uses this to show the limitations of circuit parameters on density. Here it is used as a feasibility check of the design parameters. If L<L e then the design parameters are feasible. Otherwise, the designer must change the parameters since it is unlikely the design can be routed. Studies comparing the model to actual products by both Chiba et al. 13 and Palmer and Williams 14 confirm the model s validity. For the purposes of our estimation, the total wire length is evenly distributed on all the signal layers. The circuit geometry is necessary to select the correct equations for critical area. Here we make the assumption of parallel lines such as is found when routing wires in channels. In addition to estimating total wire length the number of via holes must be estimated. According to Chiba et al. 13 the number of vias required are, N h = βn p (17) where β is an efficiency coefficient nearly equal to 1 and N p is the number of pins. The availability of locations for via holes is, N he = L x L y γn p η qn p η. (18) The coefficient γ is the ratio of the total number of pads assigned to signal, ground and power to the total number of pads to assigned to the signal. The coefficient q is the ratio of the number of pads reserved for engineering changes to the total number of pads. The parameterη is the signal pin utilization ratio. Empirically derived values for γ are 1.2 to 1.5, q between 0 and 1, and η between 0 and 1. If N h > N he then the design parameters are feasible. Otherwise, the designer must change the parameters since it is unlikely the design can be routed with the number of via holes available. 4. Discussion of Model The model captures the couplings between the design variables and the PCB fabrication yield. According to the critical area model for internal layer processing the line width is the primary design factor affecting yield. The total wire length increases the opportunities for defects and thus possibility of defects. In drilling the drilled hole diameter is the primary factor affecting yield. In drilling the number of holes indicates the opportunities for defects. The registration model shows the relationship between the hole diameter, pad diameter, and desired annular ring. The soldermask registration model indicates the pad pitch is a primary design factor affecting process yield. Figure 6 demonstrates that as line width decreases the inner layer yield will decrease slightly until it reaches a threshold below which it drop precipitously. This point at which the slope changes should be considered the processing capabilities of that facility. The figure also shows that as total line length increases yield will decrease. Similar relationships are exhibited for outer layer processing, except the slope and threshold are different.

8 198 R. E. Giachetti % % 95.00% 90.00% yield 85.00% 80.00% 500 inches 1000 inches 2000 inches 75.00% 70.00% 65.00% 60.00% line width (inches) Fig. 6. Inner line width versus yield for three different total line lengths. 95.0% 85.0% 75.0% 65.0% 55.0% 500 holes 1000 holes 45.0% 35.0% hole diameter (inch) Fig. 7. Hole diameter versus yield. Fig. 8. Yield versus via diameter when pad = inch and number of holes = 1000.

9 Models to Estimate Printed Circuit Board Fabrication Yield During the Design Stage % 95.00% 90.00% yield yield (1000 pads) yield (500 pads) 85.00% 80.00% 75.00% pad pitch Fig. 9. Soldermask yield as a function of pad pitch (inch). Fig. 10. Main menu.

10 200 R. E. Giachetti According to the drilling equation, hole diameter and number of holes are the primary design factors that impact yield. This relationship is illustrated in Fig. 7. The inter-layer registration is also affected by hole diameter as well as pad diameter. Figure 8 shows for a constant pad diameter and number of holes that an optimal hole diameter exists which balances drilling yield and registration yield. Soldermask registration yield is affected by pad pitch such that the closer the pads (smaller pitch) the more defects. Figure 9 shows that as pad pitch decreases yield decreases and as the number of pads increases yield will decrease. Other factors such as pad width are correlated to pad pitch and thus exhibit similar relationships. 5. Implementation and Illustrative Example The model was implemented using an Excel spreadsheet and Visual Basic from Microsoft. The main menu is shown in Fig. 10. Separate sheets are used for entering design information, manufacturing information, and each yield loss center as well as a summarization of the first-pass yield shown in Fig. 11. The model aids the designer in determine the best of several alternatives. For example, two functionally equivalent design alternatives are listed in Table 2. Design alternative A represents a design utilizing a standard manufacturing capabilities for the facility. Design alternative B represents more demanding specifications with respect to manufacturing. Both designs have the same components, thus the same number of surface mount pads and pad pitch. However, in design alternative B a smaller overall board size is possible by using smaller line widths, smaller via holes, and two more layers for routing. The total line length and number of vias were estimated using Eqs. (15) and (17) respectively. The system calculated first-pass yield is show for design alternative A as 78.6% and for design alternative B as 70.3%. In design alternative B the line widths and via holes are smaller which leads to more manufacturing difficulty and consequently a lower estimated Fig. 11. Yield summary screen.

11 Models to Estimate Printed Circuit Board Fabrication Yield During the Design Stage 201 Table 2. Design alternatives. Design Feature Alternative A Alternative B Board dimensions 6 9 inches inches Line width/spacing 8/8 mil 5/5 mil Number of signal layers 4 6 Number of connections Number of surface mount pads Pad Pitch inch inch Min hole diameter inch inch Capture Pad Diameter inch inch Total wire length (est.) 1500 inches 1250 inches Number of vias (est.) First-pass yield 78.65% 70.31% first-pass yield. However, it is noted that first-pass yield is a single measure of design performance and must be balanced against other criteria such as cost and time-to-market. 6. Conclusion A PCB fabrication process yield model was presented that consolidates five different process yield models for individual process steps. These five major process steps are inner layer processing, lamination, outer layer processing, drilling, and soldermask. They were identified as the major contributors to yield loss through process modeling. The inner layer and outer layer processing models utilize the critical area based yield model. The drilling yield model is a Poisson model. The registration and soldermask registration yield models were developed herein using a Monte Carlo simulation approach. The five process yield models together provide an estimation of first-pass yield of the PCB. The advantage of the process yield model is it correlates design specifications that are available early in the design process to manufacturing capabilities. The manufacturing data is based on historical defect data for inner layer processing, drilling, and outer layer process and on tolerances for lamination and soldermask. In order to estimate yield prior to layout and routing a wireability model was applied to estimate total wire length and number of vias. Using the consolidated yield model the designer can make early estimates of their design decisions on PCB fabrication process yield. The yield model can thus serve an important role as a component of the design-for-manufacturing strategy employed in industry. Acknowledgments This research was partially funded by the Printed Circuit Board Manufacturing Technology Center (PIMTEC) in Huntsville, Alabama through the cooperation of the US Army Aviation and Missile Command at Redstone Arsenal. References 1. B. T. Murphy, Cost-size optima of monlithic integrated circuits, Proceedings of the IEEE (1964), pp M. Raghavachari, A. Srinivasan and P. Sullo, Poisson mixture yield models for integrated circuits: A critical review, Microelectronics and Reliability 37(4) (1997), pp H. T. Heineken and W. Maly, Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs, IEEE/ACM International Conference on Computer-Aided Design, Los Alamitos, CA (1996), pp M. Winosky, Modeling of defects in the print and etch process of printed circuit board manufacturing, Proceedings of the Electronic Components Conference, New York (1986), pp M. Tegethoff and T. W. Chen, Sensitivity analysis of critical parameters in board test, IEEE Design & Test of Computers 13(1) (1996), W. Shih, Y. Huang, K. Srihari and G. Westby, Yield estimation through component placement accuracy evaluation in surface mount PWB assembly, Journal of Electronics Manufacturing 6(1) (1996), R. Linn and M. M. Lam, Analysis of process errors and production yield for surface mounted printed circuit assembly, Journal of Electronics Manufacturing 8(1) (1998), P. E. Hinton, Solving the problems of internal layer registration, Electronic Packaging and Production 32(1) (1992), R. A. Carhart and A. J. Murray, Improving fine line

12 202 R. E. Giachetti yield, Electronic Packaging and Production (1996), S. Shina, Concurrent Engineering and Design for Manufacture of Electronics Products, VanNostrand Reinhold, New York, R. E. Giachetti and M. I. Alvi, An object-oriented information model for manufacturability analysis of printed circuit board fabrication, in review (1999). 12. R. Linn and W. Leung, An investigation on artwork image mis-alignment in printed circuit board manufacturing, 6th Industrial Engineering Research Conference Proceedings (1997), pp T. Chiba, Yamada and F. Kobayashi, Limitation of the signal pin density on wiring boards, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B 19(2) (1996), P. J. Palmer and D. J. Williams, Understanding models of substrate behavior for the routing of high density I/O packages, Proceedings of the IEEE Symposium on IC Package Design Integration, Santa Cruz, CA (1998), pp

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