Liqiong Wei, Zhanping Chen, and Kaushik Roy. Yibin Ye and Vivek De. logic circuits more feasible.

Transcription

1 _ Mix-V th (MVT) CMOS Ciruit Dsin Mthooloy or Low Powr Applitions Liqion Wi, Zhnpin Chn, n Kushik Roy Shool o Eltril n Computr Eninrin Puru Univrsity, W. Lytt, IN Yiin Y n Vivk D Intl Corp., Hillsoro, OR Astrt Dul thrshol thniqu hs n propos to ru lk powr in low volt n low powr iruits y pplyin hih thrshol volt to som trnsistors in non-ritil pths, whil low-thrshol is us in ritil pth(s) to mintin th prormn. Mix-Vth (MVT) stti CMOS sin thniqu llows irnt thrshols within loi t, thry inrsin th numr o hih thrshol trnsistors ompr to th t-lvl ul thrshol thniqu. In this ppr, mthooloy or MVT CMOS iruit sin is prsnt. Dirnt MVT CMOS iruit shms r onsir n thr lorithms r propos or th trnsistorlvl thrshol ssinmnt unr prormn onstrints. Rsults init tht MVT CMOS sin thniqu n provi out 20% mor lk rution ompr to th orrsponin t-lvl ul thrshol thniqu. 1 Introution Th inrsin n or low powr in portl omputin n wirlss ommunition systms is mkin sin ommunitis pt low volt CMOS prosss [1, 2]. With th lowrin o supply volt, th trnsistor thrshol volt (Vth) hs to sl own to mt th prormn rquirmnts. Unortuntly, suh slin inrss th suthrshol lk urrnt, thry inrsin lk powr. Multipl-Vth sin thniqu n us to l with th lk prolm in low powr n hih prormn pplitions. Multi-Thrshol-Volt CMOS (MTCMOS) iruit thnoloy ws propos y insrtin hih thrshol vis in sris to norml iruitry [3]. This thniqu is vry tiv or th stny lk powr rution. But th lr insrt MOSFETs inrss th r n ly. For ul thrshol sin thniqu, hih thrshol volt n ssin to som trnsistors in non-ritil pths so s to ru lk urrnt, whil th prormn is mintin u to th low thrshol trnsistors in th Aknowlmnt: This rsrh is support in prt y DARPA (F C-1625), NSF CAREER wr ( MIP), Smionutor Rsrh orportion (98-HJ-638), n Intl. Prmission to mk iitl/hropy o ll or prt o this work or prsonl or lssroom us is rnt without provi tht opis r not m or istriut or proit or ommril vnt, th opyriht noti, th titl o th pulition n its t ppr, n noti is ivn tht opyin is y prmission o ACM, In. To opy othrwis, to rpulish, to post on srvrs or to ristriut to lists, rquirs prior spii prmission n/or. DAC 99, Nw Orlns, Louisin () 1999 ACM /99/06..$5.00 ritil pth(s). Thror, oth hih prormn n low powr n hiv simultnously. This thniqu hs n monstrt tht lk powr n ru urin oth tiv n stny mos without ny ly n r ovrhs [5]. Rntly, ul-vth MOSFET pross ws vlop [4], mkin th implmnttion o ul-vth loi iruits mor sil. Howvr, u to th omplxity o th iruits, not ll th trnsistors in non-ritil pths n ssin hihr thrshol volt. Othrwis, som non-ritil pths my om ritil. In orr to hiv th st lk svins unr prormn onstrints, lorithms or ul thrshol ssinmnt wr prsnt in [5, 7]. But ths lorithms only lt with th iruits t th t-lvl th trnsistors within t wr ssum to hv th sm thrshol volt. For mix-vth (MVT) CMOS iruits, th trnsistors within t n hv irnt thrshol volts with rtin pross onstrints. Thror, mor trnsistors n ssin hih-vth, n hn, lrr lk urrnt rution n hiv. In this ppr, irnt MVT CMOS iruit shms r introu n svrl lorithms or MVT CMOS iruit sin r prsnt. Th iny o h lorithm is monstrt y xprimnts on 32-it r n som ISCAS nhmrk iruits. Th ppr is orniz s ollows. In Stion 2, nssry nitions r introu. Dirnt MVT CMOS iruit shms r propos in Stion 3. Stion 4 sris thr lorithms or MVT CMOS iruit sin. Stion 5 prsnts th implmnttion tils n xprimntl rsults. Finlly, onlusions r ivn in Stion 6. 2 Prliminris Lt us onsir Fiur 1. Th loi ts r lrly mrk in irls. Suppos t G is th on in nlyz. GIi n GO r th nin n nout ts o G, whr i vris rom 1 to th numr o nins (FI) n vris rom 1 to th numr o nouts (FO). Eh nin t GIi onnts to pir o trnsistors (pi ;ni) in t G or stnr CMOS implmnttion. Similrly, or h nout t, thr r pir o trnsistors (p ;n) rivn y t G. 2.1 Trnsistor-lvl stti timin nlysis Trnsistor-lvl stti timin nlysis is us in our lorithms. Eh trnsistor hs proption ly, whih n

2 GI i xprss y p i G n i o p GO n Fiur 1: An xmpl iruit shmti t = tintrinsi + toutput CL (1) whr tintrinsi n toutput r th intrinsi ly n th ly pr unit lo, rsptivly. Thy n xtrt rom SPICE simultions [6]. CL is th lo pitn, whih is th sum o nout t pitns. Inrsin th thrshol volt will inrs t. Th irn twn hih-vth ly n low-vth ly is rprsnt y t. For th primry inputs n primry outputs, thr r timin onstrints. Eh primry input (PI) hs n rrivl tim. For th primry output (PO), thr is rquir tim. For h t G, th rrivl tim t th input o G is th tim whn th sinl propts rom th primry input to th input o G. Th prtur tim o G is th sum o th rrivl tim n th ly o th orrsponin trnsistor. Oviously, th rrivl tim is trmin y th prtur tim o th orrsponin nin t. Thr r two kins o prtur tim. On is or th hih-to-low trnsition t th output, not y Tl (G). Th othr orrspons to th low-to-hih trnsition t th output, rprsnt y Tlr(G). Tlr n Tl r trmin y th p pull-up tr n th n pull-own tr o G, rsptivly. For stnr CMOS iruits, thy n xprss y th ollowin qutions, Tlr(G) = mxtl (GIi)+t(pi) i (2) Tl (G) = mxtlr(gii)+t(ni) i (3) whr i vris or ll th nins. I GIi is primry input, its ly is 0. Hn, th prtur tim quls to th rrivl tim. 2.2 Trnsistor ly slk Th slk is th mount y whih t or trnsistor n slow own without tin th iruit prormn. For loi t, th slks o th p pull-up tr n th n pull-own tr r rprsnt y Sp n Sn, rsptivly. For primry output PO, th slk is trmin y th irn twn th rquir tim n th prtur tim o its n-in t. For ny othr t G, Sp n Sn n xprss y Sp(G) = min Sn(GO)+Tl (GO), Tlr(G), t(n) (4) Sn(G) = min Sp(GO)+Tlr(GO), Tl (G), t(p) (5) whr vris or ll th nout o G. Sn(GO) n Sp(GO) r th slks o th pull-own tr n pull-up tr or th nout t GO. Tl (GO),Tlr(G),t(n) n Tlr(GO), Tl (G), t(p) r th mounts y whih th p pull-up tr n pull-own tr o t G n slow own without tin th prtur tim o nout t GO, rsptivly. Sp(G) n Sn(G) r tkn s th minimum vlu ovr ll th nout ts so s to mintin th prormn. For h trnsistor pir (pi; ni) in t G, thir slks n rprsnt s s(pi) n s(ni), s(pi) = Sp(G) +(Tlr(G), Tl (GIi), t(pi)) = min s(n)+(tlr(g), Tl (GIi), t(pi)) (6) s(ni) = Sn(G) +(Tl (G), Tlr(GIi), t(ni)) = min s(p)+(tl (G), Tlr(GIi), t(ni)) (7) whr Sp(G) (Sn(G)) is th slk o th p pull-up tr (n pull-own tr) o G, whih is th miniml trnsistor slk ovr ll th nout FETs (FETs). Th trms (Tlr(G),Tl(GIi),t(pi)) n (Tl (G),Tlr(GIi),t(ni)) r th mounts y whih trnsistor pi n ni n slow own without tin th prtur tim o t G, rsptivly. I th thrshol volt is inrs rom low-vth to hih-vth, t will inrs y t, n thror, th trnsistor ly slk will ru y t. As lon s th slk vlu is no lss thn 0, whih mns t is no lrr thn th slk vlu, th iruit prormn is not r. 2.3 Trnsistor priority From BSIM MOS trnsistor mol [8], th suthrshol lk urrnt o MOSFET n mol s W Isu = 0 Cox ( kt ) 2 1:8 L q q n 0 kt (V GS,V th ) (1,,qV DS kt ) (8) whr Cox is th t oxi pitn pr unit r. W n L r th tiv hnnl with n th tiv hnnl lnth, rsptivly. 0 is th zro is moility. n 0 is th suthrshol swin oint o th trnsistor. Forlow-Vth trnsistor, i its thrshol volt is inrs to hih-vth vlu, th lk rution is proportionl to th tiv hnnl with n th moility. Thror, w n th lk rution msur or trnsistor i s ollows, lki = W i i (9) whr is th normliz moility, whih is qul to p n n 1 or trnsistors n trnsistors, rsptivly. p n n r th hol moility n ltron moility, rsptivly. Th lk rution msur o ul-vth iruit, not y M lk, is n s M lk = X i lki (10) whr th summtion is tkn ovr ll th hih-vth trnsistors in th ul-vth iruit. Th lrr th vlu o M lk, th mor lk rution n hiv or ul-vth iruit, ompr to th orrsponin sinl low thrshol iruit. For h trnsistor, lrr lk is prrl or lrr lk rution. Consir th hih-vth ly n low- Vth ly irn (t). I it is smll, lr numr o

3 trnsistors n ssin th hih thrshol unr prormn onstrints, thry lin to mor svins in lk powr. In our nlysis, w n th priority o trnsistor i s ollows, priority(i) = lki t i (11) Clrly, trnsistor with lrr priority will rsult in mor lk rution. 3 Mix-Vth (MVT) CMOS Ciruit Shms In this stion, irnt mix-vth iruit topolois r prsnt. Lt us rst onsir Fiur 2 whih illustrts smll prt o sinl-vth iruit. Suppos tht th trnsistors in th squrs r th trnsistors in th ritil pths, n hn, n hv low-vth. For th othr trnsistors, hih-vth n ssin without rin th prormn. Trnsistor in ritil pth Fiur 2: sinl-vth iruit Fiur 4: MVT1 shm Fiur 3: DVT shm Fiur 5: MVT2 shm Consir th t-lvl ul-vth (DVT) iruit. All th trnsistors within t hv th sm thrshol volt. Th ts r ithr ll hih-vth or ll low-vth ts. Fiur 3 shows th t-lvl ul-vth shm o th xmpl iruit shown in Fiur 2. For mix-vth CMOS iruit, th trnsistors within t n hv irnt thrshol volts with rtin pross onstrints. Thr r two typs o mix-vth CMOS iruit shms tht w onsir. For typ I shm (MVT1), thr is no mix Vth in p pull-up or n pull-own trs. Fiur 4 shows th xmpl iruit in MVT1 shm. For typ II shm (MVT2), mix Vth is llow nywhr xpt or th sris onnt trnsistors. Th xmpl iruit in MVT2 shm is illustrt in Fiur 5. Th rson tht trnsistors in stk hv th sm thrshol volt is us o th pross onsirtion. Suppos th trnsistor thrshols r ontroll y hnnl opin. For th trnsistors in stk, thir hnnls r too los to h othr, mkin it iult to hiv istint hnnl opin. Thror, it is hr to t irnt thrshols or th trnsistors in stk. Oviously, MVT CMOS shows mor opportunitis or th hih Vth ssinmnt thn th t-lvl ul thrshol iruit. 4 Alorithms or MVT Stti CMOS Ciruit Dsin In this stion, w will show howtovlop mix-vth (MVT) stti CMOS iruit unr prormn onstrints. Lt us ssum tht th timin onstrints or th primry inputs n primry outputs r ivn. Thr r two thrshol volts. Th hih-vth is rprsnt y VtH n th low-vth s VtL. In orr to hiv n optiml mix-vth stti CMOS iruit, thr trnsistor-lvl lorithms or th ssinmnt o hih thrshol to sinl low Vth stti CMOS iruit r propos. Th rst on is n xtnsion o th t-lvl lvliztion-s k-trin lorithm [5], whr th trnsistors r trvrs lvl y lvl rom primry outputs. Th son on is priority sltion lorithm, whr th trnsistors r visit orin to th priority vlus. Th thir on is priority-s k-trin lorithm, whih is th omintion o th rst two lorithms. 4.1 Bk-trin (BT) Alorithm Th rst stp in this lorithm is to lvliz iruit. Th lvl o primry input is n to 0. Th lvl o t G, not y l(g), n lult y l(g) = 1 + mx l(gii) (12) i whr i vris or ll th nin o G n GIi is th ith nin o t G. By trminin tintrinsi n toutput vlus orrsponin to VtH n VtL s on HSPICE simultions, th proption ly o h trnsistor t VtH n VtL n vlut usin qution 1, n th orrsponin ly irn (t) n sily lult. Th nxt stp is to ssin ul thrshol volts to th trnsistors unr prormn onstrints. All th trnsistors in th iruit r initilly ssum to hv th low thrshol volt. W orwr-tr th iruit lvl y lvl rom primry inputs to lult th prtur tim o h t usin qutions (2) n (3). Nxt, k-tr th iruit lvl y lvl rom primry outputs to xplor vry t G. Th pull-up tr slk(sp(g)), pull-own tr slk (Sn(G)), n th slk oh trnsistor within G n lult y usin th qutions (4)-(7). For th t-lvl ul-vth (DVT) shm, i t o ll th trnsistors within G r no lrr thn thir slk vlus, G is hih-vth t. For th mix-vth typ I shm (MVT1), i ll th trnsistors in th pull-up (pull-own) tr o t G stisy th rquirmnt tht t r no lrr thn thir slk vlus, th pull-up (pull-own) tr n ssin VtH. Lt us onsir th mix Vth typ II shm (MVT2). For h trnsistor o t G, i it is not sris onnt trnsistor n its t is no lrr thn its slk vlu, this trnsistor n ssin th hih-vth. For th sris onnt trnsistors, i th t o ll th trnsistors in sris r no lrr thn thir slk vlus, VtH is ssin to ll th trnsistors in th sris. Othrwis, VtL is mintin. Atr th thrshol volt ssinmnt or h trnsistor within t G, th proption ly o h trnsistor within G is upt. Thn th prtur tim o t G, Sp(G), n

4 Sn(G), r rlult. Th psuo-o o this prour is shown low. Bktrin lorithm () Lvliz th iruit Evlut t o h trnsistor or V th n V tl Clult t o h trnsistor Assin V tl to ll th trnsistors Forwr tr th iruit lvl y lvl Clult th prtur tim o h t Bk-tr th iruit lvl y lvl to visit h t G Clult S p(g) n S n(g) For h trnsistor (tr) within G Clult s(tr) I DVT is slt I ll th trnsistors in G stisy t slk G will ssin V th I MVT1 is slt I ll th trnsistors in pull-up tr o G stisy t slk Pull-up tr o G will ssin V th I ll th trnsistors in pull-own tr stisy t slk Pull-own tr o G will ssin V th I MVT2 is slt For h trnsistor (tr) within G I tr is not sris onnt trnsistor I t (tr) s(tr) tr n ssin V th Els i tr is in sris n not visit I ll th trnsistors in th sris stisy t slk All th trnsistors in th sris r ssin V th Mrk ll th trnsistors in th sris visit Upt th prtur tim o G,S p(g) n S n(g) For th ktrin (BT) lorithm, sin h trnsistor is ust visit on, th worst s run-tim is O(n), whr n is th totl numr o trnsistors. 4.2 Priority Sltion (PS) Alorithm Priority sltion lorithm is n xhustiv priority-s lorithm. Th trnsistors r visit orin to th priority vlus. Atr h visit, th trnsistor slks r rlult. Th psuo o o th priority sltion lorithm or mix-vth typ II shm (MVT2) is outlin low. Priority sltion lorithm () Lvliz th iruit Clult ly n priority o h trnsistor All th trnsistors r ssin V tl n mrk unvisit I th unvisit trnsistor numr is not 0 Forwr-tr th iruit lvl y lvl Clult th prtur tim o h t Bk-tr th iruit lvl y lvl Clult th slk o h trnsistor Fin mx priority trnsistor (tr) rom unvisit trnsistors I tr is not sris onnt trnsistor I t (tr) s(tr) tr n ssin V th Mrk tr s visit trnsistor Els i tr is in sris I ll th trnsistors in this sris stisy t slk All th trnsistors in this sris n ssin V th Mrk ll th trnsistors in this sris s visit trnsistors Th rst stp is to lvliz th iruit n lult th ly n priority o h trnsistor. All th trnsistors r ssum to hv VtL n mrk unvisit. Th son stp is to xplor ll th trnsistors in th iruit orin to th trnsistor priority vlus. For h visit, th prtur tim o h t n vlut y orwr trin th iruit lvl y lvl rom primry inputs, n th slk o h trnsistor n lult y ktrin th iruit lvl y lvl rom primry outputs. Th trnsistor with th mximl priority rom th unvisit trnsistors is thn slt. By omprin th t o th trnsistor in visit with its slk vlu n onsirin th sris onnt trnsistors, th thrshol volt o this trnsistor n trmin. In orr to voi rptin ssinmnt, this trnsistor is mrk s visit trnsistor. For th priority sltion (PS) lorithm, th iruit ns to upt to r-lult th trnsistor slk vlus tr h trnsistor is visit. Thror, th worst s run-tim is O(n 2 ). 4.3 Priority-Bs Bktrin (PB) Alorithm Priority-s ktrin lorithm omins th ktrin lorithm n th priority sltion lorithm. Durin th initiliztion, th iruit is lvliz; th ly n priority o ll th trnsistors r lult. Thn, th trnsistors r put into m roups orin to thir priority vlus, whr roup 1 orrspons to th mximl priority roup n roup m is th roup with th miniml priority. Nxt, rom roup 1 to m, ktrin is prorm m tims. Durin h ktrin, only th trnsistors in th slt roup r onsir. I m = 1, this lorithm is quivlnt to th ktrin lorithm. I m = n, this is xtly th priority sltion lorithm. Th psuo-o o th priority-s ktrin lorithm or mix-vth typ II shm (MVT2) is shown low. Priority-s ktrin lorithm () Lvliz th iruit Clult ly n priority o h trnsistor All th trnsistors r ssin V tl n mrk unvisit Trnsistors r ivi into m roups s on priority vlus For roup i rom 1 to m Forwr tr th iruit lvl y lvl Clult th prtur tim o h t Bk-tr th iruit lvl y lvl to visit h t G Clult th slk o h trnsistor within G For h trnsistor (tr) within G I tr is in roup i I tr is not sris onnt trnsistor I t (tr) s(tr) tr n ssin V th Els i tr is in sris n not visit or I ll th trnsistors in this sris stisy t slk All th trnsistors in this sris r ssin V th Mrk ll th trnsistors in this sris visit Upt th prtur tim o G,S p(g) n S n(g) For priority-s ktrin (PB) lorithm, th trnsistors r ivi into m roups. Atr h roup is visit, th iruit is upt to r-lult th trnsistor slks. Hn, th worst s run-tim is O(mn). 5 Implmnttion n Rsults Th thr lorithms sri in Stion 4 hv n implmnt in C unr th Brkly SIS nvironmnt. In this stion, th rsults or numr oomintionl iruits r prsnt. In our nlysis, th thrshol volt n supply volt o th oriinl sinl low-vth iruits r ssum to roun 0:2V n 1V, rsptivly. Th primry inputs r ssum to rriv simultnously n th

5 timin onstrints or primry outputs r trmin y th ritil pth ly o th sinl low-vth iruit. 5.1 Rsults or 32-it Ar Awll sin 32-it stti CMOS Ko-Ston r ws invstit s on PthMill stti timin nlysis. Th normliz tiv lk powr n stny lk powr t irnt VtH r ivn in Fiur 6 n Fiur 7, rsptivly. Th iruit tmprtur is ssum to 110 o C n 25 o C or tiv mo n stny mo, rsptivly. Rsults show tht thr is n optiml VtH, t whih mix- Vth sin thniqu n provi nrly 20% mor lk powr svins thn th orrsponin t-lvl ul thrshol thniqu. Suppos th roup numr (m) is 10 or th priority-s ktrin (PB) lorithm. ForHP worksttion, th run-tim o ktrin (BT) lorithm, priority-s ktrin (PB) lorithm, n priority sltion lorithm r 3.8s, 4s, n 18s, rsptivly. Rsults init tht th PB lorithm ivs lmost th sm lk svins s th PS lorithm, ut th run-tim is los to tht o th BT lorithm. Normliz tiv lk powr DVT, BT MVT1, BT MVT2, BT MVT2, PB MVT2, PS VtH VtL (mv) Fiur 6: Ativ lk Normliz stny lk powr DVT, BT MVT1, BT MVT2, BT MVT2, PB MVT2, PS VtH VtL (mv) Fiur 7: Stny lk Fiur 8 ivs th normliz totl powr o th mix- Vth 32-it r t irnt VtH n irnt primry input tivitis. Th totl powr n ru y out 9% n 22% t mx tivity n 0.1mx tivity, rsptivly. Fiur 9 shows th pth istriutions o th 32-it r t sinl hih-vth, sinl low-vth, n mix ul-vth onitions. Crtinly, sinl hih-vth iruit hs lss lk powr, ut th ritil ly o sinl hih-vth iruit is 30% lrr thn tht o sinl low-vth iruit. Dul-Vth iruit hs th sm ritil ly s th sinl low-vth iruit. Howvr, th ly vlus o th non-ritil pths r inrs y ssinin th hih thrshol volt to som trnsistors in non-ritil pths. Normliz powr issiptions Lk powr t mx tivity Dynmi powr t mx tivity Totl powr t mx tivity Lk powr t 0.1*mx tivity Dynmi powr t 0.1*mx tivity Totl powr t 0.1*mx tivity VtH VtL (mv) Fiur 8: Totl powr Pth Numr sinl low Vth sinl hih Vth ul Vth Dly (ns) Fiur 9: Pth istriution 3 3 () Sinl-Vth Hih-Vth Low-Vth Hih-Vth Low-Vth () MVT1 3 Hih-Vth Low-Vth Hih-Vth Low-Vth () DVT 3 Hih-Vth Low-Vth Hih-Vth Low-Vth () MVT2 Fiur 10: Bnhmrk C17 in irnt shms 5.2 Rsults or ISCAS Bnhmrk Ciruits For th ISCAS nhmrk iruits, thnoloy-mppin ws us to mp th iruits to lirry whih ontins NAND, NOR n INVERTER ts. Eh typ o t hs thr irnt with implmnttions. In our nlysis, VtL, n VtH r ssum to 0:2V n 0:3V, rsptivly. Th supply volt is 1V. Th tiv hnnl lnth is 0:32m n th t oxi thiknss is 9.8nm. Th iruit tmprtur is ssum to 110 o C. A ly look-up tl s on HSPICE simultions n lk stimtion thniqu whih urtly mols sris onnt trnsistors [9] hv n us in our nlysis. Fiur 10 illustrts th shmti o iruit C17(rom th ISCAS nhmrks) in irnt shms. Fiur 10 () is th sinl low-vth shm. Th two ritil pths o C17 r inti. Thr r 12 trnsistors n 12 trnsistors. Th tiv hnnl with or h n trnsistor is 3m n 1m, rsptivly. Th lk powr issiption or th sinl low-vth iruit o C17 is 1:0W. Th shmti o iruit C17 in t-lvl ul- Vth (DVT) shm, mix-vth typishm (MVT1), n mix-vth typ II shm (MVT2) r ivn in Fiurs 10 (), (), n (), rsptivly. Th numrs o hih Vth trnsistors r 4, 10, n 11, whil th numrs o hih Vth trnsistors r 4, 6, n 6 or DVT, MVT1, n MVT2 shms, rsptivly. Th lk powr issiptions or C17 in DVT, MVT1 n MVT2 shms r 0:726W, 0:366W, n 0:32W, rsptivly. Hn, th lk svins or C17 in DVT, MVT1 n MVT2 shms r 27:6%, 63:5%, n 68:1%, rsptivly, ompr to th sinl low thrshol shm. By usin SIS ommn \mp", iruits r mpp to lirry trtin th miniml r, whr th ts with th miniml with r prrr. Thnoloy mppin n lso hiv usin SIS ommn \mp -n 1 -AFG" to hiv miniml ly. In th ritil pth, th ts with lrr with r hosn, whil th ts in th non-ritil pths

6 Tl 1: lk powr svins or ISCAS nhmrk iruits mpp or r Ciruit PI/PO FET DVT MVT1 MVT2 Chosn # # r.(%) r.(%) r.(%) C432 36/ C499 41/ C880 60/ C / C / C / C / C / C / C / Tl 3: lk powr svins or irnt lorithms Ciruit BT l. PS l. PB l. (m=10) Chosn % CPU(s) % CPU(s) % CPU(s) C C C C C C C C C C Tl 2: lk powr svins or ISCAS nhmrk iruits mpp or ly Ciruit PI/PO FET DVT MVT1 MVT2 Chosn # # r.(%) r.(%) r.(%) C432 36/ C499 41/ C880 60/ C / C / C / C / C / C / C / my hv smllr with. Oviously, th iruit mpp or ly is mor ln thn th iruit mpp or r. Tl 1 n Tl 2 rport th lk powr svins or ISCAS nhmrk iruits whih r mpp or r n ly, rsptivly. Th ktrin lorithm is us n irnt iruit shms, suh s DVT, MVT1, n MVT2, r ompr. Mor lk rution n hiv or th iruits mpp or r us o th lrr imln in slk. Th lk svins o MVT2 shm r lrr thn thos o MVT1 shm. Th mix-vth shms provi mor lk svins thn th orrsponin t-lvl ul thrshol thniqu. For som nhmrk iruits, th itionl lk svins n mor thn 20%. Tl 3 shows th lk powr svins or irnt lorithms, suh s ktrin (BT) lorithm, priority sltion (PS) lorithm, n priority-s ktrin (PB) lorithm. MVT2 shm is us n th iruits r mpp trtin th miniml ly. Th CPU tim is or SUN UltrSPARC-II. Rsults init tht PS lorithm shows mor lk svins, ut lso tks mor CPU tim. BT lorithm is th stst on, ut it ivs lss lk svin thn th othr two lorithms. For PB lorithm, th roup numr (m) is st to 10. Th lk svins r los to thos o PS lorithm n th run-tim is similr to tht o BT lorithm. 6 Summry & Conlusion In this ppr, mix-vth CMOS iruit sin thniqu is prsnt n irnt mix-vth iruit thniqus r introu. Svrl lorithms or trnsistor lvl thrshol ssinmnt or mix-vth stti CMOS iruit sin styl r propos. A 32-it r ws simult s on PthMill timin nlysis. For ISCAS Bnhmrk iruits, ly look-up tl s on HSPICE simultions n lk stimtion thniqu whih urtly mols trnsistor stks hv n us. Rsults init tht th mix-vth CMOS sin thniqu provis out 20% mor lk svins thn th orrsponin t-lvl ul thrshol thniqu. Aknowlmnt Th uthors woul lik to thnk V. Govinrulu or th ontriution in PthMill simultions. Rrns [1] J. M. C. Stork, \Thnoloy Lvr or Ultr-Low Powr Inormtion Systms", Proins o th IEEE, Vol.83, No.4, pp , [2] A. P. Chnrksn, S. Shn n R. W. Brorsn, \Low- Powr CMOS Diitl Dsin", IEEE Journl o Soli-Stt Ciruits, Vol.27, No.4, pp.473, [3] S. Mutoh, t l., \1-V Powr Supply Hih-Sp Diitl Ciruit Thnoloy with Multithrshol-Volt CMOS", IEEE Journl o Soli-Stt Ciruits, Vol.30, No.8, pp , [4] Z. Chn, C. Diz, J. Plummr, M. Co n W. Grn, \0.18um Dul Vt MOSFET Pross n Enry-Dly Msurmnt", IEDM Dist, pp. 851, [5] L. Wi, Z. Chn, K. Roy, M.C. Johnson, Y. Y n V. D, "Dsin n Optimiztion o Dul Thrshol Ciruits or Low Volt Low Powr Applitions", IEEE Trnstions on VLSI Systms, Vol.7, No. 1, pp , 1999 [6] N. Wst n K. Eshrhin, Prinipls o CMOS VLSI Dsin: systm prsptiv, Aison-Wsly Pulishin Compny, pp , 1992 [7] Q. Wn n S. Vruhul, \Stti Powr Optimiztion o Dp Sumiron CMOS Ciruits or Dul Vt Thnoloy", Intrntionl Conrn on Computr-Ai Dsin, pp , [8] B.J. Shu, D.L. Shrttr, P.K. Ko, n M.C. Tn, \BSIM: Brkly Short-Chnnl IGFET Mol or MOS Trnsistors", IEEE J. Soli-Stt Ciruits, SC-22, No.4, pp , [9] M. Johnson, D. Somskhr, n K. Roy, \Dtrministi Estimtion o Minimum n Mximum Lk Conitions in CMOS Loi," IEEE Trnstions on Computr-Ai Dsin o IC's, pt or pulition.