ECE 523/42 - Analog Electronics University of New Mexico Solutions Homework 3 Problem 7.90 Show that when ro is taken into account, the voltage gain of the source follower becomes G v v o v sig R L r o (R L r o ) + Now, with RL removed, the voltage gain is carefully measured and found to be 0.98. Then, when RL is connected and its value is varied, it is found that the gain is halved at RL 500Ω. If the amplifier remained linear throughout this measurement, what must the values of gm and ro be? Because drain terminal is connected to ground R L r o And using T-model. We use a voltage division to determine v o R L r o v o v sig (R L r o ) + From this voltage division we obtain G v G v v o v sig R L r o (R L r o ) + When we remove R L r o G v (r o ) + G v 0.98 With R L 500Ω 500 r o G v (500 r o ) + G v 0.49
From the equation without R L we found r o 49 Substituting r o 49 in equation with R L 500Ω r o 25kΩ Therefore 49 r o.96 ma V
Problem 7.94 In an electronic instrument using the biasing scheme shown in Fig. 7.48(c), a manufacturing error reduces RS to zero. Let VDD 5 V, RG 0MΩ, and RG2 5.MΩ. What is the value of VG created? If supplier specifications allow kn to vary from 0.2 to 0.3 ma/v 2 and Vt to vary from.0 V to.5 V, what are the extreme values of ID that may result? What value of RS should have been installed to limit the maximum value of ID to.5 ma? Choose an appropriate standard 5% resistor value (refer to Appendix J). What extreme values of current now result? Using voltage division to calculate V G R G2 V G V DD R G2 + R G 5. V G 5 5. + 0 5.07V For calculating I D we use the equation for drain current For I DMIN we use k n 0.2 and V t.5v For I DMAX we use k n 0.3 and V t V I D 2 (k n ) ( W L ) (5.07 V t) 2 I DMIN (0.2)(5.07.5)2 2 I DMIN.27 ma I DMAX (0.3)(5.07 )2 2 I DMAX 2.48 ma Using the equation for drain current for calculating the new V GS using the MAX values for k n 0.3 and V t V because this will be the new MAX drain current. I D 2 (k n ) ( W L ) (V OV) 2 V OV 3.6V V GS 4.6V
Then we calculate V S V S V G V GS V S 5.07 4.6 V S 0.9V Knowing V S we can simply calculate R S R S V S I DS 0.9.5mA R S 606.6Ω R S 620Ω
Problem 7.03 Figure P7.03 shows a variation of the feedback-bias circuit of Fig. 7.50. Using a 5V supply with an NMOS transistor for which Vt 0.8 V, kn 8 ma/v 2, and λ0, provide a design that biases the transistor at ID ma, with VDS large enough to allow saturation operation for a 2V negative signal swing at the drain. Use 22MΩ as the largest resistor in the feedback-bias network. What values of RD, RG, and RG2 have you chosen? Specify all resistors to two significant digits. Using the equation for the drain current for calculating V GS and then V G I D 2 (k n ) ( W L ) (V GS V t ) 2 m 2 (8m)(V GS 0.8) 2 V GS.3V V G.3V Assuming R G2 22MΩ Using the condition for V DSMIN V DSMIN V GS V t 0.5V V DS V DSMIN + 2 2.5V I V G R G2.3 22MΩ 5.9x0 8 A Calculating R G R G V DS V G 2.5.3 20.3MΩ I 5.9x0 8 R G 20MΩ Calculating R D R D V DD V DS 5 2.5 2.5kΩ I D x0 3 R D 2.5kΩ
Problem 7.20 Figure P7.20 shows a scheme for coupling and amplifying a high-frequency pulse signal. The circuit utilizes two MOSFETs whose bias details are not shown and a 50Ω coaxial cable. Transistor Q operates as a CS amplifier and Q2 as a CG amplifier. For proper operation, transistor Q2 is required to present a 50Ω resistance to the cable. This situation is known as proper termination of the cable and ensures that there will be no signal reflection coming back on the cable. When the cable is properly terminated, its input resistance is 50Ω. What must gm2 be? If Q is biased at the same point as Q2, what is the amplitude of the current pulses in the drain of Q? What is the amplitude of the voltage pulses at the drain of Q? What value of RD is required to provide -V pulses at the drain of Q2? Calculating 2 R i2 50Ω 2 2 20 R ma i2 V If Q is biased at the same point as Q2 then 2 i D v i 20x5 x0 4 A i D 0.mA v D i D x 50 5x0 3 V v D 5 mv
In order to have v D2 v o V R D v o i D 0.mA 0kΩ R D 0kΩ
Problem 7.22 (a) The NMOS transistor in the source-follower circuit of Fig. P7.22(a) has gm 0 ma/v and a large ro. Find the open-circuit voltage gain and the output resistance. (b) The NMOS transistor in the common-gate amplifier of Fig. P7.22(b) has gm 0 ma/v and a large ro. Find the input resistance and the voltage gain. (c) If the output of the source follower in (a) is connected to the input of the common-gate amplifier in (b), use the results of (a) and (b) to obtain the overall voltage gain vo/vi. (a) For the source follower using T model and voltage division Since r o is very large v o v i R S R S + v i R out 0k 0k + 0m G v 0.99 r g o m R out 0m 00Ω v i 0k 0.k (b) For the common gate circuit and since r o is very large R in
R in 0m 00Ω Using T model and voltage division v o v i2 R D R v i G v 4.3 5k 2k 0m (c) If we connect both stages together. For the first step R L A v A v R L + R out Where R L is R in of the second stage 00 A v 00 + 00 A v 0.5 For the second stage A v2 4.3 Overall gain A v A v A v2 7.5
Problem 7.23 The MOSFET in the amplifier circuit of Fig. P7.23 has Vt 0.6 V, kn 5 ma/v 2, and VA 60 V. The signal vsig has a zero average. a) It is required to bias the transistor to operate at an overdrive voltage VOV 0.2 V. What must the dc voltage at the drain be? Calculate the dc drain current ID taking into account VA. Now, what value must the drain resistance RD have? b) Calculate the values of gm and ro at the bias point established in (a). c) Using the small-signal equivalent circuit of the amplifier, show that the voltage gain is given by v o v sig + R 2 R + R 2 R (R D r o R 2 )( R ) 2
a) At DC, v sig 0 shortcircuit. Also V GS V OV + V t V GS 0.8V From the voltage division between R and R 2 V GS V D R R + R 2 V D 4V Using the equation for the drain current taking in account VA I D 2 (k n)(v OV ) 2 ( + V DS VA ) I D 2 (5)(0.2)2 ( + 4 60 ) I D 0.07 ma Now we have the voltage and current going through R D R D V DD V D I D 0 4 0.07 ma R D 56 kω b) The equation for 2I D 2x0.07 ma V ov 0.2.07 ma V The equation for r o VA 60 I D 0.07 ma r o 560.7kΩ