R. Ludwig and G. Bogdanov RF Circuit Design: Theory and Applications 2 nd edition. Figures for Chapter 6

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R. Ludwig and G. Bogdanov RF Circuit Design: Theory and Applications 2 nd edition Figures for Chapter 6 Free electron Conduction band Hole W g W C Forbidden Band or Bandgap W V Electron energy Hole Valence band (a) Planar representation of covalent bonds (b) Energy band levels Figure 6-1 Lattice structure and energy levels of silicon. (a) schematic planar crystal arrangement with thermal breakup of one valent bond resulting in a hole and a moving electron for T > 0 K. (b) equivalent energy band level representation whereby a hole is created in the valence band W V and an electron is produced in the conduction band W C. The energy gap between both bands is indicated by W g.

Table 6-1 Effective concentrations and effective mass values at T = 300 K Semiconductor m n */m 0 m p */m 0 N C, cm 3 N V, cm 3 n i, cm 3 licon () 1.08 0.56 2.8 10 19 1.04 10 19 1.45 10 10 Germanium (Ge) 0.55 0.37 1.04 10 19 6.0 10 18 2.4 10 13 Gallium Arsenide (GaAs) 0.067 0.48 4.7 10 17 7.0 10 18 1.79 10 6

10 2 Conductivity, Ω 1 cm 1 10 0 10 2 10 4 10 6 10 8 10 10 Ge GaAs 10 12 10 14 50 0 50 100 150 200 250 Temperature, ºC Figure 6-2 Conductivity of, Ge, GaAs in the range from 50 C to 250 C.

P B Conduction band Conduction band Conduction band W C W F W F W C W D W C Valence band W V Valence band W F W V Valence band (a) Intrinsic (b) n-type (c) p-type W A W V Figure 6-3 Lattice structure and energy band model for (a) intrinsic, (b) n-type, and (c) p-type semiconductors at no thermal energy. W D and W A are donor and acceptor energy levels.

Electric field Hole diffusion current p-type I F n-type Electron diffusion current Space charge x = 0 Space charge x Figure 6-4 Current flows in the pn-junction.

p-type n-type Space charge Space charge x = 0 d p d n (a) pn-junction with space charge extent x n, p p p = N A (majority carrier) n n = N D (majority carrier) n p < < p p d p d n p n < < n n (b) Acceptor and donor concentrations x (x) d p d n x qn A qn D (c) Polarity of charge density distribution E d p d n x E 0 = qn A d p /( r 0 ) (d) Electric field distribution Figure 6-5 The pn-junction with abrupt charge carrier transition in the absence of an externally applied voltage.

V(x) V diff d p d n x (e) Barrier voltage distribution Figure 6-5 The pn-junction with abrupt charge carrier transition in the absence of an externally applied voltage. (Continued)

p n p n Space charge distribution in the pn-junction E E x x Electric field distribution in the pn-junction V V V A V diff x d p d n d p d n Voltage distribution in the pn-junction (a) Reverse biasing (V A < 0) (b) Forward biasing (V A > 0) V A x Figure 6-6 directions. External voltage applied to the pn-junction in reverse and forward

7 6 Junction capacitance C, pf 5 4 3 2 1 V diff 0 5 4 3 2 1 0 Applied voltage V A, V 1 Figure 6-7 The pn-junction capacitance as a function of applied voltage.

I/I 0 7 p I V A n 6 5 4 3 2 1 2.0 1.5 1.0 0.5 0.5 1.0 1.5 2.0 1 V A /V T Figure 6-8 Current-voltage behavior of pn-junction based on Shockley equation.

I W C W F W F W V V A Metal p-semiconductor (a) Energy band model (b) Voltage-current characteristic Figure 6-9 Metal electrode in contact with p-semiconductor.

Free electron energy level q W S W F W M W C W F W F W b qv d qv C W C W F W V W V Metal n-semiconductor x Metal n-semiconductor x (a) d s (b) Figure 6-10 Energy band diagram of Schottky contact, (a) before and (b) after contact.

Table 6-2 Work function potentials of some metals Material lver (Ag) Aluminum (Al) Gold (Au) Chromium (Cr) Molybdenum (Mo) Nickel (Ni) Palladium (Pd) Platinum (Pt) Titanium (Ti) Work Function Potential, V M 4.26 V 4.28 V 5.10 V 4.50 V 4.60 V 5.15 V 5.12 V 5.65 V 4.33 V

Metal contact Depletion region Metal contact O 2 O 2 C J R J n-type epitaxial layer n + -type substrate n n + R epi R sub R S C g Metal contact Metal contact Figure 6-11 Cross-sectional view of Schottky diode.

R J L S R S C J C g Figure 6-12 Circuit model of typical Schottky diode under forward bias.

Metal contact O 2 O 2 n-type epitaxial layer p-type ring n + -type substrate Metal contact Figure 6-13 Schottky diode with additional isolation ring suitable for very high frequency applications.

p + O 2 I = n p + I = n O 2 n + n + -type substrate (a) mplified structure of a PIN diode (b) Fabrication in mesa processing technology Figure 6-14 PIN diode construction.

Z G = Z 0 V G R J (V Q ) Z L = Z 0 (a) Forward bias Z G = Z 0 V G C J Z L = Z 0 (b) Reverse bias (isolation) Figure 6-15 PIN diode in series connection.

DC bias C B RFC C B RF in RF out PIN Diode RFC (a) Series connection of PIN diode DC bias C B RFC C B RF in RF out PIN Diode RFC C B (b) Shunt connection of PIN diode Figure 6-16 Attenuator circuit with biased PIN diode in series and shunt configurations.

1.6 1.4 1.2 Transducer loss, db 1 0.8 0.6 0.4 0.2 V G Z G = Z 0 R J (V Q ) Z L = Z 0 0 0 2 4 6 8 10 12 14 16 18 20 Junction resistance R J, Ω Figure 6-17 Transducer loss of series connected PIN diode under forward-bias condition. The diode behaves as a resistor.

70 Z G = Z 0 Transducer loss, db 60 50 40 30 20 CJ = 0.1 pf 0.3 pf 0.6 pf 1.3 pf 2.5 pf V G C J Z L = Z 0 10 0 10 MHz 100 MHz 1 GHz 10 GHz 100 GHz Frequency Figure 6-18 Transducer loss of series connected PIN diode under reverse-bias condition. The diode behaves as a capacitor.

0.20 Capacitance C V, pf 0.18 0.16 0.14 0.12 0.10 R S C V (V Q ) C V0 = 0.2 pf, V diff = 0.5 V 0.08 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 Biasing voltage V Q, V 0.4 0.2 0 Figure 6-19 mplified electric circuit model and capacitance behavior of varactor diode.

R I V V A Varactor V out V A, I V V A I V t V out t V t Figure 6-20 Pulse generation with a varactor diode.

+ + n + p I p + Hole + E W Impact Electron (a) Layer structure and electric field profile x + (b) Impact ionization Figure 6-21 IMPATT diode behavior.

V A π 2π 3π 4π T I ion I π 2π 3π 4π T π 2π 3π 4π T Figure 6-22 Applied voltage, ionization current, and total current of an IMPATT diode.

R L C L C ion L ion Figure 6-23 Electric circuit representation for the IMPATT diode.

W Cp W g n + W Vp p + W Fn W Cn V diff W Fp W g + W Vn d Figure 6-24 Tunnel diode and its band energy representation.

B E B E B E B E B E B p + p + p + p + p + p + p-base n + n + n + n + n + n-type collector C (a) Cross-sectional view of a multifinger bipolar junction transistor Base bonding pad n + emitter contacts Metallization p + base contacts p base well Emitter bonding pad (b) Top view of a multifinger bipolar junction transistor Figure 6-25 Interdigitated structure of high-frequency BJT.

Dielectric E n + n-gaalas C B B n + p-substrate n p + Figure 6-26 Cross-sectional view of a GaAs heterojunction bipolar transistor involving a GaAlAs-GaAs interface.

Electron recombination Hole recombination B Hole injection C electron collection electron diffusion electron injection n-type collector p-type base n-type emitter B I B V CB E E E (a) (b) (c) + C + I C V + CE V BE I E B C Figure 6-27 npn transistor: (a) structure with electrical charge flow under forward active mode of operation, (b) transistor symbol with voltage and current directions, and (c) diode model.

I C R C R B I B + + + V V BE BB + V CE V CC (a) Biasing circuit for npn BJT in common-emitter configuration I B Load line 1/R B I C Load line 1/R C V BB /R B V CC /R C I B4 I B Q Q V BE Q point V BB (b) Input characteristic of transistor V BE I C Q Saturation Q V CE Q point Cutoff V CC I B3 I B2 I B1 (c) Output characteristic of transistor Increasing base current V CE Figure 6-28 Biasing and input, output characteristics of an npn BJT.

Table 6-3 BJT parameter nomenclature Parameter description Emitter (n-type) Base (p-type) Doping level E N D B N A Collector (n-type) C N D Minority carrier concentration in thermal equilibrium E p n0 2 E B = n i ND n p0 2 B C = n i NA p n0 = 2 C n i ND Majority carrier concentration in thermal equilibrium E n n0 B p p0 C n n0 Spatial extent d E d B d C

Forward-biased junction B Reverse-biased junction E n B p n n E p (0) p n (0) C I E C I C B p n 0 E p n0 n p0 x = d E x = 0 x = d B x = d B + d C x Figure 6-29 Minority carrier concentrations in forward active BJT.

Reverse-biased junction B Forward-biased junction n p B C n p (d B ) p n (d B ) n E C I E E p n 0 B n p0 C p n0 I C x = d E x = 0 x = d B x = d B + d C x Figure 6-30 Reverse active mode of BJT.

20 Transition frequency f T, GHz 16 12 8 4 0 1 10 Collector current I C, ma Figure 6-31 Transition frequency as a function of collector current for the 17 GHz npn wideband transistor BFG403W (courtesy of NXP).

140 Current gain I C /I B 120 100 80 60 40 20 T j = 100 C T j = 50 C T j = 0 C T j = 50 C T j = 150 C 0 0 1 2 3 4 5 6 Collector current I C, ma Figure 6-32 Typical current gain β F as a function of collector current for various junction temperatures at a fixed V CE.

10 T j = 150 C Base current I B, ma 8 6 4 T j = 100 C T j = 50 C T j = 0 C 2 T j = 50 C 0 0.5 1.0 1.5 2.0 Base-emitter voltage V BE, V Figure 6-33 Typical base current as a function of base-emitter voltage for various junction temperatures at a fixed V CE.

Heat sink Emitter R thjs Ceramic cover Base P th R thjs T j R thcs Die R thcs T c R thha Power BJT R thha T h T a Collector T a Figure 6-34 Thermal equivalent circuit of BJT.

I C I Cmax P Vmax = V CEmax I Cmax SOAR V CElimit V CE Figure 6-35 Operating domain of BJT in active mode with breakdown mechanisms.

Insulator Source Gate Drain n + p-type substrate n + induced n-channel (a) Metal insulator semiconductor FET (MISFET) Source Gate Drain Insulator n n + p + n + p + substrate (b) Junction field effect transistor (JFET) Source Gate Drain n + n + n Semi-insulating layer Buffer layer (c) Metal semiconductor FET (MESFET) Figure 6-36 Construction of (a) MISFET, (b) JFET, and (c) MESFET. The shaded areas depict the space charge domains.

S + V GS Low V DS + G D S + V GS High V DS + G D n + y d S (y) n + d n + d S (y) n + L L (a) Operation in the linear region. (b) Operation in the saturation region. Figure 6-37 Functionality of MESFET for different drain-source voltages.

D I Dsat /I DSS 1 I D Linear Saturation V GS = 0 G V GS < 0 S S V GS / V T0 1 (a) Circuit symbol (b) Transfer characteristic (c) Output characteristic V DS Figure 6-38 Transfer and output characteristics of an n-channel MESFET.

7 Saturation drain current I Dsat, A 6 5 4 3 2 1 Quadratic law approximation V T0 = 3.44 Exact formula 0 4 3.5 3 2.5 2 1.5 1 0.5 0 Gate-source voltage V GS, V Figure 6-39 Drain current versus V GS computed using the exact and the approximate equations (6.86) and (6.87).

4 3.5 V DS = V DSsat I D = I Dsat (V DS ) V GS = 1 V Drain current I D, A 3 2.5 2 1.5 1 = 0.03 = 0 V GS = 1.5 V V GS = 2 V 0.5 V GS = 2.5 V 0 0 1 2 3 4 5 Drain-source voltage V DS, V Figure 6-40 Drain current as a function of applied drain-source voltage for different gate-source biasing conditions.

I D I Dmax I D1 1 V DS = V Dsat P max I D2 2 I D3 3 V DS3 V DS1 V DS2 V DSmax V DS Figure 6-41 MESFET. Typical maximum output characteristics and three operating points of

+ + V GS V DS Inversion layer t ox S G D Gate oxide O 2 G D B n + n + S p-substrate B L (a) Depletion region G D S (b) Figure 6-42 Cross-sectional view of an n-channel MOS transistor: (a) physical construction, (b) symbols.

Source Gate Drain 0.1 µm 300 µm 1 µm n + n-gaalas GaAlAs n + GaAs Semi-insulating GaAs 2DEG 30 nm 10 nm d 0 x y Figure 6-43 Generic heterostructure of a depletion-mode HEMT.

Schottky contact W W H W F W GaAlAs W GaAs 2DEG W G W C d 0 (a) Energy band diagram x W F GaAlAs GaAs (b) Close-up view of conduction band Figure 6-44 Energy band diagram of GaAlAs-GaAs interface for an HEMT.

30 V GS = 0 V 25 Drain current I D, ma 20 15 10 5 V GS = 0.25 V V GS = 0.5 V V GS = 0.75 V V GS = 1 V 0 0 1 2 3 4 5 Drain-source voltage V DS, V Figure 6-45 Drain current in a GaAs HEMT.

Drain lead Source and heat-sink contact Chips Gate lead 5 mm (a) Bond wire MOS capacitor Drain metallization Source finger Drain finger Inductor Die Inductor MOS capacitor 1 mm Gate metallization Bond wire Gate finger 100 µm (b) (c) Figure 6-46 The internal structure of the LDMOS power transistor BLF4G22-100 at three levels of magnification: (a) overall package, (b) die interconnections, and (c) transistor die (courtesy of NXP).

Figure 6-47 The power transistor mounted on a demonstration board.