Low-Power, High-Speed MOS Analog es G41/43/4 ESRIPTION The G41/43/4 monolithic analog switches were designed to provide precision, high performance switching of analog signals. ombining low power (.3 µw, typ) with high speed (t ON : ns, typ), the G41 series is ideally suited for portable and battery powered industrial and military applications. Built on the proprietary high-voltage silicon-gate process to achieve high voltage rating and superior switch on/off performance, break-before-make is guaranteed for the SPT configurations. An epitaxial layer prevents latchup. Each switch conducts equally well in both directions when on, and blocks up to 3 V peak-to-peak when off. Onresistance is very flat over the full ± 1 V analog range, rivaling JFET performance without the inherent dynamic range limitations. The three devices in this series are differentiated by the type of switch action as shown in the functional block diagrams. FEATURES 44 V Supply Max Rating ± 1 V Analog Signal Range On-Resistance - r S(on) : 3 Ω Low Leakage - I (on) : 4 pa Fast ing - t ON : ns Ultra Low Power Requirements - P :.3 µw TTL, MOS ompatible Single Supply apability BENEFITS Wide ynamic Range Break-Before-Make ing Action Simple Interfacing APPLIATIONS Audio and Video ing Sample-and-Hold ircuits Battery Operation Test Equipment ommunications Systems PBX, PABX Pb-free Available RoHS* OMPLIANT FUTIONAL BLOK IAGRAM AN P ONFIGURATION G41 ual-in-line and SOI 1 1 16 2 1 1 3 14 4 13 12 6 11 2 8 9 Key 4 6 8 G41 L 1 1 3 2 1 2 19 9 11 12 13 18 1 16 1 14 Two SPST es per Package TRUTH TABLE Logic OFF 1 ON Logic "".8 V Logic "1" 2.4 V Top View 2 Top View * Pb containing terminations are not RoHS compliant, exemptions may apply S-11 Rev. H, 11-Jun- 1
G41/43/4 FUTIONAL BLOK IAGRAM AN P ONFIGURATION G43 ual-in-line and SOI 1 1 16 2 1 1 3 3 14 S 3 4 13 S 4 12 4 6 11 2 8 9 Key 3 S 3 S 4 4 4 6 8 G43 L 1 1 3 2 1 2 19 9 11 12 13 2 18 1 16 1 14 Two SPT es per Package TRUTH TABLE Logic SW 1, SW 2 SW 3, SW 4 OFF ON 1 ON OFF Logic "".8 V Logic "1" 2.4 V Top View Top View G4 G4 ual-in-line and SOI 1 1 16 2 1 1 3 3 14 S 3 4 13 S 4 12 4 6 11 2 8 9 Key 3 S 3 S 4 4 4 6 8 L 1 1 3 2 1 2 19 9 11 12 13 18 1 16 1 14 Two PST es per Package TRUTH TABLE Logic "".8 V Logic "1" 2.4 V Logic OFF 1 ON 2 Top View Top View 2 S-11 Rev. H, 11-Jun-
G41/43/4 ORERG FORMATION Temp Range Package Part Number G41 G43 G4-4 to 8 16-Pin Plastic IP - 4 to 8-4 to 8 16-Pin Plastic IP 16-Pin Narrow SOI 16-Pin Plastic IP 16-Pin Narrow SOI G41J G41J-E3 G43J G43J-E3 G43Y G43Y-E3 G43Y-T1 G43Y-T1-E3 G4J G4J-E3 G4Y G4Y-E3 G4Y-T1 G4Y-T1-E3 ABSOLUTE MAXIMUM RATGS Parameter Limit Unit to 44 to 2 ( -.3) to () +.3 V igital Inputs a, V S, V or () - 2 to () + 2 3 ma, whichever occurs first urrent (Any Terminal) ontinuous 3 urrent, S or (Pulsed 1 ms, % duty) ma Storage Temperature (J, Y Suffix) - 6 to 12 Power issipation (Package) b 16-Pin Plastic IP c 4 16-Pin SOI d 6 mw Notes: a. Signals on S X, X, or X exceeding or V will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads welded or soldered to P Board. c. erate 6 mw/ above. d. erate.6 mw/ above. S-11 Rev. H, 11-Jun- 3
G41/43/4 SPEIFIATIONS a Test onditions Unless Specified = 1 V, V = Suffix - 4 to 8 Parameter Symbol = V, V = 2.4 V,.8 V f Temp b Typ c Min d Max d Unit Analog Analog Signal Range e V ANALOG Full - 1 1 V rain-source On-Resistance Δ rain-source On-Resistance Off Leakage urrent r S(on) Δr S(on) I S(off) I (off) I S = - ma, V = ± V = 13. V, = - 13. V I S = - ma, V = ± V, V = 16. V, = - 16. V = 16. V, = - 16. V V = ± 1. V, V S = ± 1. V = 16. V, = - 16. V hannel On Leakage urrent I (on) V S = V = ± 1. V igital ontrol V Input urrent V Low I under test =.8 V IL All Other = 2.4 V V Input urrent V High I under test = 2.4 V IH All Other =.8 V ynamic haracteristics Turn-On Time t ON R L = 3 Ω, L = 3 pf See Figure 2 Break-Before-Make Time elay (G43) harge Injection Q L = nf V gen = V, R gen = Ω Off Isolation Reject Ratio OIRR R L = Ω, L = pf f = 1 MHz Source Off apacitance S(off) f = 1 MHz, V S = V Notes: a. Refer to PROESS OPTION FLOWHART. b. = 2, Full = as determined by the operating temperature suffix. c. Typical values are for ESIGN AI ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. V = input voltage to perform proper function. Full Full Hot Hot Hot 3 4 3 3 -.1 -. - -.1 -. - -.4-1 -.. 1 Full. - 1 1 Full. - 1 1 Turn-Off Time t OFF 3 t R L = 3 Ω, L = 3 pf 3 Ω na µa ns 6 p 2 hannel-to-hannel rosstalk X TALK 9 12 rain Off apacitance (off) 12 hannel On apacitance, S(on) 39 Power Supplies Positive Supply urrent I+ Full Negative Supply urrent Logic Supply urrent I- I L = 16. V, = - 16. V Full V = or V Full Ground urrent I Full.1 1 -.1-1 -.1 1 -.1-1 - db pf µa Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 4 S-11 Rev. H, 11-Jun-
G41/43/4 TYPIAL HARATERISTI, unless otherwise noted 6 = 1 V = -1 V 3. 3 SW1, 2 2. V T (V) 4 3 SW3, 4 V TH (V) 2 1. = V 2 1 = V 1. 2 4 6 8 12 14 16 18 Logic Supply (V) Input ing Threshold vs. Logic Supply Voltage 1 2 2 3 3 () Input ing Threshold vs. Supply Voltages r S(on) rain-source On-Resistance ( Ω ) 4 4 3 3 2 2 1 8 2 = 1 V, = VL = V - 4 r S(on) rain-source On-Resistance (Ω) 6 4 3 2 T A = 2 ± 6 V ± V ± 12 V ± 1 V ± 2 V ± 22 V - 1. -. -.... 1. - 2-1 - 1 26 V rain V oltage (V) r S(on) vs. V and Temperature V rain V oltage (V) r S(on) vs. V and Power Supply Voltage r S(on) rain-source On-Resistance (Ω ) 9 8 6 4 3 2 T A = 2. V V 12 V 1 V 2 V 22 V Q (p) 4 3 2 - - 2 L = nf pf 1 nf 1 2 2 V rain Voltage (V) r S(on) vs. V and Power Supply Voltage ( = V) - 3-1 - - 1 V S Source V oltage (V ) harge Injection vs. Analog Voltage S-11 Rev. H, 11-Jun-
G41/43/4 TYPIAL HARATERISTI, unless otherwise noted p p = 1 V = -1 V = V V = ± 14 V Is (off) 4 2 Id (on) Id (off) Is (off) I (off) p Id (on) Id (off) (pa) I S, I - 2-4 - 6-8 1p - 4-2 2 4 6 8 Temperature ( ) Leakage urrent vs. Temperature - - 1. -. -.... 1. V or V S rain or Source Voltage (V) Leakage urrent vs. Analog Voltage na 1 na = 1 V = = V I+ I- 12 V + = 1 V = = V t ON I+, I-, I L (A) pa pa I L t ON, t OFF (ns) 8 6 4 V S = V V S = V V S = - V t OFF 2 V S = - V 1 pa - 4-2 2 4 6 8 T A Temperature ( ) Supply urrent vs. Temperature - 4-2 2 4 6 8 T A Temperature ( ) ing Time vs. Temperature* t ON, t OFF (ns) 18 16 14 12 V S = - V V S = V 8 t ON 6 V S = V 4 t OFF 2 V S = - V ± ± ± 1 ± 2 ± 2, V Positive and Negative Supplies (V) ing Time vs. Power Supply Voltage* *Refer to Figure 2 for test conditions. t ON, t OFF (ns) 3 2 V VS = V 24 2 18 - V 12 9 6 t ON 3 - V V t OFF 1 2 2 Positive Supply (V) ing Time vs. Positive Supply Voltage* 6 S-11 Rev. H, 11-Jun-
G41/43/4 TYPIAL HARATERISTI, unless otherwise noted ma ma 1 ma Supply urrent (A) μa μa 1 μa na na 1K K K 1M M Frequency (Hz) Supply urrent vs. ing Frequency SHEMATI IAGRAM (TYPIAL HANNEL) S V Level Shift/ rive V V Figure 1. S-11 Rev. H, 11-Jun-
G41/43/4 TEST IRUITS is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing edge of the output waveform. + V + 1 V Logic Input V % t f < 2 ns t f < 2 ns ± V S Input* V S 9 % t OFF R L 1 kω L 3 pf Output Input* V -V S t ON 9 % L (includes fixture and stray capacitance) R O = V S R L + r S(on) *V S = V for t ON, V S = - V for t OFF Note: Logic input waveform is inverted for switches that have the opposite logic sense control Figure 2. ing Time V S1 V S2 + V + 1 V 1 2 2 R L1 L1 1 Logic Input Output 3 V V V S1 1 V V S2 2 % 9 % 9 % R L2 L2 Output V t t L (includes fixture and stray capacitance) Figure 3. Break-Before-Make + V + 1 V R g S Δ V g 3 V L nf On Off On Q = Δ x L Figure 4. harge Injection 8 S-11 Rev. H, 11-Jun-
G41/43/4 TEST IRUITS + V + 1 V + V + 1 V V S V S S R g = Ω Ω R g = Ω V, 2.4 V R L Ω R L.8 V Off Isolation = 2 log = RF bypass V S X TALK Isolation = 2 log = RF bypass V S Figure. Off Isolation Figure. rosstalk + V + 1 V + V + 1 V V S R g = Ω V, 2.4 V S R L Ω V, 2.4 V S Meter HP4192A Impedance Analyzer or Equivalent f = 1 MHz = RF bypass Figure 6. Insertion Loss Figure 8. apacitances S-11 Rev. H, 11-Jun- 9
G41/43/4 APPLIATIONS + V + 1 V + V + 1 V Source 1 Left Right S 3 1 3 Left e in S 3 1 3 + - e out Left 1 1 1 Source 2 Right S 4 2 4 Right TTL Integrate/ Reset S 4 2 4 TTL hannel Select G43 Slope Select G43 2 Figure 9. Stereo Source Selector Figure. ual Slope Integrator ual Slope Integrators: The G43 is well suited to configure a selectable slope integrator. One control signal selects the timing capacitor 1 or 2. Another one selects e in or discharges the capacitor in preparation for the next integration cycle. + V + 1 V 1 Band-Pass ed apacitor Filter: Single-pole double-throw switches are a common element for switched capacitor networks and filters. The fast switching times and low leakage of the G43 allow for higher clock rates and consequently higher filter operating frequencies. e in lock S 3 3 1 2 S 4 4 G43 + - e out Figure 11. Band-Pass ed apacitor Filter S-11 Rev. H, 11-Jun-
G41/43/4 APPLIATIONS Peak etector: A 3 acting as a comparator provides the logic drive for operating SW 1. The output of A 2 is fed back to A 3 and compared to the analog input e in. If e in > e out the output of A 3 is high keeping SW 1 closed. This allows 1 to charge up to the analog input voltage. When e in goes below e out A 3 goes negative, turning SW 1 off. The system will therefore store the most positive analog input experienced. Reset SW 2 e in A1 + SW 1 R 1 + A 2 e out + A 3 G41 1 Figure 12. Positive Peak etector maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http:///ppg?49. S-11 Rev. H, 11-Jun- 11
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