A Modeling Environment for the Simulation and Design of Charge Redistribution DACs Used in SAR ADCs

204 UKSim-AMSS 6th International Conference on Computer Modelling and Simulation A Modeling Environment for the Simulation and Design of Charge Redistribution DACs Used in SAR ADCs Stefano Brenna, Andrea Bonfanti, Andrea L. Lacaita Dip. di Elettronica, Informazione e Bioingegneria Politecnico di Milano, Milano, Italy, 2033 e-mail: stefano.brenna@polimi.it Andrea Bonetti ams International AG Rapperswil, Switzerland, 8640 e-mail: andrea.bonetti@ams.com Abstract The optimal design of successive approximation register (SAR) analog-to-digital converters (ADCs) requires the accurate estimate of nonlinearity and parasitic capacitance effects in the feedback charge-redistribution digital-to-analog converters (DACs). Since the effects of both mismatch and stray capacitances depend on the specific array topology, complex calculations, custom modeling and heavy simulations in common circuit design environments are often required. This paper presents a novel MATLAB-based numerical tool to assist the design of classic, split and with attenuation capacitor binary weighted capacitive array topologies with an even number of bits from 6 to 4. The tool allows to perform both parametric and statistical simulations taking into account capacitive mismatch and parasitic capacitances in order to compute both differential- (DNL) and integral nonlinearity (INL). Signal-to-noise plus distortion ratio (SNDR) and Effective Number of Bits (ENoB) degradation due to static non-linear effects is also estimated. An excellent agreement with the results obtained by the available circuit simulators (e.g. Cadence Spectre) is shown but featuring up to 0 4 -times shorter simulation time. Keywords- analog-to-digital conversion; numerical simulations; charge redistribution successive approximation converters. I. INTRODUCTION In power-limited applications, such as portable instruments, wireless sensor networks or implantable biomedical systems, the use of ultra low-power analog-to-digital converters (ADCs) extends the battery life and limits heating phenomena. Due to their energy efficiency, successive approximation register (SAR) converters represent the best choice when moderate resolution and speed are required. The performance requirements of such converters are represented by static metrics, such as differential-non-linearity (DNL) and integral-non-linearity (INL), and by dynamic metrics, such as signal-to-noise-plus-distortion ratio (SNDR) and effective-number-of-bits (ENoB). All of these parameters mainly depend on the quality of the capacitive array, which implements the feedback charge-redistribution (CR) digital-to-analog converter (DAC). In the last decade, several novel CR-DAC topologies have been proposed for the design of SAR ADCs with outstanding efficiency [], [2]. The capacitive DAC plays a dominant role in degrading the overall performance of a SAR ADC as long as it is affected by mismatch and parasitic capacitances. Mismatch effects on DNL and INL can be considered statistical and they are well known for the most common array topologies [3]. Differently, the parasitic capacitance contribution is deterministic and strongly depends on the array architecture. However, precise relationships that quantify the effects of both capacitance mismatch and parasitic capacitances on static and dynamic metrics still lacks. Thus, the designer has to size the DAnit capacitance handling complex equations to target the desired requirements and quantify the converter nonlinearities running long transient simulations. Unfortunately, in common circuit design and simulation environments, like Cadence, such simulations are quite timeconsuming and require heavily post-processing of the raw data, limiting the design time of the converter. Moreover, statistical simulations, like Monte Carlo analyses, are quite impractical since they require a large number of runs, at least 00, to achieve confident results. This paper presents a MATLAB-based numerical tool to assist the design of the capacitive DAC adopted in SAR ADCs. The proposed tool implements the model of the three most common DAC topologies, such as the Classic Binary Weighted (CBW) [4], the Split Binary Weighted (SBW) [5] and the Binary Weighted with Attenuation Capacitor (BWA) [6] array, both single-ended and fully-differential, and allows to choose the switching algorithm between the conventional and the monotonic scheme [7]. The numerical models take into account all possible mismatch and parasitic effects, giving the possibility to estimate by means of both statistical and parametric simulations the converter DNL, INL, SNDR, ENoB and power consumption. The paper is organized as follows. In Section II, a brief overview of the array topologies is given, resuming the effects of mismatch and parasitic capacitances on both DNL and INL. Section III is devoted to describe how the different array models are implemented and simulated with the proposed tool. Section IV shows the most significant results, which are in agreement with Cadence Spectre analyses but achieved with a considerable time saving. Finally, conclusions are drawn in Section V. II. CONVERTER TOPOLOGIES In a generic N-bit capacitive DAC, as the one shown in Fig., each digital code is associated with a particular configuration of the bottom switches that produces the 978--4799-4923-6/4 $3.00 204 IEEE DOI 0.09/UKSim.204.23 56

Out C (N-) = 2 C MSB Out (N-) (N-2) 2 Cu 2 Cu 4 2 D N D N- D 3 D 2 D V REF,N Figure : Schematic of a N-bit CBW array. C par (N-2) (N-2) 2 C 2C C C 2 C 2C C C D MSB,N D MSB,2 D MSB,2 D MSB, D N- D 2 D V REF,N Figure 2: Schematic of a N-bit SBW array. C par corresponding output voltage. In an equivalent SAR ADC implemented by means of such a DAC in the feedback path, this voltage marks an input transition level between two adjacent digital codes. It derives that the conversion accuracy depends on the actual size of each capacitive bank. As a consequence of the technologic mismatch and parasitics, the capacitance of each block can differ from its nominal value and can be in general expressed as 2 i C i =2 i C par,i δ j i =,..., N () where C par,i is the parasitic capacitance related to i th capacitive block and δ j is the mismatch equivalent capacitance affecting the unit capacitor. The effect of the parasitic capacitances C par,i can be considered deterministic, depending on layout inaccuracies, capacitor geometry and wirings. On the contrary, the capacitance mismatch can be modeled as a Gaussian distribution of the unit capacitor value with a mean equal to the nominal capacitance,, and a standard deviation equal to [8] σ C = k c 2A = k c cspec 2, (2) k c,, A and c spec being the Pelgrom mismatch coefficient, the unit capacitance, the area and the specific capacitance, respectively. In presence of mismatch or parasitics, the DAC output voltage levels differ from their ideal values being not equally spaced and determining a nonlinearity in the ADC input-output characteristic. Another important parasitic in the charge-redistribution array is the stray capacitance connected to top-plate node of the array to a fixed voltage node, e.g. C par in Fig.. This parasitic capacitance causes a gain error in the converter characteristic but in some ADC topologies [3] it can also affect the converter nonlinearity. A. Conventional Binary Weighted Array (CBW) The classic binary weighted array [4], depicted in Fig., is the most common topology, its linearity being affected only by the mismatch and parasitic capacitances connected between the top- and the bottom-plate nodes of each capacitance block, C i. The statistical DNL and INL depend on the technology mismatch and vary with the output code. In a single-ended configuration, the maximum standard deviation of the DNL occurs in correspondence of the converter midcode, being [3], [5] σ DNL,CBW =2 N σ C 2, (3) C par,main Out Main-DAC C att Sub-DAC ( 2 m -) ( Cu 2 2 l -) Cu 2 D lm D l2 D l D l D 2 D V REF,N Figure 3: Schematic of a (m l)-bit BWA array. C par,sub while the correspondent INL maximum standard deviation is σ INL,CBW =2 N 2 σc. (4) In a fully-differential configuration, these results have to be divided by a factor 2 [3]. In this array topology, the parasitic capacitance related to the top-plate node, C par, causes a difference between two adjacent output voltage levels to be smaller than the nominal value. This turns into a gain error without affecting the converter linearity. B. Split Binary Weighted Array (SBW) The split DAC topology [5] is shown in Fig. 2. It consists of a binary weighted array where the MSB capacitor implements a binary weighted sub-array that perfectly reflects the structure of the remaining banks. This DAC topology features an improved switching efficiency [5] and also a reduced impact of the capacitance mismatch. In fact, the maximum standard deviation of DNL and INL, which still occurs at the mid-code, is a factor 2 lower than in the CBW array topology [5] being σ DNL,SBW =2 N 2 σc (5) σ INL,SBW =2 N 2 2 σc. (6) These relations are referred to a single-ended configuration while a fully-differential topology is a further 2-factor less sensitive to mismatch. Moreover, as in the CBW array, only the parasitics connected between top- and bottomplate nodes of each array capacitor limit the converter nonlinearity. C. Binary Weighted Array with Attenuation Capacitor (BWA) A single-ended BWA array [6] is shown in Fig. 3. An attenuation capacitor C att divides the DAC into two binary weighted arrays, main- and sub-dac, of m and l capacitors, respectively. In this work, we ll refer to the architecture 562

shown in Fig. 3, with the same number of bits in the mainand sub-dac (i.e. m = l = N/2) and C att =, which has been shown to be the most energy efficient [3] among all the possible choices. For the same unit capacitance, this topology is more sensitive to capacitance mismatch with respect to CBW and SBW arrays because of the reduction of the overall DAC capacitance. In fact, the maximum σ DNL and σ INL are σ DNL,BWA =2 3N 4 σc (7) σ INL,BWA =2 3N 4 σc (8) which are a factor 2 N 2 larger than in the conventional topology. As far as the parasitic effect, the linearity is degraded also by the stray capacitance connected to the top-plate node of the sub-dac, C par,sub in Fig. 3, which determines a dependence on the input code of the DAC output voltage, while the parasitic capacitance connected to the main-dac, C par,main, only affects the converter gain [3]. III. CSA MATLAB SIMULATION TOOL The proposed simulation platform (CSAtool, Chargeredistribution SAR ADC tool) is implemented in MAT- LAB and allows to evaluate the linearity, either static and dynamic, and the array power consumption of each array topology. Both statistical and deterministic effects due to capacitance mismatch and parasitics can be taken into account once evaluating the ADC performance. The tool provides a graphic user interface (GUI) which is shown in Fig. 4. A behavioral model is defined for each array topology and for a number of bits from 6 to 4. The model does not simply implement the known equations that estimate the nonlinearity (maximum standard deviation of DNL and INL) and the average power consumption of the different topologies. It reproduces the behavior of a specific circuit architecture, which is described by functional capacitive blocks, including the effects of mismatch and parasitics (see Fig. 5). The simulations can be performed with a high degree of customization, giving the possibility to accurately evaluate the impact of mismatch, through both single or multiple statistical runs, and also of the parasitics of each specific array capacitor, thus representing a suitable alternative to Cadence Monte Carlo and post-layout simulations. This section is devoted to the description of the different converter models that are implemented in the proposed tool. A. CBW model In a generic SAR ADC, the analog-to-digital conversion is effectively performed by comparing the input analog voltage signal with subsequent voltage levels generated by the capacitive DAC. For a N-bit converter, the input signal is compared with N successive DAC output levels. In a conventional binary weighted topology, the DAC output voltage at each conversion step can be written as DAC out,cbw = FSR H (9) where FSR is the full scale range of the converter and H, as shown in Fig. 5, is the scalar product H = C tot C C D (0) par where C tot is the total capacitance of the array, C par the parasitic capacitance shown in Fig., C the vector of the array capacitances C i (see ()) and D the vector of the digital word updated at each conversion cycle, C = [ ] C... C N () D = [ ] D... D N (2) The digital word D, which encodes the DAC output levels at each conversion step, is determined by the adopted switching algorithm. By means of (0), () and (2), it is possible to compute the ADC conversion characteristic. B. SBW model The simple model described in the previous section can be extended to the SBW architecture of Fig. 2. The MSB capacitor is implemented as a sub-array and the switching scheme differs from the conventional algorithm [5]. Thus, the DAC output voltage can be expressed as DAC out,sbw = FSR (H MSB H,MSB ), (3) H MSB and H,MSB being coefficients related to the MSB and the residual capacitance array, respectively, H MSB = C tot C C MSB D MSB (4) par H,MSB = C tot C C,MSB D,MSB. (5) par Thus, the conversion voltage level is set by two different N-bit words, DMSB and D,MSB, and two vectors of capacitances, CMSB and C,MSB, related to the MSB sub-array and to the residual array, respectively. C. BWA model As for as the BWA topology concerns, two equal capacitive arrays must be considered: the main-dac, which is connected to the MSB switches, and the sub-dac, related to the least significant bits. Let us indicate as C tot,main and C tot,sub to the overall capacitance of the main-dac and of the sub-dac, respectively, and as C par,main and C par,sub the parasitic capacitance at the top-plate node of the corresponding DAC (see Fig. 3). Due to the presence of the attenuation capacitor, C att, the sub-dac contribution to the overall DAC output voltage is reduced by an attenuation factor AR, C att AR =, (6) C tot,main C par,main C att 563

Figure 4: Screenshot of the Graphic User Interface. Input Mismatch ( Yes / No) Options Parasitics (Yes / No) Output, V REF,N Parasitics Topology N bit Tech Parameters k, c cspec N runs Switching algorithm Y N Parasitics module None None Basic Array Structure N Y Models Complete Array Structure C D -2 N H (code) A/D Characteristic A/D transition levels DAC out DNL/INL Oversampled Sinusoid ADC ideal DAC FFT (SNDR, ENOB) Figure 5: CSAtool block diagram. C tot,main being the total capacitance of the ideal main-dac, while C par,main is the parasitic capacitance connected to the top-plate node of the main array. Thus, the DAC output in the BWA topology is evaluated as DAC out,bw A = FSR (H main AR H sub ), (7) where H main and H sub are coefficients related to the mainand sub-dac, H main = C tot,main C par,main C C main D main (8) att H sub = C tot,sub C par,sub C C sub D sub (9) att where C main, Csub, Dmain and D sub are the capacitance and digital output code vectors related to the main- and the sub-dac, C main = [ ] C N 2... C N (20) C sub = [ ] C... CN (2) 2 D main = [ ] D N 2... D N (22) D sub = [ ] D... DN 2. (23) IV. SIMULATION RESULTS The CSAtool implements in MATLAB the three abovementioned converter topologies by considering each array capacitor as a composition of unit elements,, each with its own variability that depends on technologic parameters, i.e. k c and c spec. This simple modeling approach allows to accurately take into account the effects of mismatch and stray capacitances, which affect the converter linearity. The tool allows to run both nominal and statistical simulations in order to accurately evaluate the DNL and INL taking into account at the same time capacitance mismatch and parasitic 564

effects. The tools also allows to estimate the degradation of both SNDR and ENoB due the converter nonlinearity. These two parameters are evaluated by feeding the real ADC with an oversampled sinewave of variable amplitude and reconverting the digital output signal to an analog waveform by means of an ideal DAC. Hence, the signal-to-noise ratio and the effective number of bits are evaluated by performing a FFT on the DAC output. Both SNDR and ENoB can be estimated while considering both deterministic parasitic effects and the contribute of statistical capacitance mismatch on multiple runs. Thus, CSAtool allows to obtain results accurate enough to be compared with post-layout and Monte Carlo simulations in Cadence Virtuoso environment but with a large improvement in terms of simulation time. In this section, the simulation results for the three converter topologies are shown and compared to both analytic expressions and Cadence results in terms of accuracy and simulation time. The presented results are related to converters featuring a 20- ff unit capacitor with a specific capacitance of ff/μm 2 and a Pelgrom coefficient of % μm. A. Static metrics The estimate of parasitic contribution to static nonlinearity has been evaluated by means of the CSAtool and compared with Cadence Virtuoso simulation results. A single-ended SAR ADC has been designed in Cadence Virtuoso adopting a VerilogA description for the logic circuit and the comparator, while the feedback DAC has been implemented with ideal capacitors. Arbitrary parasitic capacitances have been added between the main capacitor top- and bottom-plate nodes in order to estimate their effect on the converter nonlinearity. Hence, the input-output characteristic has been evaluated by means of a transient simulation applying a full-scale ramp as input signal. To reduce the simulation time, only the converter input and output values have been saved. The strobe and the sampling periods have been chosen short enough to guarantee at least 00 points per each conversion level, thus keeping the systematic error on the DNL below %. Fig. 6 shows the comparison between the DNL and INL characteristics obtained by CSAtool and Cadence Spectre simulations for the three converter topologies. The error between the CSAtool and Cadence results is never larger than 0.05 LSB, confirming the good accuracy of the implemented converter models. Fig. 7 shows the results obtained by the CSAtool once the capacitance mismatch has been considered in terms of standard deviation of DNL and INL. Since a Monte Carlo simulation performed in the Cadence environment requires at least 00 runs to achieve confident results, thus being impractical, the effect of capacitance mismatch has been compared to the analytic expressions by using (5)- (8). Table I compares the maximum values of DNL/INL standard deviation, i.e. σ DNL and σ INL, computed by the CSAtool running 00 simulations and the estimates obtained by the analytic expressions. The error between estimates and CSAtool results is always lower than 0.05 LSB. Figure 6: Comparison between DNL and INL estimated by Cadence simulations (black lines) and by CSAtool (red lines) for a given pattern of parasitic capacitances and for each converter topology. Figure 7: Standard deviation of DNL and INL as a function of the output code for a CBW, SBW and BWA 0-bit converter. B. Dynamic metrics The dynamic metrics have been computed in the CSAtool for the three single-ended converter topologies (with added parasitic capacitances) and compared to Cadence simulation results. The Cadence test-bench is similar to the one described in the previous section. The input signal is a sinewave at -khz frequency but featuring a variable amplitude, while the sampling rate has been set to 30 khz. Fig. 8 shows the SNDR evaluated by means of Cadence Spectre simulations and CSAtool as function of the input signal amplitude (referred to the full scale range) for the TABLE I: ESTIMATES OF σ DNL,max AND σ INL,max σ DNL,max σ INL,max Topology CSAtool Equation CSAtool Equation CBW 0.552 0.506 0.274 0.253 SBW 0.35 0.358 0.252 0.253 BWA 0.286 0.286 0.43 0.44 565

TABLE II: SINGLE SIMULATION TIME Static metrics Dynamic metrics Number of Bits CSAtool Cadence CSAtool Cadence 6 0.064s 625s.74s 625s 8 0.087s 2.5 0 3.99s 2.5 0 3 0 0.272s 0 4 s 2.66s 0 4 s 2.005s 4 0 4 s 2.549s 4 0 4 s 4 3.997s.6 0 5 s 3.322s.6 0 5 s TABLE III: MONTECARLO SIMULATION TIMES FOR 00 RUNS Resolution Static metrics Dynamic metrics 6 2.3s 60s 8 6.49s 72s 0 25.25s 83s 2 00s 245s 4 425s 573s Figure 8: SNDR as function of the input signal amplitude for the three converter topologies. three converter topologies. The maximum discrepancy between the Cadence and CSAtool results is always lower than 0.45 db. However, it s worth pointing out that the CSAtool allows to easily compute the SNDR vs. input amplitude curve, while the same simulations in Cadence takes a long time allowing to compute only few points of the dynamic characteristic. This can results in a not correct evaluation of the SNDR peak and thus of the ENoB. C. Simulation time Table II reports a comparison between the simulation times needed to compute the static and dynamic metrics with the CSAtool and Cadence environment. The simulation times refer to a CBW converter with a number of bits from 6 to 4 and to a single simulation run. All the simulations have been performed with a 3-GHz Pentium Xeon featuring a 4-Gbyte main memory. For the same accuracy (i.e. DNL lower than %), the CSAtool features an improvement in terms of simulation time up to about 0 4. Finally, it s worth pointing out that the CSAtool allows to estimate the static nonlinearities and the dynamics metrics in presence of statistical mismatch and parasitic capacitance effect allowing to perform a Monte Carlo simulation over a large number of runs. Table III shows the simulation time for a Monte Carlo analysis of 00 runs. For a 4-bit converter, i.e. the worst case, the tool allows to compute the static and dynamic metrics in less than 0 minutes, while the same analysis cannot be performed in a reasonable amount of time in Cadence Virtuoso environment. V. CONCLUSIONS This work shows the first MATLAB-based simulation tool for the analysis and design of charge redistribution SAR capacitive array to be used in SAR converters. A graphic user interface environment supports the implemented models that allow to simulate both technology mismatch and parasitic effects on converter linearity. The proposed tool overwhelms the conventional circuit-level simulation method based on transient analyses in terms of computation time for a given accuracy and does not require a fine calibration of simulation parameters (points per conversion step, strobe period, etc.). In particular, the method is helpful every time a fast analysis and an accurate sizing of commonly-used converter architectures is needed. The proposed CSAtool can be downloaded with encrypted scripts from ftp://ftp.elet.polimi.it/outgoing Stefano.Brenna. REFERENCES [] M. van Elzakker et al., 0-bit charge-redistribution ADC consuming.9μw at MS/s, IEEE J. of Solid State Circuits, vol. 45, no. 5, pp. 007 05, May 200. [2] P. Harpe et al., A 2.2/2.7fJ/conversion-step 0/2b 40kS/s SAR ADC with data-driven noise reduction, Dig. Tech. Papers Int. Solid State Circuits Conf., pp. 270 27, Feb. 203. [3] M. Saberi et al., Analysis of power consumption and linearity in capacitive digital-to-analog converters used in successive approximation ADCs, IEEE Trans. Circuits Syst. I: Reg. Paper, vol. 58, no. 7, pp. 736 747, Aug. 20. [4] P. Harpe et al., A26 μw 8 bit 0 MS/s asynchronous SAR ADC for low energy radios, IEEE J. of Solid State Circuits, vol. 46, no. 7, pp. 585 595, Jul. 202. [5] A. Chandrakasan and B. Ginsburg, 500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC, IEEE J. Solid State Circuits, vol. 42, no. 4, pp. 739 747, Apr. 2007. [6] A. Agnes, E. Bonizzoni, and F. Maloberti, A 9.4-ENOB V 3.8μW 00kS/s SAR ADC with time-domain comparator, Dig. Tech. Papers Int. Solid State Circuits Conf., vol. 37, no. 2, pp. 246 60, Feb. 2008. [7] C. Liu et al., A 0-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure, IEEE J. of Solid State Circuits, vol. 45, no. 4, pp. 73 740, Apr. 200. [8] S. Haenzsche, S. Henker, and R. Shcuffny, Modeling of capacitor mismatch and non-linearity effects in charge redistribution SAR ADCs, Proceedings of the Mixed Design of Integrated Circuits and Systems (MIXDES), pp. 300 305, June 200. 566