Tri-Gate Fully-Depleted CMOS Transistors: Fabrication, Design and Layout B.Doyle, J.Kavalieros, T. Linton, R.Rios B.Boyanov, S.Datta, M. Doczy, S.Hareland, B. Jin, R.Chau Logic Technology Development Intel Corporation 1
Outline of Presentation Introduction Different Depleted Substrate Transistor (DST) Architectures Experimental Results Computer Simulation Results Dimensional Analysis Importance of Corner Effects Tri-Gate Layout Analysis Summary 2
Source Transistor Architectures Gate Si L g Drain H Si ~ Lg/3 Single-Gate Planar Isolation Drain H Si Gate 3 Drain Gate 1 Source W Si L g Gate 2 W Si ~ 2Lg/3 Double-gate (e.g. FINFET) Non-Planar Gate 1 L g Source H Si Tri-gate Non-Planar W Si Gate 2 H Si ~ W Si ~ Lg 3
Tri-gate Transistor Side Gate D/S L g H Si W Si S/D Side Gate Top Gate Top Gate Side Gate Gate Side Gate Body controlled on three sides by adjacent gates -> Excellent electrostatic control of body 4
Experimental Tri-Gate Process Starting Si thickness = 50nm BOX thickness ~ 200nm Well implants N 2 O sacrificial oxidation Physical Tox = 1.5nm Poly thickness = 100nm Raised source-drain Nickel salicide Side Gate Side Gate Top Gate 5
60nm NMOS Tri-Gate Transistors Id (µa/µm) 1E-02 1E-03 1E-04 1E-05 1E-06 1E-07 1E-08 Vd=1.3V Vd=0.05V 0 0.4 0.8 1.2 Vg (Volts) Id (A/µm) 1.3E-03 Vg=1.3V 1.0E-03 Vg=1.1V 7.5E-04 Vg=0.9V 5.0E-04 2.5E-04 0.0E+00 0 0.4 0.8 1.2 Vd (Volts) Idsat = 1.23mA/µm and Ioff = 40nA/um at Vcc = 1.3V Subthreshold slope = 72mV/decade DIBL (Drain Induced Barrier Lowering) = 35mV/V 6
60nm pmos Tri-Gate Transistors Drain Current (A/µm) 1E-03 1E-04 1E-05 1E-06 1E-07 1E-08 1E-09 Vd=1.3V Vd=0.05V -1.2-0.8-0.4 0 Gate Voltage (V) Drain Current (A/µm) 6.E-04 5.E-04 4.E-04 3.E-04 2.E-04 1.E-04 0.E+00-1.2-0.8-0.4 0 Drain Voltage (V) Idsat = 520 µa/um and Ioff = 24nA/um at Vcc = 1.3V Subthreshold slope = 69.5mV/decade DIBL (Drain Induced Barrier Lowering) = 48mV/V 7
Double Gate-like Understanding Tri-Gate Behavior Device simulator - Full 3D single-carrier solution using DESSIS device simulator - Hansch quantum correction model applied - Intel 2.2 Ghz Xeon processor takes about 1 minute/bias point for an 18000 node mesh Simulated structures -L g =60 nm / H Si =60 nm / W Si =60 nm -L g =30 nm / H Si =30 nm / W Si =30 nm - Electrical Tox varies from 22 to 34 A - Corner radius varied from 0 (right-angle) to 16 nm - Adjusted doping adjusted to get I off ~100 na/µm 8
Simulation of L g =H Si =W Si =60nm Id (A) 1.E-03 1.E-04 1.E-05 1.E-06 1.E-07 1.E-08 1.E-09 Vd=1.3V Vd=0.05V DIBL=56 mv/v S/S (0.05V)= 72.5mV/dec S/S (1.3V)= 76mV/dec 0.0 0.3 0.6 0.9 1.2 Vg (V) Tri-Gate device shows full depletion effects 9
Simulation of L g =H Si =W Si =30nm 1.0E-03 1.0E-04 1.0E-05 Vd=1.0V Vd=0.05V Id (A) 1.0E-06 1.0E-07 1.0E-08 DIBL=62 mv/v S/S (0.05V)= 76mV/dec S/S (1.3V)= 76mV/dec 0.0 0.2 0.4 0.6 0.8 1.0 Vg (V) L g = W Si = W Si = 30nm device shows excellent electrostatics 10
Body Scaling Vs DST Architecture Minimum Body Dimension (H si, W Si (nm) 30 20 10 0 H Si =0.33*L g W Si =0.66*L g H Si =W Si =L g Lg =30nm Lg =20nm Lg =15nm Single- Double- Tri-Gate Gate Gate Tri-Gate body size more relaxed than single-gate or Double-Gate 11
Tri-Gate Device Understanding TCAD simulations partitioned into 3 distinct regions: Corners Top channel Sidewall channel Oxide 12
1.0E-02 Components of Current 1.0E-03 1.0E-04 Vd=1.0V Id (A/µm) 1.0E-05 1.0E-06 Vd=0.05V 1.0E-07 Corner 1.0E-08 Non-Corner Total 1.0E-09 0.0 0.2 0.4 0.6 0.8 1.0 Vg (V) Corner device shows much improved S/S & DIBL over noncorner devices because of proximity of adjacent gates 13
Components of Current % of Total Current 100.0% 80.0% 60.0% 40.0% Vd=1.0V Vd=0.05V 20.0% Corner 0.0% Non-Corner 0.0 0.2 0.4 0.6 0.8 1.0 Vg (V) Corner device dominates at low Vg s Non-Corner device (top & side) dominates at high Vg s 14
Physics of Corner Device R=8nm Vg=0.5V, Vd=1.0V Cut at midpoint along channel Proximity of the two gates at the corner give the nearly-ideal characteristics of the corner device, and the high current density 15
Physics of Tri-Gate Device hdensity Source Top Gate Drain hdensity 3E+04 T T Si Si = = 30nm 30nm Lg =30nm Si 1E+18 1E+16 1E+14 1E+12 1E+10 1E+08 1E+06 10000 100 1 (well conc. = 8E+18) All 3 gates control the depletion regions in the Tri-Gate device to make the Si body fully depleted 16
Importance of Corner Profile 1.E-02 Corner Current (A/µm) 1.E-04 1.E-06 1.E-08 1.E-10 1.E-12 R=0 nm R=5 nm R=10 nm R=15 nm R=20 nm R= infinity 0 0.2 0.4 0.6 0.8 1 Vg (V) Gate Radius R Body Body R is the radius of curvature of the corner Corner profile affects the sub-threshold characterisics of the corner device 17
Layout Implications: Fabricating Different Widths Fins Poly To meet different required widths for transistors, multi-tri- Gate fins are required. What are the layout width implications? 18
Layout Considerations Fins Z eff = Z Z eff = 0.6Z Planar Transistor Tri-Gate Transistor For a given pitch, total current per unit layout-width of the Tri-gate transistor has only 0.60X the channel width of the standard transistor Need to use spacer-litho technique to double the # of fins for a given pitch to increase total current (R.Chau et al., SSDM, Nagoya, Japan, Sept.,2002) (C-M Hu et al., IEEE Trans El Dev.,Vol. 49, pp. 436-441, 2002) 19
Spacer-Defined Fins Fins Z eff = 0.6Z Oxide Blocks with nitride spacers Fins Z eff = 1.2 Z Litho-defined Fins Oxide blocks to define spacer-masks for forming Si fins For the same pitch, # of spacer-defined fins doubles that of lithodefined fins Use of spacer-litho technique enables the Tri-gate transistor to have 20% more total current per unit layout-width than the standard planar transistor 20
Conclusions Tri-Gate transistors have been fabricated and achieve excellent drive current with near-ideal DIBL, S/S. Tri-Gate corners are responsible for the excellent subthreshold slope, DIBL characteristics, as well as relaxing the body dimensions compared to doublegate devices. In addition to the corners, the top-gate and sidewall channel regions are important in achieving optimal device performance. Layout analysis shows Tri-Gate achieves 20% higher total current per unit layout area than standard planar devices. 21