Wet Clean Challenges for Various Applications Business of Cleans Conference 2018 Stephen Olson, Martin Rodgers, Satyavolu Papa Rao, Chris Borst solson@sunypoly.edu
Outline SUNY Poly Introduction Background Key focus areas and wet process challenges SiC power devices Si Photonics Qubit fabrication EUV post-etch clean timesunion.com, July 10, 2015
SUNY Polytechnic Institute - Diverse Departments and Faculty ~3000 graduate and undergrad students SUNY Poly prepares today s students at two NYS locations; providing a comprehensive academic and research experience Business Management Communications and Humanities Computer and Information Sciences Engineering, Science & Mathematics Engineering Technology Social and Behavioral Sciences Nanobioscience Nanoeconomics Nanoengineering Nanoscience Utica Campus Albany Campus Utica Campus Albany Campus
SUNY Poly is not a traditional university: Public and private investments in excess of $15B with >$150 M in annual sponsored R&D Over 3,500 jobs on site (2,700 from industrial partners) > 1,670,000 sq.ft. of cutting-edge facilities, 120,000 sq.ft. of industry compliant 300mm cleanrooms More than 300 industry partners including electronics, energy, defense & biohealth
Combined Industry and Academic Mission Interdisciplinary academic research Industry R&D partnerships statewide Track record of CNSE graduates hired by research labs in industry & academia
SUNY Poly Timeline 1997 - present National Focus Center Consortium ($10M/year) 07/02 06/97 04/01 NanoFab 200 Building ($16.5M) 08/98 International SEMATECH North ($320M/5 years) Nanoelectronics Center of Excellence ($150M) College of Nanoscale Science & Engineering Formed 04/04 01/05 11/02 01/05 Tokyo Electron Ltd. (TEL) Technology Center America IBM-Albany CSR ($450M) ASML R&D Center ($400M/5 years) GF Luther Forest Plant ($4.6B) 07/05 INVENT ($600M/7 years) $1.5B Packaging R&D & MFG 06/06 07/08 05/07 International Sematech / NYS Agreement ($300M/5 years) M+W Group relocates its North American Headquarters 02/10 09/10 Smart System Technology & Commercialization Center created International SEMATECH Manufacturing Initiative 10/10 04/11 U.S. DOE PVMC Grant ($57.5M) NYS Power Electronics Manufacturing Consortium ($500M/5years) 07/14 07/15 American Institute for Manufacturing Integrated Photonics ($600M/5 years) Danfoss Silicon Power Utica Quad-C ($100M) 03/17
Power Electronics 150/200mm NY-PEMC Cleanroom at SUNY Poly Danfoss power electronic drives and cooling products Packaging Center at the Computer Chip Commercialization Center (Quad-C) in Utica, NY The New York Power Electronics Manufacturing Consortium (NY-PEMC) is building the next generation of power electronic devices Newly outfitted fab at SUNY Poly for building devices on 150 mm SiC wafers The NY-PEMC Packaging Center in Utica is a partnership with Danfoss Silicon Power for the packaging of modules and power blocks for industrial, automotive, and renewable applications
SiC Advantages Radar plot compares properties of SiC and Si Graph shows application areas for Si, SiC & GaN based devices Si power devices are approaching physical performance limits for high power devices Compared to Si, SiC devices have: 3x larger band gap 2x higher melting point 10x higher dielectric breakdown field
Wet Process Challenges for SiC Diagram shows crystal structure of 4-H SiC 1 Graph shows oxidation rates on different faces of 4-H SiC, Rate is slower on Si-rich surface 2 Thermal oxidation of SiC forms oxides with different thickness on the front and back side of the wafer Wet etch processes need to be designed for Si vs C face differences 1 Liu, Gang. (2015). Applied Physics Reviews. 2. 021307. 10.1063/1.4922748. 2 Simonka et al J. Appl. Phys. 120, 135705 (2016)
Defect Metrology Challenges Images show crystal defects on a SiC wafer 1 Substrate defects overwhelm metrology Hence more challenging to monitor and control wet processes on SiC 1 http://www.ledtaiwan.org/zh/sites/ledtaiwan.org/files/data16/docs/2.%20kla-tencor.pdf
Integrated Photonics Design Fabricate SEM images show Si photonics devices fabricated in SUNY Poly s 300mm semiconductor cleanroom Assemble Test AIM Photonics program is building Si photonic devices using established semiconductor technology and methods on 300 mm wafers EPDA: Enabling faster design with leading tools MPW runs: Cost-effective use of resources Key optical elements: light source, wave guide, modulator, detector Assembly & Test: Being developed at Rochester facility SEM image of modulator
Photonics Wet Challenges Oxide Si Cross section diagram of a Si waveguide Calculated loss as a function of roughness amplitude and correlation length for 500 nm wide waveguide 1 Loss measured as a function of waveguide dimension and smoothing process 2 Waveguide loss is driven by roughness of the sidewall Chemical oxidation followed by dhf has been shown to smooth the sides of Si wave guides 1 Lee et al. Appl. Phys. Lett., Vol. 77, No. 11, 11 September 2000 2 Sparacin et al. Journal of Lightwave Technology, Vol 23, No. 8, August 2005
University Research Nanoengineering Constellation - Current Research Next generation ICs, sensors, fuel cell, and photovoltaic technologies Reconfigurable multifunctional 2D devices Single-cell in-vivo carbon nanotube (CNT) multimodality sensors AlGaN next generation micro-batteries CIGS device optimization for PV alternative energy New 2D channel IC devices CNT in-vivo biosensors 3D MOCVD structures for micro-batteries n-doped graphene CIGS
Quantum Computing SUNY Poly researchers are exploring superconducting qubit architectures and materials to enable scaling of Quantum Computing systems Quantum computers have an advantage when solving certain problems that are difficult on a classical computer Factoring large numbers Efficient search through unstructured data Secure communication Pharma-molecule design, etc. Josephson junction formation using advanced processes at SUNY Poly Two 3D qubits from a 300mm wafer, measured at Syracuse University
Qubit Devices A qubit is a physical system that can be placed into a quantum state State is fragile, and eventually decays due to interaction with the environment Must last long enough to complete computation step Superconducting materials allow us to engineer systems that display quantum behavior Examples Systems from nature Photons, trapped ions, nuclear spin Engineered systems Superconducting Josephson junction Coherence time Long (s) Short (µs) Interfacing and coupling Difficult Easier as it can be part of the design New devices falling somewhere between these categories are being developed including topological qubit (Microsoft) and Si spin qubits (Intel) Key challenge: Insulators and interfaces are still have loss at superconducting temperatures
Strong sputter clean Gentle sputter clean Materials and Interfaces are Critical Improve dielectric growth 1 Interface Preparation 2 Remove dielectric 3 lower N-H defects, better loss tangent Qubit coherence time can be improved by eliminating defects in insulators and interfaces Interfaces are improved with surface cleaning and preparation 1 H. Paik and K.D. Osborn APL 96, 072505 (2010) 2 Quintana et al., APL 105, 062601 (2014) 3 Y. Chu et al. APL 109, 112601 dx.doi.org/10.1063/1.4962327 16
Interface Improvement TEM images show an Al / Al oxide / Al Josephson junction formed in an e-beam evaporation system Green region under Al/AlO/Al device shows oxide TEM image of Al deposited on Si in SUNY Poly s 300m line Surface was prepared using DHF Si surface prepared with DHF shows reduced oxide under the deposited Al
Si Undercut Etch TiN Q improvement of NbTiN resonators with Si recess 1 Si TiN overhang improves Q factor of resonators Wet process was used to create the overhang SEM image shows undercut TiN structure fabricated at SUNY Poly 1 Barends et al, arxiv:1005.0408v1 3 May 2010)
EUV Lithography ASML 3400B NXE EUV System SEM image shows single-pass 16nm EUV pattern SUNY Poly and partners are working together to enable EUV lithography success at the 7 and 5 nm nodes
EUV resist Hardmask Oxide Wet Clean for EUV Patterned Features After HM open and EUV resist ash After wet clean After oxide RIE After wet clean Process flow 1. Pattern EUV resist 2. Etch hardmask 3. Wet clean 1 4. Etch oxide 5. Wet clean 2 EUV resist must be very thin to support fine feature size Requires an etch to open hardmask and etch features Wet clean is used to remove re-deposited polymer after HM open RIE and ash. Similar structure a different wet clean shows pattern collapse
Conclusion Wet clean remains an important process technology as semiconductor fabrication technology are applied to new areas