Appendix B Review of Digital Logic Baback Izadi Division of Engineering Programs bai@engr.newpaltz.edu
Elect. & Comp. Eng. 2
DeMorgan Symbols NAND (A.B) = A +B NOR (A+B) = A.B AND A.B = A.B = (A +B ) OR A+B = A+B =(A.B ) NOT A = A Buffer A = (A ) Elect. & Comp. Eng. 3
Gates, truth tables, and logic equations Asserted signal: A signal that is (logically) true, or 1. Deasserted signal: A signal that is (logically) false, or 0. Combinational logic: A logic system whose blocks do not contain memory and hence compute the same output given the same input. Sequential logic: A group of logic elements that contain memory and hence whose value depends on the input as well as the current contents of the memory. Problem: Consider a logic function with three inputs: A, B, and C. Output D is true if at least one input is true Output F is true only if all three inputs are true Output E is true if exactly two inputs are true Elect. & Comp. Eng. 4
D=A+B+C F=A B C E=(A B C)+(A B.C)+(A.B C) Elect. & Comp. Eng. 5
Find: a. Sum of Min-terms b. Product of Max-terms c. Standard Sum of Products d. Standard Product of Sums e. Minimum Sum of Products f. Minimum Product of Sums g. Implement the circuit using AND OR logic h. Implement the circuit using all NAND logic i. Implement the circuit using OR AND logic j. Implement the circuit using all NOR logic Elect. & Comp. Eng. 6
Simplification of Boolean Functions Elect. & Comp. Eng. 7
Popular Combinational Devices Full Adder Seven Segment Decoder Standard Decoders: Used to enable one device out of many Encoders: Used to identify the device that is requesting service Multiplexers: An electronic switch which connects an input to one of many outputs Demultiplexers: An electronic switch which connects an output to one of many inputs Elect. & Comp. Eng. 8
Encoder Elect. & Comp. Eng. EGC4 32 SUNY New
Decoder Decoder: A logic block that has an n-bit input and 2 n outputs, where only one output is asserted for each input combination. 1 out of 8 decoder has 3 inputs, called 12, 11, and 10, and 2 3 = 8 outputs, called Out0 to Out7. Only the output corresponding to the binary value of the input is true, as shown in the truth table. The label 3 on the input to the decoder says that the input signal is 3 bits wide. Elect. & Comp. Eng. 10
The Multiplexor A multiplexor might more properly be called a selector, since its output is one of the inputs that is selected by a control. 1-out-2 MUX A B S 0 1 O S O 0 A 1 B C = S A + S B How about 1-out-4? Elect. & Comp. Eng. 11
Abstraction What if we are choosing between two 32-bits inputs Select A 32 B 32 Select M u x 32 C A31 B31 A30 B30 M u x M u x. C31 C30. A0 B0 M u x C0 Elect. & Comp. Eng. 12
1 to 4 Demultiplexer Elect. & Comp. Eng. 13
S1 S0 Y3 Y2 Y1 Y0 0 0 0 0 0 Din 0 1 0 0 Din 0 1 0 0 Din 0 0 1 1 Din 0 0 0 Elect. & Comp. Eng. 14
Programmable logic array Elect. & Comp. Eng. 15
Verilog Hardware description language Behavioral specification: Describes how a digital system operates functionally. Structural specification: Describes how a digital system is organized in terms of a hierarchical connection of elements. Elect. & Comp. Eng. 16
Clocking methodology Clocking methodology: The approach used to determine when data is valid and stable relative to the clock. Elect. & Comp. Eng. 17
Setup and Hold Time Setup time: The minimum time that the input to a memory device must be valid before the clock edge. Hold time: The minimum time during which the input must be valid after the clock edge. Propagation time: The time required for an input to a flip-flop to propagate to the outputs of the flip-flop. Elect. & Comp. Eng. 18
Clock skew Clock skew: The difference in absolute time between the times when two state elements see a clock edge. Elect. & Comp. Eng. 19
Design of a Register File Ability to read from two registers and write to one register Read operation using D flip-flops and MUX s Readregister number 1 Register 0 Read register number 1 Read register number 2 Write register Write data Register file Write Read data 1 Read data 2 Readregister number 2 Register 1... Register n 2 Register n 1 M u x Readdata 1 M u x Readdata 2 Elect. & Comp. Eng. 20
Register File Read and Write Read register number 1 Read register number 2 Read register number 1 Read register number 2 Write register Write data Register 0 Register 1 Register n 1 Register n Register file Write Read data 1 Read data 2 M u x Read data 1 Write Write Register 0 1 n-to-1 decoder n 1 n C Register 0 D C Register 1 D C Register n 1 D M u x Read data 2 Write Data C Register n D Elect. & Comp. Eng. 21
Design of Sequential Circuits Design Procedure: 1. Word description. 2. State diagram. 3. Assign binary values. 4. Decide on type of flip flops. 5. Excitation table for the flip flop. 6. State table. 7. Generate simplified logic equations for flip flop inputs and system outputs. 8. Draw logic diagram. Elect. & Comp. Eng. 22
Moore Vs Mealy FSMs: different output generation Moore FSM: next state inputs x 0...x n Comb. Logic S + n CLK D Flip- Flops Q n Comb. Logic outputs y k =f k (S) present state S Mealy FSM: inputs x 0...x n Comb. Logic direct combinational path! S + n CLK D Flip- Flops Q n Comb. Logic outputs y k = f k (S, x 0...x n ) S Elect. & Comp. Eng. 23
Finite State Machines Example State diagrams are representations of Finite State Machines (FSM) Mealy FSM Output depends on input and state Output is not synchronized with clock can have temporarily unstable output Moore FSM Output depends only on state Mealy FSM Moore FSM Elect. & Comp. Eng. 24
Example #2: Using JK flip-flops, design a circuit for following state diagram Step 1: State Diagram Step 2: JK Flip-Flop Excitation Table PRESENT STATE NEXT STATE Q(t) Q(t+1) J K 0 0 0 X 0 1 1 X 1 0 X 1 1 1 X 0 Mealy or Moore? Elect. & Comp. Eng. 25
Step 3: State Table PRESENT STATE INPU T NEXT STATE FLIP-FLOP INPUTS OUTPU T Q A Q B X Q A Q B J A K A J B K B Z 00 0 00 0 X 0 X 0 00 1 01 0 X 1 X 0 01 0 10 1 X X 1 0 01 1 01 0 X X 0 0 10 0 10 X 0 0 X 1 10 1 11 X 0 1 X 1 11 0 11 X 0 X 0 0 11 1 00 X 1 X 1 0 Step 4: Karnaugh Map Q B X 00 01 Q 11 10 A 0 1 0 1 m 0 m 1 m 3 m 2 X X X X m 4 m 5 m 7 m 6 J A = Q B X' Q B X 00 01 Q 11 10 A X X m 0 m 1 m 3 m 2 m 4 m 5 m 7 m 6 X 1 1 X Q B X 00 01 Q 11 10 A Q B X 00 01 Q 11 10 A K A = Q B X 0 1 X X m 0 m 1 m 3 m 2 0 X X 1 m 0 m 1 m 3 m 2 Q B X 00 01 Q 11 10 A 1 1 m 4 m 5 m 7 m 6 X X 1 X X 1 0 m 4 m 5 m 7 m 6 m 0 m 1 m 3 m 2 J B = X K B = Q A X + Q' A X = Q A + X 1 1 1 m 4 m 5 m 7 m 6 Z= Q A Q' B Elect. & Comp. Eng. 26
Step 5: Circuit Elect. & Comp. Eng. 27
4-bit Binary Counter with Reset module count_4_r_v (CLK, RESET, EN, Q, CO); input CLK, RESET, EN; output [3:0] Q; output CO; reg [3:0] Q; assign CO = (count == 4'b1111 && EN == 1 b1)? 1 : 0; always@(posedge CLK or posedge RESET) begin if (RESET) Q <= 4'b0000; else if (EN) Q <= Q + 4'b0001; end endmodule Elect. & Comp. Eng. 28
4-bit Shift Register with Reset module srg_4_r_v (CLK, RESET, SI, Q,SO); input CLK, RESET, SI; output [3:0] Q; output SO; reg [3:0] Q; assign SO = Q[3]; always@(posedge CLK or posedge RESET) begin if (RESET) Q <= 4'b0000; else Q <= {Q[2:0], SI}; end endmodule Elect. & Comp. Eng. 29