Selective Processes: Challenges and Opportunities in Semiconductor Scaling June 4, 2018 Kandabara Tapily TEL Technology Center, America, LLC IITC 2018 Selective Deposition Workshop K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 1
Contents Technology trends: challenges and approach in patterning Selective Deposition opportunities and challenges Summary K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 2
Technology trends
Technology trend 3D Architecture Nano-wire Planar FET FinFET High AR of DRAM 3D NAND large stack 1000 [nm] 100 10 i-line KrF Resolution Wavelength ArF 180 130 110 90 Scaling 1 1990 1993 1996 1999 2002 2005 2008 2011 2014 2017 Vertical utilization is the key approach towards sub-10nm generation 65 45 32 22 immersion 14 EUV 10 7 5 2020 K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 4
Metal Pitch Nano Wire Nano Sheet CFET/VFET Logic trend and challenges FEOL MOL Advanced patterning technology Continuous evolution of transistor structure Advanced patterning technology Continuous scaling Limit of 193i single exposure N16/14 N20 N28 Poly Gate Pitch Limit of 193i single exposure BEOL Alignment Resistivity N3 N5 N7 N10 Advanced patterning technology Capacitance Advanced patterning technology is the key to continuous scaling and transistor structure evolution K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 5
Design trend and challenges 2D layout Grid challenge 1D layout Single Exposure Line cut challenge roughness Pitch walk SADP SAQP alignment complexity Grid + Cut/block 1D layout SADP : Self-Aligned Double Patterning SAQP : Self-Aligned Quadruple Exposure Layout decomposition to 1D is a break through to scaling, but also creates new challenges (source : TEL) K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 6
Patterning challenges and approach
Patterning challenges Grid formation Line cutting Final Pattern SADP SAQP LE LELE LELELE (EPE : Edge Placement Error) Mandrel, spacer, cuts Traditional sources of CD variation Roughness Previous Pattern Cuts to the grid Cuts to each other EPE is the fundamental challenge for advanced patterning technology K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 8
EPE (nm) EPE requirement (10nm hp) 20nm cut mask 10nm 10nm ±5.0nm Cut mask case 10 9 8 7 6 5 4 3 2 1 0 8.3 20 BEOL case 7.0 Device requirement Process-induced 6.1 15 10 half pitch (nm) 5.3 4.7 5 EPE = +(PitchErorr grating ) 2 +(CDU hole ) 2 + (Overlay) 2 2.0nm 2.0nm 4.0nm Metal Metal Via Continuous EPE improvement is needed along with scaling K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 9
Typical EPE factors CD variation a-c S io 2 a-c SiO 2 SiN (N. Kuboi et al, J Vac. Sci. Technol. A 31 (6), Nov/Dec 2013) Roughness (LER / LWR / CER) Pattern profile (leaning) Etch clogging Loading effect Overlay Mx+1 Mx Litho-Etch Litho-Etch OVL Litho-Etch OVL Alignment of cut/block to gird Alignment of via to metal lines Alignment of holes at multiple LE Numerous factors impact EPE and should be addressed K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 10
Patterning paradigm towards placement accuracy Bottom-up lithography Shorter wavelength Immersion EUV i-line KrF ArF Top-down lithography + Multiple patterning LEx SAMP Shrink + Self-alignment ALD / ALE Multi color Self-alignment + self-assembly Selective deposition DSA The paradigm is expanding to self-alignment and bottom up approach K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 11
Patterning challenges and approaches Grid formation Typical scheme SADP SAQP Challenge Potential approach LER, LWR, local CDU Etch smoothing (DCS) Spacer reshape Spacer leaning Dep / cure and trim Cost PR mandrel Cut / Block LEx CD, CDU, CER Healing, shrink Via formation New process development Alignment with grid (within layer) SAB Cost and complexity mitigation EUV LEx CD, CDU, CER Healing, shrink Alignment with metal lines (inter layers) FSAV Cost and complexity mitigation EUV Atomic level process ALD / ALE Bottom up lithography Selective deposition K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 12
Process technology examples
Self-alignment through etch selectivity Intended design Conventional approach using L/S grid Self-aligned approach with 3 grid colors C B A B C B A B B A B C Etch selects mandrel A Core B Spacer C Fill material Etch selects fill material Self-alignment of cut/block is enabled by SAB, using etch selectivity K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 14
Placement margin improvement by SAB half pitch Conventional 12 12 half pitch SAB 36 36 (pitch assumption: 24nm) etch etch Lithography OL is restricted to be within 6nm (regardless of 193i or EUV) Lithography OL limit will be covered within the margin Placement margin of hard mask is 3 times relaxed K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 15
Flexibility of material selection for SAB Potential material combinations SAB demonstration (case 2) Case # Mandrel (A) Spacer (B) Fill (C) 1 a-si MeOx SOG 2 SiN Oxide SOC 3 a-si Oxide SOM A = Mandrel B = Spacer C = Fill material Combination of non-metal materials Various material combinations can be implemented Combination of non-metal materials is demonstrated K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 16
Atomic level process approach 22
Evolution of the Self-aligned Technology: New integration and material Innovation Self-Aligned Self-Limited Atomic Layer Deposition Säynätjoki 8 May 2012, SPIE Newsroom. DOI 10.1117/2.1201204.004218 Atomic Layer Etching Self-Directed Younkin SPIE 2015 Kim JES EDL 158, 12, 2011, D710-4 doi: 10.1149/2.061112jes K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 18
Dep. amount [nm] Atomic Layer Deposition (ALD) technology Initial Si 1adsorption st reactant Purge Oxidation O 2 plasma Purge cyclic Si Precursor O* radical 12 10 8 6 4 2 0 Self-limited reaction (0.2nm / cycle) ALD 50cycle Adsorption step time [sec.] saturated Film coverage comparison Conventional (CVD) ALD (ALD : Atomic Layer Deposition) ( Top / Side / Btm) 18/8/13nm 18/12/16nm 18/17/18nm 18/18/18nm uniform coverage Conformal deposition is enabled by self-limited reaction at atomic level K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 19
ALE Technology (AlOx example) 1 Etchant Adsorption 2 Etchant Purge 4 Etching Products Purge 1 cycle 3 Etching Products Desorption Ar neutral beam irradiation Min Microelectronic Eng. 110 (2013) 457 460 Anisotropic ALE by self-limiting half cycles K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 20
Thermal ALE Reverse ALD through ligand exchange K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 21
Multiple options of atomic layer approach Approach Atomic layer (A) Several layers (B) Ion Modification (C) Schematic diagram Time control B Adsorption Activation Self-limiting Self-limiting Time control Quasi self-limiting Loading Free Controlled by step parameter Semi self-limiting Semi self-limiting Semi Free Polymer No use Thin polymer No use Etched film Si, Ge SiO 2, SiN SiN Throughput Slow OK Middle Selectivity Infinite High Ultrahigh T Self-limiting time C Semi self-limiting A Optimal approach can be selected by the requirement of material combination, selectivity and throughput K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 22
Quasi-ALE technology SiO2 etch Initial Adsorption Activation Desorption (radical transportation) Ar (ion bombardment) + + + FC film xn SiO 2 (ALE : Atomic Layer Etch) Several layers of adsorption Example : Self-Aligned Contact Conventional Quasi-ALE Mask SiO 2 SiN 1. High SiN selectivity 2. Narrow slit etch M. Honda, et al,, J. Phys. D: Appl. Phys. 50 (2017) 234002 High selective etch is enabled by independent control of radical and ion flux. K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 23
Novel SiN etch technology Ion Modification step Chemical Removal step + + + Modified layer cyclic SiN Modified layer formation by ion activation Example : SiN spacer etch SiN Modified layer removal by radical reaction Initial Conventional Novel process SiN SiO 2 Si Si loss : 7.8nm SiO2 loss : 13.6nm Bad footing Si loss : 0.0nm SiO2 loss : 1.6nm Excellent footing High selective etch is enabled by semi self-limiting reaction of SiN K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 24
Selective Deposition Toolbox/Opportunities Wallace, AVS, 2015 K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 25
thickness Area Selective Deposition (ASD) Objectives Device fabrication requires due to scaling to make simple process scheme Growth on A Selectivity regime Growth on B Requirements Cycle/time 1. Difference in surface chemistries between growth and non growth areas 2. Deposition on either Dielectric or Metal on Dielectric or Metal 3. No deposition on undesired surfaces 4. Orthogonal film growth Litho. / Etch / Depo Selective deposition Advantages Current Scheme No litho. / Etch process needed No scaling limit Dielectric Metal or Si Depo. Concerns Multiple processes Impact CPW New technology required K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 26
Approaches to Area Selective Deposition (ASD) ASD by Inherent Selectivity Metal on metal Epitaxy of Si ASD by Ligand/precursor design Precursor inhibition or reactant inhibition ASD by Surface deactivation or activation Passivation by Self-assembled monolayer (SAM) ASD by Combination of deposition and etch Topographically selective Selectivity enhancement by correction step ASD by Inhibition during ALD (ABC or ABCD) process K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 27
Selective deposition by inherent material selectivity (Example Metal on metal) growth CD: 46.4nm 6.2nm SiO2 W Ru 106.9nm 200nm 50nm X-TEM Ru W EDX mapping growth 41.7nm SiO2 Ru 37.7nm Ru W K. Tapily, AVS Focus Topic Selective Deposition, San Jose 2015 Deposition of Ru is demonstrated to grow on W only K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 28
unfavorable Selective Deposition by Ligand Design 3eV Material A Material B 2eV 1eV -1eV -2eV favorable Tailor precursor chemistry for favorable reactions on desired surfaces Need to be explored -3eV K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 29
Selective Deposition by Via Selective Precursor adsorption J. Singh et al., Chem. Mater., 30, 663 (2018) Selective ALD Fe 2 O 3 only growth on Pt when using O2 as co-reactant growth occurs only on the catalytic active surface K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 30
Selective Deposition by Area Deactivation or Activation R. Chen et al., Appl. Phys. Lett., 86, 191910 (2005) Mackus et al., J. Phys. Chem.C,117,10788 (2013) SAM is used to block HfO2 growth on undesired surface while grows on desired surface ALD Pt grows on Pt but not on Al2O3 surface at low pressure K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 31
Requirement for SAM Layer Lee and Bent, Wiley-VCH Verlag (2012) Densely packed long chain SAM Densely packed short chain SAM Tail group determines surface functionalization Head group determines substrate reaction Van der Waals ensures formation of ordered SAM SAM with bulky tail groups R. Chen, chem. Mater, 17(3), 536 (2005) SAM needs to be densely pack and reasonably long chain Loosely packed SAM with pinholes K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 32
Area selective deposition by combining Deposition and Etch: topographically selective HfO 2 K. Tapily, AVS Focus Topic Selective Deposition, San Jose 2015 Note: Very high selectivity to SiO 2 Al 2 O 3 ALD high K dielectrics followed by anisotropic ALE enables thin ALD sidewall spacers K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 33
Area selective deposition by combining ALD and etch: topographically selective Woo-hee Kim et al., ACS Nano, 10, 4451 (2016) Selective Pt thin film using topographically selective inhibition K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 34
Selective deposition via inhibition during deposition Dielectric on dielectric HDHD Si substrate treatment: HDHD: Adding H radical treatment during after every x cycles to inhibit growth - Delayed ALD Al 2 O 3 incubation - Super ALD cycles [X (AB cycles)+h treatment] Y 10:1 4-5nm selectivity Thickness Ox Si Ox Si K. Tapily, AVS Focus Topic Selective Deposition, San Jose 2015 SPA H plasma is effective in suppressing Al 2 O 3 growth up to ~5nm on Si and not on oxides K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 35
ASD using inhibition during ALD (ABC or ABCD) process Inhibitor selectively absorbed Inhibitor blocks growth Inhibitor is removed during co-reactant Mameli et al., ACS Nano, 11, 9303 (2017) Selectivity achieved via precursor deactivation using insitu inhibitor (Hacac) Different selectivity observed for different oxide surfaces K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 36
Challenges for Area Selective Deposition Surface preparation Incoming defects on non-growth surface Non growth area changes during deposition Surface functionalization/modification during the ALD deposition Finite selectivity Slow/Throughput Defectivity and defect removal Metrology and characterization Incoming surface is not clean so nucleation sites during ASD Green et al., J. Appl. Phys., 94, 3405 (2003) K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 37
Can defectivity in selective deposition be controlled? K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 38
Correction Step/Defect Removal F. Hashemi et al, ACS Nano, 9, 8710 (2015) F. Hashemi et al, Adv. Mater. Interfaces, 1600464 (2016) Improved Selectivity using correction steps K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 39
thickness Metrology and Characterization Blanket studies necessary to understand growth mechanism and loss of selectivity Structural properties of the deposited films Surface coverage and selectivity numbers Selectivity regime Growth on A XPS, FTIR, RBS, SIMS. Develop metrology for relevant structures with scaled dimension Growth on B Defectivity Cycle/time K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 40
Summary 32
Patterning paradigm towards placement accuracy Self-Alignment + Self-Assembly Top-Down Lithography Shorter Wavelength + Multiple Patterning LEx SAMP Shrink + Self-Alignment Atomic Level Approach Multi Color Approach Selective Deposition DSA Bottom-Up Lithography Immersion EUV i-line KrF ArF The paradigm is expanding to self-alignment and bottom up approach K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 42
Summary 3D architecture and scaling are key requirements for sub 7nm generation Scaling booster along with aggressive pitch scaling will enable the next generation scaling EPE is the fundamental challenge for advanced patterning Patterning paradigm is expanding to self-alignment and bottom up approach Selective deposition will be an enabling technology in reducing complexity in advanced patterning as well as the increasing cost associated with it. Defects removal and metrology are key challenges that need to be addressed K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 43
Acknowledgement R&D Team at TEL Technology Center, America, LLC (TTCA) T. Tsunomura at TEL Corporate Technology Marketing (CTM) R&D Team at TEL Technology Solutions (TTS) K. Nawa at TEL Process Integration Center (PIC) Thank you for your attention! K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 44
K. Tapily/ IITC 2018 Workshop/Selective Processes and Challenges 45