Page 1/5 Version: 7/30/17 1. Multiply out the following logic expressions to obtain the Sum of Products.. (/W /X Y) (W /Z) (/W X /Z) (W X) (W Y /Z). (/W /Y Z) (/W Y) (X /Y /Z) (/W X Y) (Y Z) 2. Using oolean identities, find the MSOP for your SOP obtained in #1. 3. Repeat #2 using K-Maps to obtain the MSOP and MPOS. heck your MSOP answers that you obtained in #2 with your K-Map derived MSOP results. 4. Use oolean identities to simplify the following logic equation. Then use a K-Map to check the MSOP result. lso use a K-Map to find the MPOS result. = /X*/Y*/Z /W*/Y*Z /[(/W /Z /X*Y)(X Z W*/Y)] 5. reate a logic expression as required in each of the following paragraphs.. You should laugh at a joke if it is funny, it is in good taste, and it is not offensive to others, or if it is told in class by your professor (regardless of whether it is funny and in good taste) and it is not offensive to others.. flow rate sensing device used on a liquid transport pipeline functions as follows: The device provides a 5 bit output where all five bits are zero if the flow rate is less than 10 gallons/minute. The least significant bit is 1 if the flow is greater than 10 gal/min. The LS and next most significant bit are 1 if the flow is greater than 20 gal/min. The LS and next two most significant bits are 1 if the flow is greater than 30 gal/min and so on. The five bits are represented by variables,,, D and E where is least significant and E is most significant. Write an equation for if we want to be 1 when the flow rate is less than 30 gal/min. Write an equation for G if we want G to be at least 20 gal/min but less than 50 gal/min.
Page 2/5 Version: 7/30/17 6. Given the following Logic Truth Table, find the MSOP and MPOS for Y and Z. Y Z 000 0 0 001 1 X 010 X X 011 1 0 100 0 X 101 1 X 110 X 1 111 1 1 7. reate a single bit cascade-able full adder and a single bit full subtractor. ascade several single bit adders to form a 4 bit adder and cascade several single bit subtractors to form a 4 bit subtractor. 8. bank vault has three locks with a different key for each lock. Each key is owned by a different person. In order to open the vault door, at least two people must insert their keys into the locks. The signal lines,, and are 1 if there is a key inserted into locks 1, 2 or 3, respectively. Write an equation for the variable U (unclock) which is 1 if the door should open. 9. Design a circuit which will add an 8 bit signed number to a 6 bit signed number. 10. Repeat the above design but assume that the 6 bit number is now unsigned. 11. combinatorial circuit has four inputs (MS),, and D (LS) which represent a D number. The circuit then has two groups of four outputs P (MS), Q, R, S and W, X, Y, and Z (LS) where each group represents a D digit. The goal is to design a circuit that will multiply the single D digit times five producing a two digit D output. i.e. D = 0111 then PQRS = 0011 and WXYZ = 0101. ssuming that no invalid D digits will occur as inputs, create a truth table and logic equations for the device. Hint: Use don t cares in the outputs to simplify the output equations when exceptable.
Page 3/5 Version: 7/30/17 12. or the following logic expressions, use a K-Map to find the MPOS and MSOP.. Y*Z /W*Y /W*X W*/X*/Z. (W /X) (/W /X Z) (/X Y /Z) (/Y Z). /W*X*Y*Z /X*Y /W*X*/Y*/Z /Y*/Z /W*X*Z /W*/X*/Y*/Z 13. Simplify the (2) circuits below and convert each circuit to a circuit that contains only NND gates. 14. Repeat #13 above but this time convert each circuit to a circuit that contains only NOR gates. 15. Given the following logic equations, create a circuit that contains only ND, OR and Inverter gates. ssume all signals are low true and do not simplify the equations.. = (W X Y /Z) (/W /X Y /Z) (/W Y) (W /Z) (X Y Z). = /W*/Y*/Z /X*Z /W*Y*Z W*X*/Z. = (W /X) (/W /X Y) /Z 16. Repeat #15, but now assume all inputs are high true and the output is low true. 17. or. and. in #15, implement the equation using NND gates. 18. or. and. in #15, implement the equation using NOR gates.
Page 4/5 Version: 7/30/17 or the two circuits below, answer the questions that follow. igure 1 igure 2 19. In ig. 1, assume,, and are all high true. What is the logic equation for? 20. In ig. 1, what is the logic equation for with.l,.h,.l and.l? 21. In ig. 2, assume all signals are low true, what is the logic equation for? 22. In ig. 2, what is the logic equation for with.l,.l and.l? 23. Design by direct implementation the circuit diagrams (by hand) for the following logic equations using only 2-input NND gates. Do not simplify the logic equation. Y = D*/(/(/*/*) */) ctive-high:,d ctive-low:,,y 24. Implement the logic equation in #23 using only 2-input NOR gates. 25. In igure 3, solve the logic equation for Z assuming,d, E are high true and,,,g and Z are low true. 26. In igure 4, solve the logic equation for Z assuming,,, D, E, and G are low true and Z is high true. 27. ind MSOP and MPOS for the following two K-Maps:.. D 0 1 1 1 0 1 1 0 1 1 1 0 1 0 1 1 D 1 0 1 X 1 1 X 0 X 0 1 X 1 0 0 1
Page 5/5 Version: 7/30/17 D E igure 3 Z G D Z E G igure 4 28. Given the following logic block, realize a circuit for the design out of NDs, ORs & Inverters. Y = ()(/) Y 29. Design a 2:4 decoder with high true inputs, a low true global enable and low true outputs. reate a logic truth table, find the logic equations and implement wih NDs, ORs and Inverters. Then use the 2:4 decoder (as many as you like) to create a 3:8 decoder with low true inputs and high true outputs.