TOPIS: Logic Logic Expressions Logic Gates Simplifying Logic Expressions Sequential Logic (Logic with a Memory) George oole (85-864), English mathematician, oolean logic used in digital computers since the late 93 s, for arithmetic functions, and storage asic Logic Functions onsider a simple switch: it has two positions: OFF =, ON = We can use the switch to allow current to flow to light a bulb onsider f to indicate if the bulb is on, by denoting the switch to be we can write: f = 2 Switches in series (ND) Truth Tables Two switches can be used in series: The bulb is on if switch ND switch are both on i.e. f =.. is used to denote ND in oolean algebra (also ) 3 truth table define the output values of a function in relation to LL possible input variables. Each line in the truth table represents a UNIUE value of the input variables. E.g. for the two switches in Series n 2 entries ( n is the number of input variables ) f =. Input Variables Output Variables f 4 Switches in Parallel (OR) lternative view for OR an also consider two switches in parallel: if (switch is NOT on) ND (switch is NOT on) then the bulb is NOT on i.e. f =. if either switch OR is on then the bulb is on: f = + + is used to denote OR in oolean lgebra (also ) f 5 where the bar ( ) indicates negation in oolean lgebra but f = + so f = + (negate both sides). = + (de Morgans rule) 6
Exclusive OR connection Only one switch when on enables the bulb to be on: f = is used to denote EX-OR in oolean lgebra EX-OR is often referred to as an Equivalence relation (i.e. the output is zero if both inputs are the same) f 7 Functions of two binary variables 6 ( = 2 4 ) functions can be performed between two binary variables: f f f 2 f 3 f 4 f 5 f 6 f 7 f 8 f 9 f f f 2 f 3 f 4 f 5 E.g. f = f =. f 2 =. f 3 = f 4 =. f 3 =. 8 Some Logic Relationships Relation Dual Relation. = + =. = + =. = + =. = + =.( + ) =. +. + (.) = +. =.( + ) =.( + ) = =.( + ) =. +. + (.) = +. =. = + Mathematical Laws also apply to oolean lgebra: ommutative Law (ordering may change): e.g.. =., + = + ssociative Law (brackets can be moved): e.g..(.) = (.). =.. + ( + ) = ( + ) + = + + Distributive Law (can multiply out brackets): e.g..( + ) =. +. ( + ).( + ) =. +. +. +. =.( + + ) +. 9 De-Morgans Rule: Electronic Logic Gates + =., + =. To change form of expression: ) hanges ND s to OR s and vice versa, 2) negate variables (or sub-expressions) 3) negate resulting expression Examples: Use concepts of oolean algebra, often using voltages of 5V and V to represent and. Standard symbols: NOT ND OR EX-OR. ( + D ) = (. ) + D =.(.D ) =.(.D ) ( + ) + D NND NOR EX-NOR (. ) + (. D ) = + + + D a indicates negation 2 2
ombinatorial Logic ircuits logic circuit whose outputs are logical functions of its inputs onsider the EX-OR function f = From the Truth Table we can write: f =. +. This can be represented by the logic circuit: f... +. 3 NOT ND OR EX-OR NND Gates an be used to implement any other function, e.g. f = =.. f =. =. f = + =. + f =. +. + =..... 4 Logic ircuit -> Truth Table an construct a Truth Table for a logic circuit, e.g. P f R P R f onsider intermediate signals P,, R, where P =., =., R =., and the output is f =. +. +. 5 Truth Table -> oolean equation We can obtain a sum of products equation directly from a Truth Table. f.......... So function f is TRUE when any of these combinations are TRUE f =.. +.. +.. +.. +.. 6 Minimising Logic Expressions Logic expressions can be simplified to reduce complexity (and also the number of gates used), in two main ways: ) use mathematical laws (commutative, ssociative, Distributive, de-morgans etc). 2) use truth table to construct a sum of products form and represent graphically (Karnaugh Map) In either case the truth table for the logic expression before and after minimisation must be the SME. ) Mathematical Laws e.g. f = + (. ) + (.D) = + (. ). (.D ) de-morgan = + ( + ). ( + D ) de-morgan = +. +. +.D +.D distributive = +.( + + D ) +.D = + +.D 7 8 3
2a) Sum of Products Use the truth table to obtain the sum of products. (So called, since an OR + is considered as a sum, and an ND. as a product) Simplifying Sum of products form can be simplified by looking for terms that differ by only one variable and its complement (X and X), e.g. f f =.. +.. +.. +.. +.. 9.. +.. =..( + ) but ( + ) = So..( + ) =. Simplify f : f =.. +.. +.. +.. +.. f =..( + ) +.. +..( + ) =. +.. +. =. +.(. + ) =. +.( + ) 2 2b) Karnaugh Maps Geometric (graphical) way to quickly derive minimal expressions for a logic function (of a few variables) three variable function can be represented by a 4x2 rectangle, djacent values Key idea of the Karnaugh Map is that horizontally and vertically adjacent squares correspond to input values that differ in only one variable. e.g... Each square represents a particular value of the input variables (,, in this case). 2...... NOTE : numbering on the edge of the Karnaugh Map - Gray coded 22 Example Karnaugh Maps Further Example. f =. +. +. = +. To use a Karnaugh map to obtain a logic expression, look for groupings of ones, e.g.....( + )..( + ) f =. +. 23 OR. f = +. 24 4
Karnaugh Map Grouping Left most-column is also adjacent to right mostcolumn, & top row is adjacent to bottom row....... lso: Groupings may overlap Minimum logic expression is obtained on minimum number of groupings Group contains power of two elements (2,4,8,6 etc) 25 Larger Karnaugh Maps Karnaugh maps can be used for more variables, e.g. (,,,D) D Movement from square to an adjacent, results in the change of only ONE variable e.g. D D f =.D +..D f =.D +. 26 Examples D D....D..D..D f =.. +..D +..D or f =.. +..D +..D an result in more than logic expression (but equivalent) annot get any groupings => no minimisation possible This is actually an EX-OR function between the 4 input variables: f = ( ) ( D) 27 Function Minimisation onstruct Truth Table: f = + (. ) + (. D) D..D (.)+(.D) f D f = + +.D 28 ommon ombinatorial ircuits in omputers N-bit Full dder One-bit Full dder (in rithmetic Logic Unit - LU) N- N- N-2 N-2 out S Full dder in inputs -,, in (each one bit) outputs - S, out (one bit) in out S out... F F F F S N- S N-2 S S arry output from one Full dder -> carry input of next 29 3 5
dder/subtractor N-bit dder/subtractor To convert into an adder/subtractor: add control input (Z): Z = -> S = + Z = -> S = - N- N- N-2 N-2 Z Note: - = + (-) Problem: How do we calculate -? out... F F F F nswer: Use two s complement, i.e. invert the N-bit binary number (Use EX-OR gates) and add (arry in) Z f S N- S N-2 S S 3 32 Multiplexers & de-multiplexers Demultiplexer a) Multiplexer - output is a selected input. e.g. a 4- multiplexer (four inputs to one output) b) de-multiplexer - opposite of a multiplexer allowing an input to appear on any one of the outputs: X X X 2 X 3 Y S S Y X X X 2 X 3 S S Y Y Y 2 Y 3 S S Y Y Y 2 Y 3 S S e.g. Y = S.S. Y = X.S.S + X S.S + X 2 S.S + X 3.S.S 33 34 Decoders and Encoders ctive High Decoder Used to either encode a set of inputs into a defined representation on the outputs, or to decode the representation into a number of outputs e.g. decoding 2 inputs to 4 unique outputs: Y X X Y Y Y 2 Y 3 X Y Y X 2 Y 3 Note that the two inputs select which output is active (active = in this case) These decoders are often used to address unique memory locations in a micro-processor system 35 Previous example decoder had an output which was active low (= ). i.e. the active output and only this output was low. an also have active high outputs : e.g. 2 to 4 line decoder (active high outputs) X X Y Y Y 2 Y 3 X X Y Y Y 2 Y 3 36 6
Sequential Logic Flip-Flop Operation So far have considered combinations of Logic gates (OMINTORIL LOGI), but now consider a circuit whose outputs are fed back to inputs: S R onsider: S =, R = -> then if S =, R = -> and then S =, R = -> then S =, R = -> P Flip-Flop P =, = P =, = P =, = P =, = 37 Output is Set (to one) when S = (& R = ), and is Reset (to Zero) when R =, (& S = ) If S = R =, then does not change This behaviour is summarised in the truth table: S R P x x - hazard condition no change The flip-flop is able to STORE a value when both S = R = 38 Flip-Flop Timing Diagram transparent latch an also view this operation in a timing diagram S R time Flip-Flop output is not just dependent on the input (as in combinatorial logic) but also on its previous behaviour - circuits of this type are called SEUENTIL circuits 39 modification to the previous flip-flop is known as the transparent latch: D Enable when Enable =, = D ( = D) Enable =, = no change (previous value) i.e. output can change only when the enable line is high 4 Truth Table locked Flip-Flops The truth table for the transparent latch can be written as: Enable D or: Enable D x where x stands for don t care. Enable D D 4 Flip-flops whose output changes only an a rising edge (clock) D lock D n lk T lock T-type T lk J lock K JK-type J K lk Often have additional gates included for set (=) and reset (=) (Important to understand the operation of these flip-flops) 42 7
Example circuits using Flip-Flops N-bit Register or Latch (stores N-bits) N-bit Shift Register register that stores and shifts a number N- N-2... D lock... lock N- N-2 N- N-2 the N-bit number ( N- N-2... ) is stored in the register on a low to high ( ) transition of the clock. The number will then appear on the outputs ( N-... ) 43 When a transition on the clock (low -> high) occurs, then each bit in the register will be shifted one place to the right 44 N-bit ounter Three-state Logic lock... Logic components considered so far have two possible states ( or ). However, there is a further gate termed a three-state buffer whose output can be placed in a third state (OFF): N-2 N- In Out Each flip-flop is clocked only on a transition of high -> low (negative clock edge) of the previous output. Note - use of a circle (on the input to the ) to indicate the negative transition Enable When Enable is High, the Input is disconnected from the output When Enable is Low, the Input is connected to the output 45 46 Three-state uses Multi-bit us an use three state buffers to allow different sources of data onto a common US. e.g. -bit wide us us E E2 When E =, will be placed on the us When E2 =, will be placed on the us e.g. 4-bit bus E E2 us Or E E2 When E =, will be placed on the us 4 4 us 4 N.. Should not have E= and E2 = at the same time! 47 When E2 =, will be placed on the us 48 8
Logic values by Voltage level: Voltage Properties of Logic Gates V max V min V max V Logic Forbidden region Logic Do NOT connect outputs together: Typically (TTL), V max = 5, V min = 2.8, V max =.8 (Three-state buffers ok) 49 Propagation Delay Each gate has a propagation delay, typically nanoseconds (x -9 s) or less. This limits the speed at which Logic circuits work. Propagation delays can be reduced by putting logic gates close together (eg. on the same I - VLSI) e.g. f Gate NOT. NND.2 ND.7 OR.2 NOR.5 Prop. Delay(ns) (values for illustration only) What is the maximum propagation delay in this circuit? 5 Logic I s Elementary logic gates and functions can be obtained in small I s (e.g. 74 - quad NND gate). However, systems commonly use programmable logic devices. e.g. PL s - Programmable rray Logic PL s - Programmable Logic rrays FPG s - Field Programmable Gate rrays (Some contain up to s simple logic gates) 5 Example Programmable Logic rray - PL an perform an ND function on a combination of any inputs (and their inverses), followed by an OR. I.e. performs a Sum of Products combinatorial function. x x 2 x n. Input uffers and inverters I. I 2nP ND array... OR array P k O. O m Output uffers. f f m 52 PL Organisation x I I 2 ND array x Example PL I I 2 ND array P = X. X 2 x 2 x 3 I 3 I 4 I 5 I 6 x 2 x 3 I 3 I 4 I 5 I 6 P 2 = X. X 3 P 3 = X. X 2. X 3 P 4 = X. X 3 f = P + P 2 + P 3 P P 2 P 3 P 4 f P P 2 P 3 P 4 f f 2 = P + P 3 + P 4 f 2 f 2 Links (Fuses) that can be broken OR array 53 Un-broken connections OR array 54 9
Summary (Logic) Processor components oolean lgebra Logic Gates Function definition using Truth Tables Logic Function Minimisation (algebraic manipulation & Karnaugh Maps) Some common functional units Example Sequential Logic devices (using flip-flops) Three state logic (uses) Programmable logic lso looked at some units that form major components of Microprocessors within a omputer System: dder / Subtractor Registers usses (data processing) (data storage) (data transfer) 55 56 Minimal µprocessor Further Reading 8 8 lements: hapter 2 dd Subtract lock rithmetic Logic Unit (LU) 8 Register us 8 OR Tannenbaum: Section 3., 3.2, 3.3. - 3.3.3 uffer oth cover combinatorial logic, oolean algebra, Sequential logic, Programmable logic. Enable 57 58