EE 457 HW 2 rithmetic Desins Redeko uvvada Name: Due: ee Website core: lease ost any questions reardin HW roblems on iazza. Refer to your class notes Unit on Fast ddition. In this class we will count the delay of an XOR ate as two (2) ate-delays. This is based on the O (sum of roducts) exression of X^Y = X Y' + X' Y, which requires two ND ates in the first level feedin an OR ate in the second. We are not countin inverters as a level of loic (ate delay). The actual VLI desin of an XOR ate does not use this O exression and thus the delay may be less than 2 ates, but is enerally more than 1 ate delay. 1. (15 ts.) Fast dder Desin 1.1. (3) Refer to the 16-bit CL adder desin resented in the 'Fast dders lides' on and calculate its delay. Is it 5, 7, or 9 ate delays? Exlain how you arrived at your answer. 1.2. (4) If you take four of these 16-bit adders and build a 64-bit adder usin an additional level of carry-lookahead loic what would be the delay of such a desin? 1.3. (2+2) What would be the comlexity of ates needed in the O imlementation of the carry-lookahead loic which can receive eiht airs of 's and 's and also a carry-in (c0) and roduce c1-c8? y comlexity of ates, we mean the hihest fan-in (number of inut ins) warranted for the ND ates and the hihest fan-in warranted for the OR ates to imlement the desin in 2-level ND-OR (O) loic. Hihest Fan-in of NDs: Hihest Fan-in of ORs: Coyriht 2004 andhi uvvada. Edited by Mark Redeko with ermission. 1
3 3 2 2 1 1 0 0 3 2 1 0 3 3 2 2 1 1 0 0 Loic (CLL) 1.4. (2+2) Consider the evaluation of: = 63 + 62 + + 1 + 0 Usin 4-inut OR ates only what is the number of ate delays required if you arrane OR ates in a linear cascade (one feedin the next and so on)? What would be the delay if you arrane them in a tree fashion? You do not have to draw any of the arranements just work out the number of ate delays required. Coyriht 2004 andhi uvvada. Edited by Mark Redeko with ermission. 2
2. (10 ts.) dders (3 + 3 + 2 + 2) Reroduced below is a 4-bit CL discussed in your class. We have arrived at the delay of this adder as 5 ate delays. dd additional loic to this adder as necessary and roduce (i) UO=Unsined ddition Overflow outut and (ii) O=ined (i.e. 2's comlement) ddition Overflow and find the delay for these oututs. Do your best to kee your delay at 5 ates or less. 3 3 2 2 1 1 0 0 3 2 1 0 3 3 2 2 1 1 0 0 Loic (CLL) DELY for UO= DELY for O= Coyriht 2004 andhi uvvada. Edited by Mark Redeko with ermission. 3
3. (30 ts.) Unsined and ined Comarison and Overflow 3.1. (5 + 5 + 5) Desin a 4-bit comarator to comare two 4-bit UNINED numbers [3:0] and [3:0] usin a 4-bit adder-subtractor iven below and additional ates as needed. Hint: Consider the overflow in unsined subtraction (as the MI LTU instruction miht do) [You may not have covered the MI instruction set yet, in which case you can inore the arenthetical comment]. 3 3 2 2 1 1 0 0 U/~DD 3 2 1 0 3 3 2 2 1 1 0 0 Loic (CLL) < = > Coyriht 2004 andhi uvvada. Edited by Mark Redeko with ermission. 4
3.2. (5 + 5 + 5)Desin a 4-bit comarator to comare two 4-bit INED numbers X[3:0] and Y[3:0] usin a 4-bit adder-subtractor iven below and additional ates as needed. Hint: Consider the overflow in sined subtraction (as the MI LT instruction miht do) [You may not have covered the MI instruction set yet, in which case you can inore the arenthetical comment]. 3 3 2 2 1 1 0 0 U/~DD 3 2 1 0 3 3 2 2 1 1 0 0 Loic (CLL) < = > Coyriht 2004 andhi uvvada. Edited by Mark Redeko with ermission. 5
4. (27 ts.) asic Comuter rithmetic 4.1. n incrementer is a secial case of an adder addin the constant 1 (ONE). Instead of usin a full CL adder to increment, a simlified incrementer can be desined as shown below. The ONE to be added can be conveyed at the INCInut which is connected to the (carry-in) inut. If INCInut is 0 the circuit will simly reroduce (+0=). Note: i = (i XOR i) XOR = (i XOR 0) XOR = i XOR i = i OR i = i OR 0 = i i = i ND i = i ND 0 = 0 = 1 if some earlier adder (F) enerates a carry and all intermediate adders (Fs) roaate the same. ince i = 0, the can only be true if there is a carry-in () and all intermediate i sinals are true. New it-cell INC 3 2 1 0 INCInut ( 1 to increment) 3 2 1 0 3 2 1 0 New_CLL_INC 4.1.1. (2+2+2) Write the oolean equations for,, roduced by the NEW_CLL_INC block. = = = 4.1.2. (3) What is the ate delay of the 4-bit incrementer? Count XOR as a 2- ate delay device. Exlain how you arrived at your answer? Coyriht 2004 andhi uvvada. Edited by Mark Redeko with ermission. 6
4.2. imilar to an incrementer, a decrementer is a secial case of an adder addin the constant -1 (MINU ONE). In a 4-bit 2's comlement, -1 = 1111 (all ones). Desin a simlified (area efficient, seed efficient) decrementer by simlifyin a CL adder that adds 1111. Do not assume that is a zero but instead treat it as a variable. New it-cell DEC 3 2 1 0 DECInut (usually 0 but not necessarily) 3 2 1 0 3 2 1 0 New_CLL_DEC Note: i = (i XOR i) XOR = (i XOR 1) XOR = ~i XOR = i XNOR 4.2.1. (1+1+1) Comlete the followin lines: i = i OR i = i OR 1 = i = i ND i = i ND 1 = = 1 if some earlier adder (F) enerates a carry and all intermediate adders (Fs) roaate the earlier carry. ince all i are in this desin, the can be true if 4.2.2. (1+2+2+2) Write the oolean equations for,, and rou enerate,, sinal roduced by the NEW_CLL_DEC. = = = = Coyriht 2004 andhi uvvada. Edited by Mark Redeko with ermission. 7
Consider a 64-bit decrementer usin three levels of the above NEW_CLL_DEC. 4.2.3. (2) Number of NEW_CLL_DECs needed: 4.2.4. (2) Number of New it-cell DECs needed: 4.2.5. (2) Delay of the 64-bit decrementer in ates (countin XOR/XNOR as 2 ate delays): 4.2.6. (2) The 64-bit decrementer is ood to decrement (circle the correct answer): Unsined numbers only ined 2's comlement numbers only oth unsined and sined 5. (18 ts.) Rile Carry dder and Carry Lookahead dder Delays 5.1. Delay of the 2-bit RC (desin 1 below) is ate delays. 5.2. Delay of the 2-bit CL (desin 2 below is ate delays 5.3. Delay of a 4-bit RC (shown in class) is ate delays. 5.4. Delay of a 4-bit CL (shown in class) is ate delays. 5.5. Delay of the 8-bit adder in desin 3 on the next. is ate delays. 5.6. Delay of the 8-bit adder in desin 4 on the next. is ate delays. 2 1 1 0 0 1 1 1 0 0 1 1 1 0 0 0 1 0 Loic (CLL) Coyriht 2004 andhi uvvada. Edited by Mark Redeko with ermission. 8
3 3 3 2 2 1 1 0 0 7 7 6 6 5 5 4 4 3 2 1 0 7 6 5 4 3 3 2 2 1 1 0 0 Loic (CLL) 4 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 6 5 5 4 3 2 1 0 3 3 2 2 1 1 0 0 Loic (CLL) Coyriht 2004 andhi uvvada. Edited by Mark Redeko with ermission. 9