DATASHEET EL71 High Performance Pin Driver FN779 Rev 3. The EL71 high performance pin driver with 3-state is suited to many ATE and level-shifting applications. The 3.A peak drive capability makes this part an excellent choice when driving high capacitance loads. Output pins OUT H and OUT L are connected to input pins V H and respectively, depending on the status of the IN pin. One of the output pins is always in tri-state, except when the OE pin is low, in which case both outputs are in tri-state mode. The isolation of the output FETs from the power supplies enables V H and to be set independently, enabling level-shifting to be implemented. This pin driver has improved performance over existing pin drivers. It is specifically designed to operate at voltages down to V across the switch elements while maintaining good speed and ON-resistance characteristics. Available in an 8 Ld SOIC package, the EL71 is specified for operation over the full - C to +8 C temperature range. Features Clocking speeds up to MHz 1ns tr/tf at pf C LOAD.ns rise and fall times mismatch.ns t ON -t OFF prop delay mismatch 3.pF typical input capacitance 3.A peak drive Low ON-resistance of 3.Ω High capacitive drive capability Operates from.v up to 16.V Pb-free (RoHS compliant) Applications ATE/burn-in testers Level shifting IGBT drivers CCD drivers OE V H IN GND LEVEL SHIFTER 3-STATE CONTROL OUT H OUT L FIGURE 1. BLOCK DIAGRAM FN779 Rev 3. Page 1 of
Pin Configuration EL71 (8 LD SOIC) TOP VIEW Ordering Information PART NUMBER (Notes 1, ) PART MARKING PACKAGE (Pb-Free) PKG. DWG. # VS+ OE IN 1 3 L O G I C 8 7 6 VH OUTH OUTL EL71CSZ 71CSZ 8 Ld SOIC M8.1E EL71CSZ-T7 (Note 3) EL71CSZ-T7A (Note 3) 71CSZ 8 Ld SOIC M8.1E 71CSZ 8 Ld SOIC M8.1E GND VL EL71CSZ-T13 (Note 3) 71CSZ 8 Ld SOIC M8.1E Pin Descriptions PIN # PIN NAME FUNCTION EQUIVALENT CIRCUIT 1 VS+ Positive Supply Voltage OE Output Enable INPUT NOTE: 1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-.. For Moisture Sensitivity Level (MSL), please see product information page for EL71. For more information on MSL, please see tech brief TB363. 3. Please refer to TB37 for details on reel specifications. Circuit 1 3 IN Input Reference Circuit 1 GND Ground VL Negative Supply and Lower Output Voltage 6 OUTL Lower Switch Output OUT L Circuit 7 OUTH Upper Switch Output V H OUT H Circuit 3 8 VH Upper Output Voltage FN779 Rev 3. Page of
Absolute Maximum Ratings (T A = + C) Supply Voltage ( to ).................................... +18V V H -, V H to GND, to V H..................................16.V Input Voltage....................... -.3V below to +.3V above V S Continuous Output Current................................. ma Storage Temperature Range........................-6 C to + C Thermal Information Ambient Operating Temperature.....................- C to +8 C Operating Junction Temperature............................+1 C Power Dissipation...................................... see curves Pb-Free Reflow Profile.................................. see TB93 CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Electrical Specifications = +1V, V H = +1V, = V, T A = + C, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T A, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN (Note ) TYP (Note ) MAX (Note ) UNITS INPUT V IH Logic 1 Input Voltage. V I IH Logic 1 Input Current V IH =.1 µa V IL Logic Input Voltage.8 V I IL Logic Input Current V IL = V.1 µa C IN Input Capacitance 3. pf R IN Input Resistance MΩ OUTPUT R OVH ON-Resistance V H to OUT H I OUT = -ma.7. Ω R OVL ON-Resistance to OUT L I OUT = +ma 3.. Ω I OUT Output Leakage Current OE = V, OUT H =, OUT L =.1 µa I PK Peak Output Current (linear resistive operation) Source 3. A Sink 3. A I DC Continuous Output Current Source/Sink ma POWER SUPPLY I S Power Supply Current Inputs = 1.3 3 ma I VH Off Leakage at V H V H = V µa SWITCHING CHARACTERISTICS t R Rise Time C L = pf 1. ns t F Fall Time C L = pf 1 ns t RF t R, t F Mismatch C L = pf. ns t D-1 Turn-Off Delay Time C L = pf 9. ns t D- Turn-On Delay Time C L = pf ns t D t D-1 - t D- Mismatch C L = pf. ns t D-3 3-state Delay Enable ns t D- 3-state Delay Disable ns FN779 Rev 3. Page 3 of
Electrical Specifications = +V, V H = +V, = -V, T A = + C, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T A, unless otherwise specified. PARAMETER DESCRIPTION CONDITION MIN (Note ) TYP (Note ) MAX (Note ) UNIT INPUT V IH Logic 1 Input Voltage. V I IH Logic 1 Input Current V IH =.1 µa V IL Logic Input Voltage.8 V I IL Logic Input Current V IL = V.1 µa C IN Input Capacitance 3. pf R IN Input Resistance MΩ OUTPUT R OVH ON-Resistance V H to OUT H I OUT = -ma 3. Ω R OVL ON-Resistance to OUT L I OUT = +ma 6 Ω I OUT Output Leakage Current OE = V, OUT H =, OUT L =.1 µa I PK Peak Output Current (linear resistive operation) Source 3. A Sink 3. A I DC Continuous Output Current Source/Sink ma POWER SUPPLY I S Power Supply Current Inputs = 1. ma I VH Off Leakage at V H V H = V µa SWITCHING CHARACTERISTICS t R Rise Time C L = pf 17 ns t F Fall Time C L = pf 17 ns t RF t R, t F Mismatch C L = pf ns t D-1 Turn-Off Delay Time C L = pf 11. ns t D- Turn-On Delay Time C L = pf 1 ns t D t D-1 - t D- Mismatch C L = pf. ns t D-3 3-state Delay Enable 11 ns t D- 3-state Delay Disable 11 ns NOTES:. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.. Typical values are for information purposes only. FN779 Rev 3. Page of
Typical Performance Curves 1. Max T J = +1 C 1.8 POWER DISSIPATION (W).8.6.. SO8 JA = 16 C/W INPUT VOLTAGE (V) 1.6 1. 1. HIGH THRESHOLD HYSTERESIS LOW THRESHOLD 7 8 1 1. 1 AMBIENT TEMPERATURE ( C) SUPPLY VOLTAGE (V) FIGURE. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE JEDEC JESD1-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD FIGURE 3. INPUT THRESHOLD vs SUPPLY VOLTAGE, T = C. 6 1.6 V OUT - SUPPLY CURRENT (ma) 1..8. ALL INPUTS = GND ALL INPUTS = ON-RESISTANCE (Ω) 3 1 V OUT - V H 1. 7.. 1. 1. SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) FIGURE. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE, T = + C FIGURE. ON-RESISTANCE vs SUPPLY VOLTAGE, I OUT = ma, T = + C, = V H, = V 3 18 RISE/FALL TIME (ns) 1 t F t R t F RISE/FALL TIME (ns) 16 1 1 t F t R t R 1 - SUPPLY VOLTAGE (V) TEMPERATURE ( C) FIGURE 6. RISE/FALL TIME vs SUPPLY VOLTAGE C L = pf, T = + C FIGURE 7. RISE/FALL TIME vs TEMPERATURE C L = PF, = 1V FN779 Rev 3. Page of
Typical Performance Curves (Continued) 17 1 1 t D- 1 t D- DELAY TIME (ns) 13 11 t D-1 DELAY TIME (ns) 8 t D-1 9 1 6 - - 7 1 SUPPLY VOLTAGE (V) TEMPERATURE ( C) FIGURE 8. PROPAGATION DELAY vs SUPPLY VOLTAGE C L = pf, T = + C FIGURE 9. PROPAGATION DELAY vs TEMPERATURE C L = pf, = 1V 7 6 RISE/FALL TIME (ns) 3 t F t R SUPPLY CURRENT (ma) 3 1 LOAD CAPACITANCE (pf) LOAD CAPACITANCE (pf) FIGURE. RISE/FALL TIME vs LOAD CAPACITANCE = +1V, T = + C FIGURE 11. SUPPLY CURRENT vs LOAD CAPACITANCE, = V H = 1V, = V, T = + C, f = khz SUPPLY CURRENT (ma) 1. = 1V = V = V.1 k k 1M M FREQUENCY (Hz) FIGURE 1. SUPPLY CURRENT vs FREQUENCY, C L = pf, T = + C FN779 Rev 3. Page 6 of
TABLE 1. TRUTH TABLE OE IN V H to OUT H OUT L to Open Open 1 Open Open 1 Closed Open 1 1 Open Closed TABLE. OPERATING VOLTAGE RANGE PIN MIN (V) MAX (V) - GND - - 16. V H - 16. - V H 16. - GND 16. 3-State Output V H TimingDiagrams V INPUT.V INVERTED OUTPUT 9% % t D1 t D t F t R Standard Test Configuration V H.7µ.1µ 1 8.1µ.7µ k OE IN 3 LOGIC 7 6 p OUT GND EL71.1µ.7µ - FN779 Rev 3. Page 7 of
Applications Information Product Description The EL71 is a high performance MHz pin driver. It contains two analog switches connecting V H to OUT H and to OUT L. Depending on the value of the IN pin, one of the two switches will be closed and the other switch open. An output enable (OE) is also supplied, which opens both switches simultaneously. Due to the topology of the EL71, should always be connected to a voltage equal to or lower than GND. V H can be connected to any voltage between and the positive supply,. The EL71 is available in the 8 Ld SOIC package. Application dependent power dissipation should be calculated to ensure that the maximum junction temperature isn t violated. 3-state Operation When the OE pin is low, the output is 3-state (floating.) The disabled output voltage is the parasitic capacitance s voltage. It can be any voltage between V H and, depending on the previous state. At 3-state, the output voltage can be driven to any voltage between V H and. The output voltage can t be driven higher than V H or lower than since the body diode at the output stage will turn on. Supply Voltage Range and Input Compatibility The EL71 is designed for operation on supplies from V to 1V (.V to 16.V maximum). Table on page 7 shows the specifications for the relationship between the, V H,, and GND pins. All input pins are compatible with both 3V and V CMOS signals. With a positive supply () of V, the EL71 is also compatible with TTL inputs. Power Supply Bypassing When using the EL71, it is very important to use adequate power supply bypassing. The high switching currents developed by the EL71 necessitate the use of a bypass capacitor between the and GND pins. It is recommended that a.µf tantalum capacitor be used in parallel with a.1µf low-inductance ceramic MLC capacitor. These should be placed as close to the supply pins as possible. It is also recommended that the V H and pins have some level of bypassing, especially if the EL71 is driving highly capacitive loads. Power Dissipation Calculation When switching at high speeds, or driving heavy loads, the EL71 drive capability is limited by the rise in die temperature brought about by internal power dissipation. For reliable operation die temperature must be kept below T JMAX (+1 C). It is necessary to calculate the power dissipation for a given application prior to selecting the package type. Power dissipation may be calculated: PD = V S I S + C INT V S f + C L V OUT f (EQ. 1) where: V S is the total power supply to the EL71 (from to GND) V OUT is the swing on the output (V H - ) C L is the load capacitance C INT is the internal load capacitance (pf max) I S is the quiescent supply current (3mA max) f is frequency Having obtained the application s power dissipation, a maximum package thermal coefficient may be determined, to maintain the internal die temperature below T JMAX : T JMAX T MAX (EQ. ) JA = ---------------------------------------------- PD where: T JMAX is the maximum junction temperature (+1 C) T MAX is the maximum operating temperature PD is the power dissipation calculated above JA thermal resistance on junction to ambient JA is 16 C/W for the SO8 package when using a standard JEDEC JESD1-3 single-layer test board. If T JMAX is greater than +1 C when calculated using the Equation, then one of the following actions must be taken: 1. Reduce JA the system by designing more heatsinking into the PCB (as compared to the standard JEDEC JESD1-3).. Derate the application either by reducing the switching frequency, the capacitive load, or the maximum operating (ambient) temperature (T MAX ). FN779 Rev 3. Page 8 of
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE FN779.3 Updated datasheet to new Intersil template. Updated the Ordering Information table on page by removing the obsolete products and adding the -T7A part. Added revision history and about Intersil. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support Copyright Intersil Americas LLC 3-1. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN779 Rev 3. Page 9 of
Package Outline Drawing M8.1E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev, 8/9.9 ±. A DETAIL "A". ±.3 B 6. ±. 3.9 ±. PIN NO.1 ID MARK 1.7.3 ±.76 (.3) x ± TOP VIEW. MCAB SIDE VIEW B 1.7 MAX 1. ±.1.17 ±.7 SIDE VIEW A. GAUGE PLANE C SEATING PLANE. C.63 ±.3 (1.7) (.6) DETAIL "A" (1.) NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. (.). 3... 6. Dimensioning and tolerancing conform to AMSE Y1.m-199. Unless otherwise specified, tolerance : Decimal ±. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed.mm per side. The pin #1 identifier may be either a mold or mark feature. Reference to JEDEC MS-1. TYPICAL RECOMMENDED LAND PATTERN FN779 Rev 3. Page of