Hold Time Illustrations

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Transcription:

Hold Time Illustrations EE213-L09-Sequential Logic.1 Pingqiang, ShanghaiTech, 2018

Hold Time Illustrations EE213-L09-Sequential Logic.2 Pingqiang, ShanghaiTech, 2018

Hold Time Illustrations EE213-L09-Sequential Logic.3 Pingqiang, ShanghaiTech, 2018

Hold Time Illustrations EE213-L09-Sequential Logic.4 Pingqiang, ShanghaiTech, 2018

Hold Time Illustrations EE213-L09-Sequential Logic.5 Pingqiang, ShanghaiTech, 2018

Outline Sequential logics and their timing metrics Storage mechanisms Static latch/register (flip-flop) Dynamic latch/register Other latches/registers TSPC latch/register Pulse-triggered latch EE213-L09-Sequential Logic.6 Pingqiang, ShanghaiTech, 2018

Dynamic Register master slave D A Q T 1 I M B 1 T 2 I 2 Q master transparent slave hold C 1 C 2 t su = t hold = t c-q = t pd_tx zero 2t pd_inv + t pd_tx master hold slave transparent EE213-L09-Sequential Logic.7 Pingqiang, ShanghaiTech, 2018

Pseudo-Static Dynamic Latch Robustness considerations limit the use of dynamic FF s coupling between signal nets and internal storage nodes can inject significant noise and destroy the FF state leakage currents cause state to leak away with time A simple fix is to make the circuit pseudo-static Q M B C 2 Q EE213-L09-Sequential Logic.8 Pingqiang, ShanghaiTech, 2018

Dynamic Flip-Flop Race Conditions master slave D Q M A T 1 I 1 T B 2 I 2 Q C 1 C 2 0-0 overlap race condition t overlap-0-0 < t T1 + t I1 + t T2 1-1 overlap race condition t overlap-1-1 < t hold EE213-L09-Sequential Logic.9 Pingqiang, ShanghaiTech, 2018

Fix 1: Dynamic Two-Phase Flip-Flop master slave 1 2 D Q T 1 I M 1 T 2 I 2 Q 1 C 1 C 2 2 master transparent slave hold 1 2 t non_overlap master hold slave transparent EE213-L09-Sequential Logic.10 Pingqiang, ShanghaiTech, 2018

Fix 2: Dynamic C 2 MOS (Clocked CMOS) Flip-Flop A clock-skew insensitive FF Master Slave M 2 M 6 D M 4 M 3 Q M C 1 M 8 M 7 C 2 Q M 1 M 5 EE213-L09-Sequential Logic.11 Pingqiang, ShanghaiTech, 2018

C 2 MOS Flip-Flop A clock-skew insensitive FF Master Slave M 2 M 6 D off off M 4 M 3 on on Q M C 1 on on M 8 M 7 off off C 2 Q M 1 M 5 master transparent slave hold master hold slave transparent EE213-L09-Sequential Logic.12 Pingqiang, ShanghaiTech, 2018

C 2 MOS Flip-Flop: 0-0 Overlap Case Master Slave M 2 M 6 D M 4 M 3 Q M C 1 M 8 M 7 C 2 Q M 1 M 5 EE213-L09-Sequential Logic.13 Pingqiang, ShanghaiTech, 2018

C 2 MOS Flip-Flop: 0-0 Overlap Case Clock-skew insensitive as long as the rise and fall times of the clock edges are sufficiently small M 2 M 6 D 0 0 M 4 Q M C 1 M 8 C 2 Q M 1 M 5 EE213-L09-Sequential Logic.14 Pingqiang, ShanghaiTech, 2018

C 2 MOS Flip-Flop: 1-1 Overlap Case Master Slave M 2 M 6 D M 4 M 3 Q M C 1 M 8 M 7 C 2 Q M 1 M 5 EE213-L09-Sequential Logic.15 Pingqiang, ShanghaiTech, 2018

C 2 MOS Flip-Flop: 1-1 Overlap Case M 2 M 6 D Q M 1 1 C 1 M 3 M 7 C 2 Q M 1 M 5 1-1 overlap constraint t overlap1-1 < t hold EE213-L09-Sequential Logic.16 Pingqiang, ShanghaiTech, 2018

Outline Sequential logics and their timing metrics Storage mechanisms Static latch/register (flip-flop) Dynamic latch/register Other latches/registers TSPC latch/register Pulse-triggered latch EE213-L09-Sequential Logic.17 Pingqiang, ShanghaiTech, 2018

True Single Phase Clock (TSPC) Latches Positive Latch (Transparent when CLK=1) Negative Latch (Transparent when CLK=0) EE213-L09-Sequential Logic.18 Pingqiang, ShanghaiTech, 2018

Including Logic in TSPC NAND-2 Latch EE213-L09-Sequential Logic.19 Pingqiang, ShanghaiTech, 2018

TSPC Register EE213-L09-Sequential Logic.20 Pingqiang, ShanghaiTech, 2018

Outline Sequential logics and their timing metrics Storage mechanisms Static latch/register (flip-flop) Dynamic latch/register Other latches/registers TSPC latch/register Pulse-triggered latch EE213-L09-Sequential Logic.21 Pingqiang, ShanghaiTech, 2018

Pulse-Triggered Latches: An Alternative Approach Ways to design an edge-triggered sequential cell: Data Master-Slave Latches D Q D Q Pulse-Triggered Latch L1 L2 L Data D Q Clk Clk Clk Clk Clk EE213-L09-Sequential Logic.22 Pingqiang, ShanghaiTech, 2018

How to Generate Pulse? EE213-L09-Sequential Logic.23 Pingqiang, ShanghaiTech, 2018

Why not Route the Pulse? EE213-L09-Sequential Logic.24 Pingqiang, ShanghaiTech, 2018

Summary: Three Sequencing Methods EE213-L09-Sequential Logic.25 Pingqiang, ShanghaiTech, 2018

Choosing a Clocking Strategy Choosing the right clocking scheme affects the functionality, speed, and power of a circuit Two-phase designs + robust and conceptually simple - - need to generate and route two clock signals have to design to accommodate possible skew between the two clock signals Single phase designs + only need to generate and route one clock signal + supported by most automated design methodologies + don t have to worry about skew between the two clocks - have to have guaranteed slopes on the clock edges EE213-L09-Sequential Logic.26 Pingqiang, ShanghaiTech, 2018

Next Lecture and Reminders Next lecture Timing Chapter 10 Chapter 9/12 EE213-L09-Sequential Logic.27 Pingqiang, ShanghaiTech, 2018

Further Reading EE213-L09-Sequential Logic.28 Pingqiang, ShanghaiTech, 2018

More Complicated Latches: Cross-Coupled NOR-Based S-R Latch Active-HIGH input NAND-Based S-R Latch EE213-L09-Sequential Logic.29 Pingqiang, ShanghaiTech, 2018

Cross-Coupled Register Gated S-R Latch Gated D Latch J-K Flip-Flop D Flip-Flop Ronald J. Tocci, et al., Digital Systems Principles and Applications, 11 th ed., Prentice Hall, 2011. EE213-L09-Sequential Logic.30 Pingqiang, ShanghaiTech, 2018

Non-Bistable Sequential Circuits Schmitt Trigger V out V OH In O u t VTC with hysteresis Restores signal slopes V OL V M V M+ V in EE213-L09-Sequential Logic.31 Pingqiang, ShanghaiTech, 2018

Noise Suppression using Schmitt Trigger EE213-L09-Sequential Logic.32 Pingqiang, ShanghaiTech, 2018

CMOS Schmitt Trigger V DD M 2 M 4 V in X V out M 1 M 3 Moves switching threshold of the first inverter EE213-L09-Sequential Logic.33 Pingqiang, ShanghaiTech, 2018

Multi-Vibrator Circuits R S B i s t a b l e M u l t i v i b r a t o r f l i p - f l o p, S c h m i t t T r i g g e r T M o n o s t a b l e M u l t i v i b r a t o r o n e - s h o t A s t a b l e M u l t i v i b r a t o r o s c i l l a t o r EE213-L09-Sequential Logic.34 Pingqiang, ShanghaiTech, 2018

Transition-Triggered Monostable In D E L A Y O u t t d t d EE213-L09-Sequential Logic.35 Pingqiang, ShanghaiTech, 2018

Astable Multivibrators (Oscillators) 0 1 2 N-1 Ring Oscillator Simulated response of 5-stage oscillator EE213-L09-Sequential Logic.36 Pingqiang, ShanghaiTech, 2018

Voltage Controller Oscillator (VCO) S c h m i t t T r i g g e r V D D V D D r e s t o r e s s i g n a l s l o p e s M 6 M 4 M 2 In M 1 I ref I ref V c o n t r M 5 M 3 C u r r e n t s t a r v e d i n v e r t e r 6 t p H L ( n s e c ) 4 2 0. 0 0. 5 1. 5 2. 5 V c o n t r ( V ) p r o p a g a t i o n d e l a y a s a f u n c t i o n o f c o n t r o l v o l t a g e EE213-L09-Sequential Logic.37 Pingqiang, ShanghaiTech, 2018

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