CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 18: Static Sequential Circuits [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11 CMPEN 411 L18 S.1
A Chip Example Type Gate_Count Area ---------------------------- NAND 70232 425102 AND 44417 310227 OR 21652 139790 NOR 43635 361006 XOR 17095 211430 XNOR 9699 127071 INV 78870 269643 MUX 34505 422824 REG 112805 2737435 MEM 138 17937962 OA 37878 379645 AO 40396 480452 ADD 4185 87885 ------------------------ total gate count 502597 total gate count for combinatorial 389654 total area 23,766,927 um2 total area for combinatorial 3,091,530 um2 87% of the area are memory and registers Sp11 CMPEN 411 L18 S.2
Sequential Logic Inputs Current State Combinational Logic Outputs Next State clock Sp11 CMPEN 411 L18 S.3
Timing Metrics clock clock t su t hold time In data stable t c-q time Out output stable output stable time Sp11 CMPEN 411 L18 S.4
System Timing Constraints Inputs Current State Combinational Logic Outputs Next State clock T (clock period) t cdreg + t cdlogic t hold T t c-q + t plogic + t su Sp11 CMPEN 411 L18 S.5
Static vs Dynamic Storage Static storage preserve state as long as the power is on have positive feedback (regeneration) with an internal connection between the output and the input useful when updates are infrequent (clock gating) Dynamic storage store state on parasitic capacitors only hold state for short periods of time (milliseconds) require periodic refresh usually simpler, so higher speed and lower power Sp11 CMPEN 411 L18 S.6
Latches vs Flipflops Latches level sensitive circuit that passes inputs to when the clock is high (or low) - transparent mode input sampled on the falling edge of the clock is held stable when clock is low (or high) - hold mode Flipflops (edge-triggered) edge sensitive circuits that sample the inputs on a clock transition - positive edge-triggered: 0 1 - negative edge-triggered: 1 0 built using latches (e.g., master-slave flipflops) Sp11 CMPEN 411 L18 S.7
Positive and Negative Latches clock clock In In Out Out Sp11 CMPEN 411 L18 S.8
Review: The Regenerative Property V i1 V o1 V i2 V o2 cascaded inverters A C B If the gain in the transient region is larger than 1, only A and B are stable operation points. C is a metastable operation point. V i1 = V o2 Sp11 CMPEN 411 L18 S.9
Bistable Circuits The cross-coupling of two inverters results in a bistable circuit (a circuit with two stable states) V i1 V i2 Have to be able to change the stored value by making A (or B) temporarily unstable by increasing i the loop gain to a value larger than 1 done by applying a trigger pulse at V i1 or V i2 the width of the trigger pulse need be only a little larger than the total propagation delay around the loop circuit (twice the delay of an inverter) Two approaches used cutting the feedback loop (mux based latch) overpowering the feedback loop (as used in SRAMs) Sp11 CMPEN 411 L18 S.10
Bistable Circuits The cross-coupling of two inverters results in a bistable circuit (a circuit with two stable states) V i1 V i2 Have to be able to change the stored Two approaches used cutting the feedback loop (mux based latch) overpowering the feedback loop (as used in SRAMs) Sp11 CMPEN 411 L18 S.11
Review (from CSE 271): SR Latch S R! S R! 0 0! memory 1 0 1 0 set 0 1 0 1 reset 1 1 0 0 disallowed Sp11 CMPEN 411 L18 S.12
Review (from CSE 271): Clocked D Latch D! D clock transparent mode clock clock hold mode Sp11 CMPEN 411 L18 S.13
MUX Based Latches Change the stored value by cutting the feedback loop feedback 1 D 0 feedback 0 D 1 Negative Latch Positive Latch = &! & D transparent when the clock is low =! & & D transparent when the clock is high Sp11 CMPEN 411 L18 S.14
TG MUX Based Latch Implementation! D input sampled (transparent mode) D! feedback (hold mode) Sp11 CMPEN 411 L18 S.15
PT MUX Based Latch Implementation! D! Reduced area and clock load, but a threshold drop at output of pass transistors so reduced noise margins and performance Sp11 CMPEN 411 L18 S.16! input sampled (transparent mode) feedback (hold mode)
Latch Race Problem B B B Which value of B is stored? Two-sided clock constraint T t c-q + t plogic + t su T high < t c-q + t cdlogic Sp11 CMPEN 411 L18 S.17
Master Slave Based ET Flipflop D 0 1 1 D 0 M Slave Master D clock = 0 transparent hold M = 0 1 hold transparent Sp11 CMPEN 411 L18 S.18
MS ET Implementation Master Slave Sa I 2 T I I 3 5 T I 2 4 6 M D I I 1 T 1 4 T 3! Sp11 CMPEN 411 L18 S.19
MS ET Implementation Master Slave Sa I 2 T I I 3 5 T I 2 4 6 M D I I 1 T 1 4 T 3 master transparent slave hold master hold slave transparent! Sp11 CMPEN 411 L18 S.20
MS ET Timing Properties Assume propagation delays are t pd_inv and t pd_tx, that the contamination delay is 0, and that the inverter delay to derive! is 0 Set-up time - time before rising edge of that D must be valid Propagation delay - time for M to reach Hold time - time D must be stable after rising edge of - Sp11 CMPEN 411 L18 S.21
MS ET Timing Properties Assume propagation delays are t pd_inv and t pd_tx, that the contamination delay is 0, and that the inverter delay to derive! is 0 Set-up time - time before rising edge of that D must be valid t su = 3 * t pd_inv + t pd_tx Propagation delay - time for M to reach t c-q = t pd_inv + t pd_tx Hold time - time D must be stable after rising edge of t hold = zero Sp11 CMPEN 411 L18 S.22
Set-up Time Simulation 3 2.5 2 M t su = 0.21 ns 15 1.5 t setup Volts 1 05 0.5 0 D I 2 out -0.5 0 0.2 0.4 0.6 0.8 1 Time (ns) works correctly Sp11 CMPEN 411 L18 S.23
Set-up Time Simulation 3 2.5 2 I 2 out t su = 0.20 ns 15 1.5 Volts 1 0.5 t setup D 0 M -0.5 fails 0 0.2 0.4 0.6 0.8 1 Time (ns) Sp11 CMPEN 411 L18 S.24
Propagation Delay Simulation 3 2.5 2 t c-q(lh) = 160 psec 1.5 Volts 1 0.5 t c-q(lh) t c-q(hl) t c-q(hl) = 180 psec 0-0.5 0 0.5 1 1.5 2 2.5 Time (ns) Sp11 CMPEN 411 L18 S.25
Power PC Flipflop! 1 D 0 0 1 1!! Sp11 CMPEN 411 L18 S.26
Power PC Flipflop! 1 D 0 1 0 1 1 00 1 0! master transparent slave hold master hold slave transparent! Sp11 CMPEN 411 L18 S.27
Reduced Load MS ET FF Clock load per register is important since it directly impacts the power dissipation of the clock network. Can reduce the clock load (at the cost of robustness) by making the circuit ratioed D T 1!! I 1 I 3 M T 2 I 2 I 4 reverse conduction to switch the state of the master, T 1 must be sized to overpower I 2 to avoid reverse conduction, I 4 must be weaker than I 1 Sp11 CMPEN 411 L18 S.28
Non-Ideal Clocks!! Ideal clocks Non-ideal clocks clock skew 1-11 overlap 0-0 overlap Sp11 CMPEN 411 L18 S.29
Example of Clock Skew Problems X! D P A 1 I P 3 1 I I 2 3 I 4 B P P 2 4!! Race condition direct path from D to during the short time when both and! are high (1-1 overlap) Undefined state both B and D are driving A when and! are both high Dynamic storage when and! are both low (0-00 overlap) Sp11 CMPEN 411 L18 S.30
Pseudostatic Two-Phase ET FF 1 X 2 D P A 1 I P 1 I 3 I 2 3 I 4 B P P 2 4! master transparent slave hold 1 2 2 t non_overlap dynamic storage 1 master hold slave transparent Sp11 CMPEN 411 L18 S.31
Two Phase Clock Generator A 1 B 2 A B 1 2 Sp11 CMPEN 411 L18 S.32
Review (from CSE 271): SR Latch S R! S R! 0 0! memory 1 0 1 0 set 0 1 0 1 reset 1 1 0 0 disallowed Sp11 CMPEN 411 L18 S.33
Review (from CSE 271): Clocked D Latch D! D clock transparent mode clock clock hold mode Sp11 CMPEN 411 L18 S.34
Ratioed CMOS Clocked SR Latch 0! off M2 on M4 1 M6 M8 on M1 M3 off 0 S M5 M7 off on R 1 Sp11 CMPEN 411 L18 S.35
Ratioed CMOS Clocked SR Latch off on on off M2 M4 1 0 1 0! off on off on 0 1 M6 M8 0 1 M1 M3 on off off on 0 S R M5 M7 off on 1 Sp11 CMPEN 411 L18 S.36
Sizing Issues 2 1.5 so W/L 5and6 > 3! (Volts) 1 0.5 0 2 2.5 3 3.5 4 W/L 5and6 W/L 2and4 = 1.5μm/0.25 μm W/L 1and3 = 0.5μm/0.25 μm Sp11 CMPEN 411 L18 S.37
Transient Response 3 SET &! (Vol lts) 2 1 t c-!! t c- 0 0.9 1 1.1 1.2 1.3 1.4 1.5 Time (ns) Sp11 CMPEN 411 L18 S.38
6 Transistor CMOS SR Latch R S R M5! M2 M4 M6 S M1 M3 Will see this structure in SRAM design Sp11 CMPEN 411 L18 S.39
Next Lecture and Reminders Next lecture Dynamic sequential circuits - Reading assignment Rabaey, et al, 7.3, 7.7 Sp11 CMPEN 411 L18 S.40