EE141-pring 2008 igital Integrated ircuits Lecture 28 Multipliers 1 Announcements Project Phase 2 Posted ign up for one of three project goals today Graded Phase 1 and Midterm 2 will be returned next Fr Hw Lab in week 13 2 2
lass Material Last lecture Power Intro to sequential Today s lecture: Intermezzo Multipliers Reading hapter 11 3 Multipliers 4
Binary Multiplication + x 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 0 Multiplicand Multiplier Partial products Result 5 Binary Multiplication Z M+ N 1 X = Y = Z k 2 k k = 0 M 1 X i 2 i N 1 Y j 2 j = i = 0 j = 0 = M 1 i = 0 X Y = N 1 j = 0 = X i Y j 2 i+ j with M 1 X i 2 i i = 0 N 1 Y j 2 j j = 0 6
The Array Multiplier X 3 X 2 X 1 X 0 Y 0 X 3 X 2 X 1 X 0 Y 1 Z 0 HA HA X3 X 2 X 1 X 0 Y 2 Z 1 HA X3 X 2 X 1 X 0 Y 3 Z 2 HA Z 7 Z 6 Z 5 Z 4 Z 3 7 The M-byM by-n N Array Multiplier: ritical Path HA HA HA ritical Path 1 ritical Path 2 ritical Path 1 & 2 HA ( 1) ( 2) ( 1) t M + N t + N t + t mult carry sum and 8
Transmission-Gate Full Adder Balanced t sum and t carry P V A V A A P i i P um Generation V B A P B P A P V o arry Generation i i etup A i P 9 arry-ave Multiplier HA HA HA HA HA HA HA HA Vector Merging Adder ( 1) t = t + N t + t mult and carry merge 10
Multiplier Floorplan X 3 X 2 X 1 X 0 Y 0 Y 1 Z 0 HA Multiplier ell Multiplier ell Y 2 Z 1 Vector Merging ell Y 3 Z 2 X and Y signals are broadcasted through the complete array. ( ) Z 7 Z 6 Z 5 Z 4 Z 3 11 Wallace-Tree Multiplier y 0 y 1 y2 i-1 y 0 y 1 y 2 y 3 y 4 y 5 y 3 i i-1 i i i-1 i-1 y 4 i i-1 i i-1 y 5 i 12
Wallace-Tree Multiplier Partial products First stage 6 5 4 3 2 1 0 6 5 4 3 2 1 0 Bit position (a) (b) econd stage Final adder 6 5 4 3 2 1 0 6 5 4 3 2 1 0 (c) HA (d) 13 Wallace-Tree Multiplier Partial products x 3 y 3 x 3 y 2 x 2 y 2 x 3 y 1 x 1 y 2 x 3 y 0 x 1 y 1 x 2 y 0 x 0 y 1 x 2 y 3 x1 y 3 x 0 y 3 x 2 y 1 x 0 y 2 x 1 y 0 x 0 y 0 First stage HA HA econd stage H Final adder z 7 z 6 z 5 z 4 z 3 z 2 z 1 z 0 14
Multipliers ummary Optimization constraints different than in binary adder Once again: Need to identify critical path And find ways to use parallelism to reduce it Other possible techniques Logarithmic versus linear (Wallace Tree Mult) ata encoding (Booth) Pipelining First glimpse at system level optimization 15 The Binary hifter Right nop Left A i B i A i-1 B i-1 Bit-lice i... 16
The Barrel hifter A 3 B 3 h1 A 2 B 2 h2 : ata Wire A 1 B 1 : ontrol Wire h3 A 0 B 0 h0 h1 h2 h3 Area ominated by Wiring 17 4x4 Barrel hifter A 3 A 2 A 1 A 0 h0 h1 h2 h3 Buffer Width barrel ~ 2 p m M 18
Logarithmic hifter h1 h1 h2 h2 h4 h4 A 3 B 3 A 2 B 2 A 1 B 1 A 0 B 0 19 0-77 bit Logarithmic hifter A 3 Out3 A 2 Out2 A 1 Out1 A 0 Out0 width log p m K 1 K [ 2K + ( 1+ 2 +... + 2 )] = p ( 2 + 2K 1) m 20
equential Logic 21 Latch versus Register (Flip-flop) - REVIEW Latch: level-sensitive clock is low - hold mode clock is high - transparent Register: edge-triggered stores data when clock rises lk lk lk lk 22
haracterizing Timing - REVIEW t lk lk t Register t Latch 23 Timing efinitions - REVIEW t su t hold t Register ATA TABLE t t c q ATA TABLE t 24
torage Mechanisms tatic ynamic 25 Positive Feedback: Bi-tability V i1 V o1 =V i2 V o2 V o1 V o1 = V i2 V o2 =V i1 V i1 V o2 A V o1 = V i2 B V o2 = V i1 26
Meta-tability V i2 5V o1 A V i2 5V o1 A B B d V i1 5V o2 d V i1 5V o2 Gain should be larger than 1 in the transition region 27 Writing into a tatic Latch Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states onverting into a MUX Forcing the state (can implement as NMO-only) 28
Pseudo-tatic Latch 29 Mux-Based Latches Negative latch (transparent when = 0) Positive latch (transparent when = 1) 1 0 0 1 = lk + lk In = lk + lk In EE141 30
Mux-Based Latch 31 Mux-Based Latch M M NMO only Non-overlapping clocks 32
Latch-Based esign N latch is transparent when Φ = 0 φ P latch is transparent when Φ = 1 N Latch Logic P Latch Logic 33 Master-lave (Edge-Triggered) Register Master lave 1 0 M 0 1 M Two opposite latches trigger on edge Also called master-slave latch pair 34
Master-lave Register Multiplexer-based latch pair I 2 T 2 I 3 I 5 T 4 I 6 I 1 T 1 M I 4 T 3 35 lk- elay 2.5 1.5 t clk-q(lh) t clk-q(hl) Volts 0.5 20.5 0 0.5 1 1.5 2 2.5 time, nsec 36
etup Time 3.0 2.5 3.0 2.5 2.0 M 2.0 I 2 2 T 2 Volts 1.5 1.0 Volts 1.5 1.0 0.5 I 2 2 T 2 0.5 M 0.0 0.0 2 0.5 0 0.2 0.4 0.6 0.8 1 time (nsec) 2 0.5 0 0.2 0.4 0.6 0.8 1 time (nsec) (a) T setup 5 0.21 nsec (b) T setup 5 0.20 nsec 37