InGaAs Double-Gate Fin-Sidewall MOSFET Alon Vardi, Xin Zhao and Jesús del Alamo Microsystems Technology Laboratories, MIT June 25, 214 Sponsors: Sematech, Technion-MIT Fellowship, and NSF E3S Center (#939514) 1
Outline Motivation Process technology Results and analysis Conclusions 2
Motivation III-V MOSFET for sub 1 nm CMOS Outstanding planar devices, but need tighter channel control through 3D designs Concerns about nano-structure sidewall fabricated by RIE Curing of plasma etching damage: forming gas annealing, digital etch Sidewall MOS 3
Key technologies BCl 3 /SiCl 4 /Ar RIE of InGaAs nanostructures with smooth, vertical sidewall and high aspect ratio (>1). 24 nm 15 nm Digital etch (DE): self-limiting O 2 plasma oxidation + H 2 SO 4 oxide removal Fins 4 nm 3 nm Zhao, EDL 214 Shrinks fin width by 2 nm per cycle Unchanged shape Reduced roughness As etched 5 cycles DE Lin, EDL 214 4
InGaAs finfet process flow 1 nm thick, n-ingaas N d =1 18 cm -3 SiO 2 Gate dielectric Mo InAlAs SI-InP Fin Patterning Gate stack Thick Top Gate Oxide G D S G Gate Patterning Contacts + Pads 5
InGaAs finfets = InGaAs Typical device consists of 1 fins, L g =5 µm Process splits: Number of digital etch cycles: 1, 2 and 4 HfO 2 vs. Al 2 O 3 (same EOT of 4 nm) w/ and w/o forming gas anneal (FGA): 3 min, 4 o C 6
Electrical Characteristics I D [µa/µm] 2 15 1 5 Al 2 O 3, 4 cyc DE, FGA =12 nm L g =5 µm V GS = V..1.2.3.4.5 V DS V GS =.5 V I D [µa/µm] 15 =5 nm 1 5 V DS =5 mv =37 nm -1. -.5..5 1. V GS =12 nm Current normalized to active layer thickness (1 nm) and number of fins Good electrostatic control over fin sidewalls V t 7
Subthreshold characteristics 8 =37 nm I D,I G [µa/µm] 1 2 1 1 1 1-1 1-2 1-3 1-4 1-5 1-6 Al 2 O 3, 4 cyc DE, FGA =37 nm -1. -.5..5 1. V GS I D =12 nm =5 nm V DS =5mV Subthreshold characteristics unrelated to I G and governed by D it on fin sidewalls I G S [mv/dec] [mv/dec] 6 4 2 =12 nm -1. -.5..5 1. V GS 8 6 4 2 1 15 2 25 3 35 4 8
: Al 2 O 3 vs. HfO 2 [mv/dec] 14 12 1 8 6 4 2 4 cyc DE, FGA HfO 2 Al 2 O 3 1 15 2 25 3 35 4 Narrow : (HfO 2 ) (Al 2 O 3 ) Wide : (HfO 2 ) > (Al 2 O 3 ) 9
: Effect of forming gas annealing 14 12 Al 2 O 3, 4 cyc DE 14 12 HfO 2, 4 cyc DE [mv/dec] 1 8 6 4 2 Before FGA After FGA 1 15 2 25 3 35 4 [mv/dec] 1 8 6 4 2 Before FGA After FGA 1 15 2 25 3 35 4 FGA S at all on both oxides 1
: Effect of digital etching [mv/dec] 14 12 1 8 6 4 2 Al 2 O 3, FGA Cycles 2 Cycles 4 Cycles 1 15 2 25 3 35 4 45 Narrow : S not affected by digital etch Wide : #DE cycles 11
Simulations: Ideal interface [mv/dev] 2D Poisson-Schrödinger (nextnano) 15 1 5 15 2 25 3 35 4 n [1 18 cm -3 ].8.6.4.2 n f [cm -1 ] S [mv/dec] 1 8 1 6 Wf =37 nm 1 4 1 2 1 1-2 1-4 1-6 4 3 2 1-2. -1.5-1. -.5..5 1. =37 nm -2. -1.5-1. -.5..5 1. V G =17 nm 6 mv/dec V G Onset of sidewall inversion V t shift =17 nm SS = ddvv gg ddllllll 1 (nn ff ) D it = =6 mv/dec, independent of 12
Simulations: uniform D it across bandgap 1E13 D it [cm -2 ev -1 ] [mv/dev] 1E12..2.4.6 Ec 15 1 5 2 1 D it =3x1 12 cm -2 ev -1 2 1 2 3 D it = 1 E-E V [ev] 6 1 + qqdd iiii CC oooo 15 2 25 3 35 4 S [mv/dec] Sidewall Inversion onset 4 2 1 =37 nm -1.5-1. -.5. V G D it > (uniform) =6 1 + qqdd iiii, independent of W CC f oooo Onset of inversion shifts to negative voltage (stretch out) =17 nm 13
D it [cm -2 ev -1 ] [mv/dev] 1E13 2 18 16 14 12 1 8 6 Simulations: D it rising toward VB 2 1 D it = 1E12..2.4.6 Ec E-E V [ev] 15 2 25 3 35 4 3 3 1 2 S [mv/dec] 4 3 2 1 2 1 =37nm 3-1.5-1. -.5. V G =17nm D it rising towards VB: for different probe D it at different locations in the band gap 14
Simulations: ϕ s qϕ t1 1 1 qϕ t2 2 > 1 X X 2 3 > 2 qϕ t3 3 ϕ t V t (negative V t shift) probe D it closer to VB 15
Effect of Oxide type on D it profile D it [mv/dec] 14 12 1 8 6 4 2 4 cyc DE, FGA HfO 2 Al 2 O 3 1 15 2 25 3 35 4 E V HfO 2 Al 2 O 3 Position in bandgap E C Al 2 O 3 yield better D it than HfO 2 in lower part of bandgap 16
Effect of FGA on D it profile 14 12 Al 2 O 3, 4 cyc DE [mv/dec] 1 8 6 4 2 14 12 Before FGA After FGA 1 15 2 25 3 35 4 HfO 2, 4 cyc DE D it FGA [mv/dec] 1 8 6 4 2 Before FGA After FGA 1 15 2 25 3 35 4 E V Position in bandgap E C FGA reduces D it everywhere in bandgap 17
Effect of DE on D it profile D it 14 12 1 Cycles 2 Cycles #DE [mv/dec] 8 6 4 2 4 Cycles 1 15 2 25 3 35 4 45 E V Position in bandgap E C DE reduces D it in lower part of bandgap 18
Towards a more detailed analysis: Al 2 O 3, 4 cyc DE, FGA Mobility extraction C g [µf/cm 2 ].8 V DS =V.7.6.5.4 =37 nm.3.2 1MHz.1 =12 nm. -1. -.5..5 1. V GS µ [cm 2 /Vsec] 8 W =27 nm f 6 4 2 =12 nm.5 1. V GS Mobility is 5-7 times smaller than expected µ sidewall scattering From I D and µ extract n f 19
Fitting of D it profile n f [cm -1 ] 1 8 1 6 1 4 1 2 1 1-2 1-4 1-6 Al 2 O 3, 4 cyc DE, FGA =7 nm =1 nm -2. -1.5-1. -.5..5 1. V GS 6 mv/dec Ideal Measured n f [cm -1 ] 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 =37 nm =12 nm Measurement Simulation: U-shape D it -1. -.5..5 1. V GS 1 U-shape D it profile provides excellent agreement with measurements D it [1 12 cm -2 ev -1 ] 1.5 Ec 1. E-E v [ev] 2
Comparison to planar structures Al 2 O 3 /InGaAs This work Brammertz, APL 29 D it distribution on properly prepared dry etched sidewalls approaches that of planar structures 21
Conclusions Study of D it on dry etched nano-structure sidewalls U shape D it distribution as in planar MOSFETs FGA reduces D it everywhere while DE lowers D it toward the valence band HfO 2 and Al 2 O 3 give comparable results near CB, but rise of D it toward VB stronger for HfO 2 HfO 2 #DE FGA Al 2 O 3 With all treatments, D it level approaches level obtained on planar structures 22