EE247 Lecure 18 ADC Converers Sampling Sampling swich induced disorion Sampling swich conducance dependence on inpu volage Sampling swich charge injecion Complemenary swich Use of dummy device Boom-plae swiching Track & hold circui T/H circui incorporaing gain EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 1 Sampling Disorion Effec of Supply Volage 10bi ADC & T/τ = 10 V DD V h = 2V V FS = 1V Effec of lower supply volage on sampling disorion HD3 increases by (V DD1 /V DD2 ) 2 HD2 increases by (V DD1 /V DD2 ) 10bi ADC & T/τ = 10 V DD V h = 4V V FS = 1V EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 2
Sampling Disorion SFDR sensiive o sampling disorion - improve lineariy by: Larger VDD Higher sampling bandwidh Soluions: Overdesign Larger swiches Increased swich charge injecion Increased nonlinear S & D juncion cap. Maximize VDD/VFS Decreased dynamic range if VDD cons. Complemenary swich Consan & max. S? f(n ) 10bi ADC T/τ = 20 V DD V h = 2V V FS = 1V EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 3 Pracical Sampling kt/c noise B 2 1 C 12kT B VFS Finie R sw limied bandwidh 1 1 R << 2 fcln 2 1 s 2 B ( ) g sw = f(n ) disorion v IN M1 Vin W g = g 1 for g µ C V V VDD V = h L ( ) ON o o ox DD h v OUT C Swich charge injecion Clock jier EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 4
Complemenary Swich g o g n o g o T =g on + g o p B g o p B Complemenary n & p swich advanages: Increase in he overall conducance Linearize he swich conducance for he range V hp < Vin < Vdd - V hn EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 5 Complemenary Swich Issues Supply Volage Evoluion Supply volage scales down wih echnology scaling Threshold volages do no scale accordingly Ref: A. Abo e al, A 1.5-V, 10-bi, 14.3-MS/s CMOS Pipeline Analog-o-Digial Converer, JSSC May 1999, pp. 599. EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 6
Complemenary Swich Effec of Supply Volage Scaling g o g o n g o T =g o n + g o p g o p B B As supply volage scales down inpu volage range for consan g o shrinks Complemenary swich no effecive when V DD becomes comparable o V h EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 7 Boosed & Consan S Sampling S =cons. OFF ON Gae volage S =low Device off Beware of signal feedhrough due o parasiic capaciors Increase gae overdrive volage as much as possible + keep S consan Swich overdrive volage independen of signal level Error due o finie R ON linear (o 1s order) Lower R on lower ime consan EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 8
Consan S Sampling (= volage @ he swich inpu erminal) EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 9 Consan S Sampling Circui VDD=3V P_N M1 M2 M3 M8 M6 VP1 100ns P C1 PB C2 C3 M12 P M4 M5 M9 VS1 1.5V 1MHz Va Vg M11 Vb Chold Sampling swich & C This Example: All device sizes:10µ/0.35µ All capacior size: 1pF EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 10
VDD=0 3V M1 0ff C1 PB 0 3V Clock Volage Doubler C2 M2 Sauraion mode 0 3V 0 (3V-V h M2 ) 0 0 M1 Triode Acquire charge C1 C2 PB 3V 0 VDD=3V M2 off 3V 0 3V (3V-V h M2 ) (6V-V h M2 ) 0 3V P P VP1 0 3V VP1 3V 0 a) Sar up b) Nex clock phase EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 11 Clock Volage Doubler M1 0ff 3V ~6V VDD=3V C1 PB 0 3V M2 C2 3V 0 M2 Triode (6V-V h M2 ) (3V-V h M2 ) ~ 3V Acquires charge Boh C1 & C2 charged o VDD afer one clock cycle P VP1 0 3V c) Nex clock phase EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 12
Clock Volage Doubler VDD=3V 2VDD M1 M2 P_Boos R1 R2 VDD C1 C2 PB P 0 VP1 Clock period: 100ns *R1 & R2=1GOhm dummy resisors added for simulaion only EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 13 Consan S Sampler: Φ LOW VDD=3V ~ 2 VDD (boosed clock) M3 Triode OFF VDD C3 M4 Sampling swich M11 is OFF VDD M12 Triode Inpu volage source OFF M11 OFF VS1 1.5V 1MHz Chold 1pF Device OFF C3 charged o VDD EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 14
Consan S Sampler: Φ HIGH M8 C3 previously charged o VDD VDD C3 1pF M9 VS1 1.5V 1MHz M11 Chold 1pF M8 & M9 are on: C3 across G-S of M11 M11 on wih consan VGS = VDD EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 15 Consan S Sampling Inpu Swich ae Chold Signal Inpu Signal EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 16
Complee Circui Clock Muliplier M7 & M13 for reliabiliy Remaining issues: -S consan only for n <V ou -Nonlineariy due o Vh dependance of M11on bodysource volage Swich Ref: A. Abo e al, A 1.5-V, 10-bi, 14.3-MS/s CMOS Pipeline Analog-o-Digial Converer, JSSC May 1999, pp. 599. EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 17 Consan Conducance Swich Ref: H. Pan e al., "A 3.3-V 12-b 50-MS/s A/D converer in 0.6um CMOS wih over 80-dB SFDR," IEEE J. Solid-Sae Circuis, pp. 1769-1780, Dec. 2000 EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 18
Consan Conducance Swich OFF Ref: H. Pan e al., "A 3.3-V 12-b 50-MS/s A/D converer in 0.6um CMOS wih over 80-dB SFDR," IEEE J. Solid-Sae Circuis, pp. 1769-1780, Dec. 2000 EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 19 Consan Conducance Swich M2 Consan curren consan g ds ON M1 replica of M2 & same VGS as M2 M1 also consan g ds Ref: H. Pan e al., "A 3.3-V 12-b 50-MS/s A/D converer in 0.6um CMOS wih over 80-dB SFDR," IEEE J. Solid-Sae Circuis, pp. 1769-1780, Dec. 2000 EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 20
Advanced Clock Boosing Technique Ref: M. Walari e al., "A self-calibraed pipeline ADC wih 200MHz IFsampling fronend," ISSCC 2002, Dig. Tech. Papers, pp. 314 Sampling Swich EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 21 Advanced Clock Boosing Technique clk low Sampling Swich clk low Capaciors C1a & C1b charged o VDD MS off Hold mode EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 22
Advanced Clock Boosing Technique clk high Sampling Swich clk high Top plae of C1a & C1b conneced o gae of sampling swich Boom plae of C1a conneced o V IN Boom plae of C1b conneced o V OUT VGS & VGD of MS boh @ VDD & ac signal on n3 average of V IN & V OUT EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 23 Advanced Clock Boosing Technique Ref: M. Walari e al., "A self-calibraed pipeline ADC wih 200MHz IFsampling fronend," ISSCC 2002, Dig. Tech. Papers, pp. 314 Sampling Swich Gae racks average of inpu and oupu, reduces effec of I R drop a high frequencies Bulk also racks signal reduced body effec (echnology used allows connecing bulk o S) Repored measured SFDR = 76.5dB a f in =200MHz EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 24
Swich Off-Mode Feedhrough Cancellaion Ref: M. Walari e al., "A self-calibraed pipeline ADC wih 200MHz IF-sampling fronend," ISSCC 2002, Dig. Techn. Papers, pp. 314 EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 25 Pracical Sampling M1 C V o R sw = f( ) disorion Swich charge injecion EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 26
Sampling Swich Charge Injecion V H +V h M1 V O V L V O DV C s off Firs assume is a DC volage When swich urns off offse volage induced on C s Why? EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 27 Sampling Swich Charge Injecion MOS xor operaing in riode region Cross secion view L D C ov Disribued channel resisance & gae & juncion capaciances G C ov L S D C HOLD C j sb B C j db Channel disribued RC nework Channel o subsrae juncion capaciance disribued & variable Over-lap capaciance C ov = L D xwxc ox associaed wih GS & GD overlap EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 28
Swich Charge Injecion Slow Clock V H +V h V L - off Slow clock clock fall ime >> device speed During he period (- o off ) curren in channel discharges channel charge ino low impedance signal source Only source of error Charge ransfer from C ov ino C s EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 29 Swich Charge Injecion Slow Clock VG V H C ov +V h D ov s C s Cov V = V + V V C + C ( ) i h L V L V O DV Cov V h V L Cs ( ε ) ( ) + V = V 1+ + V o i os - off Cov C where ε = ;V = V V C s ( ) ov os h L Cs EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 30
Swich Charge Injecion Slow Clock- Example 12m/0.35m M1 VO V H +V h C s =1pF ' 2 ov µ ox µ h C = 0.3fF/ C = 5fF/ V = 0.5V V L V O DV Cov 12µ x0.3ff/ µ ε = = =.36% 7 bi C 1pF s Cov Vos = ( Vh VL) = 1.8mV C s - off EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 31 Swich Charge Injecion Fas Clock M1 VO V H +V h C s =1pF V L V O DV Sudden gae volage drop no gae volage o esablish curren in channel channel charge has no choice bu o escape ou owards S & D off EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 32
Swich Charge Injecion Fas Clock Cov 1 Q Vo= ( VH VL) C + C 2 C ov s s Cov 1 WCox( L 2LD )(( VH Vi Vh) ) ( VH VL) C + C 2 C ov s s V = V ( 1+ ε ) + V o i os 1 WCoxL whereε = 2 C s ch V H V L V O +V h DV Cov 1 WCoxLV ( H Vh) Vos = ( VH VL) C 2 C s s Assumpion channel charge divided equally beween S & D Source of error channel charge ransfer + charge ransfer from C ov ino C s off EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 33 Swich Charge Injecion Fas Clock- Example 12m/0.35m M1 VO C s =1pF V H V IN +V h 2 ov µ ox µ h DD C = 0.3fF/ C = 5fF/ V = 0.5VV = 3V WLCox 12µ x0.35x5ff/ µ ε = 1/2 = = 2.1% 4.5 bi C 1pF s Cov 1 WCoxLV ( H Vh) Vos = ( VH VL) = 9mV 26.3mV = 45.3mV C 2 C s s V L V O off DV EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 34
Swich Charge Injecion Example-Summary 2.1% e 45mV V OS.36% Clock fall ime 1.8mV Clock fall ime Error funcion of: Clock fall ime Inpu volage level Source impedance Sampling capaciance Swich size EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 35 How do we reduce he error? Reduce swich size? 1Qch Vo = 2Cs Cs τ = RONCs = W µ Cox ( VGS Vh) L Swich Charge Injecion Error Reducion Consider he figure of meri (FOM): Cs 1 WCoxL( ( VH Vi Vh) ) FOM = τ Vo W µ Cox ( VGS Vh) 2 Cs L 2 L FOM µ Reducing swich size increases τ increased disorion no a viable soluion Small τ and small V use minimum chanel lengh For a given echnology τ x V=cons. EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 36
Sampling Swich Charge Injecion Summary Exra charge injeced ono sampling capacior @ swich device urn-off Charge sharing wih C ov Channel charge ransfer Issues: DC offse Inpu dependan error volage disorion Soluions: Complemenary swich? Addiion of dummy swiches? Boom-plae sampling? EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 37 Swich Charge Injecion Complemenary Swich V H B V L B In slow clock case if area of n & p devices are equal effec of overlap capacior for n & p devices o firs order cancel (maching n & p widh and L) EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 38
Swich Charge Injecion Complemenary Swich Fas Clock ( ) Q = WC L V V V ch n n ox n H i h n ch p p ox p i L ( Vh p) Q = WC L V V V H 1 Q Q Vo 2 Cs Cs ch p ch n V L V = V ( 1+ ε ) + V o i os 1 WC L + WC L ε 2 C n ox n p ox p s In fas clock case Offse cancelled for equal device widh Inpu volage dependan error worse! B EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 39 Swich Charge Injecion Dummy Swich B M1 M2 V O V H B W M2 =1/2W M1 C s V L Dummy swich same L as main swich bu half W Main device clock goes low, dummy device goes high dummy swich acquires same amoun of channel charge main swich needs o lose Effecive only if exacly half of he charge ransferred o M2 and requires good maching beween clock fall/rise EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 40
Swich Charge Injecion Dummy Swich R M1 B M2 W M2 =1/2W M1 VO C s C s To guaranee half of charge goes o each side creae he same environmen on boh sides Add capacior equal o sampling capacior o he oher side of he swich + add fixed resisor o emulae inpu resisance of nex circui Issues: Degrades sampling bandwidh EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 41 Dummy Swich Effeciveness Tes Dummy swich W=1/2W main Noe large Ls good device area maching Ref: L. A. BIENSTMAN e al, An Eigh-Channel 8 13i Microprocessor Compaible NMOS D/A Converer wih Programmable Scaling, IEEE JSSC, VOL. SC-15, NO. 6, DECEMBER 1980 EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 42
Swich Charge Injecion Boom Plae Sampling b M1A V O+ + Cs a V H V L b M2A V O- - M1B Cs a M2B Swiches M2A@ B are opened slighly earlier compared o M1A&B Injeced charge by he opening of M2AB is consan & eliminaed when used differenially Since boom plae of C s is open when M1A&B are opened no charge injeced on C s EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 43 Flip-Around Track & Hold S2A D D D C S3 v IN S1A S2 v OUT S1 Concep based on boomplae sampling v CM EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 44
Flip-Around T/H S2A D D D C S3 v IN S1A S2 v OUT S1 v CM Concep based on boom-plae sampling EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 45 Flip-Around T/H S2A D D D C S3 Charging C v IN S1A S2 v OUT S1 v CM EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 46
Flip-Around T/H S2A D D D C S3 Holding v IN S1A S2 v OUT S1 v CM EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 47 Flip-Around T/H - Timing S2A D D D C S3 Sampling v IN S1A S2 v OUT S1 S1 opens earlier han S1A "Boom Plae Sampling" v CM EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 48
Charge Injecion A he insan of sampling, some of he charge sored in sampling swich S1 is dumped ono C Wih "Boom Plae Sampling", charge injecion comes only from S1 and is o firs-order independen of v IN Only a dc offse is added o he inpu signal This dc offse can be removed wih a differenial archiecure EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 49 Flip-Around T/H Consan swich S o minimize disorion S2A D D D C S3 v IN S1A S2 v OUT S1 v CM EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 50
Small Nch-only Flip-Around T/H S2A D D D C S3 v IN S1A S2 v OUT S1 v CM EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 51 Flip-Around T/H S1 is an n-channel MOSFET Since i always swiches he same volage, i s onresisance, R S1, is signal-independen (o firs order) Choosing R S1 >> R S1A minimizes he non-linear componen of R = R S1A + R S1 S1A is a wide (much lower resisance han S1) consan S swich In pracice size of S1A is limied by he (nonlinear) S/D capaciance ha also adds disorion If S1A s resisance is negligible delay depends only on S1 resisance S1 resisance is independen of v IN delay is independen of v IN EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 52
Differenial Flip-Around T/H S11 S12 Offse volage associaed wih charge injecion of S11 & S12 cancelled by differenial naure of he circui Ref: W. Yang, e al. A 3-V 340-mW 14-b 75-Msample/s CMOS ADC Wih 85-dB SFDR a Nyquis Inpu, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001 1931 EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 53 Differenial Flip-Around T/H Gain=1 f2 Feedback facor=1 n-cm =V ou_com -V sig_com Amplifier needs o have large inpu common-mode compliance EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 54
Differenial Flip-Around T/H Choice of Sampling Swich Size THD simulaed w/o sampling swich boosed clock -45dB THD simulaed wih sampling swich boosed clock (see figure) Ref: K. Vleugels e al, A 2.5-V Sigma Dela Modulaor for Broadband Communicaions Applicaions IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001, pp. 1887 EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 55 Inpu Common-Mode Cancellaion Ref: R. Yen, e al. A MOS Swiched-Capacior Insrumenaion Amplifier, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-17, NO. 6,, DECEMBER 1982 1008 EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 56
Inpu Common-Mode Cancellaion Track mode (φ high) V C1 =V I1, V C2 =V I2 V o1 =V o2 =0 Hold mode (φ low) V o1 +V o2 =0 V o1 -V o2 = -(V I1 -V I2 )(C 1 /(C 1 +C 3 )) Inpu common-mode level removed EECS 247 Lecure 18: Daa Converers 2005 H.K. Page 57