Chapter 7. Sequential Circuits Registers, Counters, RAM

Chapter 7. Sequential Circuits Registers, Counters, RAM

Register - a group of binary storage elements suitable for holding binary info A group of FFs constitutes a register Commonly used as temporary storage in a processor They are faster and more convenient than main memory. More registers can help speed up complex calculations. A basic register Just put a bunch of flip-flops together Uses D FFs (ex) 4-bit register 2

Shift register a register capable of shifting its binary info by one bit position (ex) 4-bit shift register Q (t+) = SI, Q (t+) = Q (t) Q 2 (t+) = Q (t), Q 3 (t+) = Q 2 (t) Q Q Q 2 Q 3 (ex) 4-bit circular shift register with J-K FFs 3

Serial transfer from Reg A to Reg B 4

Reg A Reg B SO of B initial after T after T 2 after T 3 after T 4 Bidirectional shift register with parallel load (aka, universal shift register 7494) Mode control Reg operation S S No change Shift right Shift left Parallel load Serial transfer For parallel transfer of n- input lines 5

SI for Shift-left 6

Counters A register that goes through a predetermined sequence of states upon the application of clock pulses Gates are connected to produce the prescribed sequence of states A special type of register Types Ripple counter (asynchronous counter) FF output transition serves as a source for triggering other FFs Ex: Binary ripple counter, BCD ripple counter Synchronous counter FFs are synchronized by the common CK so that FF outputs change simultaneously 7

(ex) 4-bit binary ripple counter 8

(ex) 4-bit BCD ripple counter 9

(ex) 3-decade BCD counter CP CP

Synchronous counter types Binary counter BCD counter Ring counter only one FF output is set at any particular time (ex) 4 distinguishable states Johnson counter - starting from, each shift operation inserts s from the left until, and then s are inserted from the left until (ex) 8 distinguishable states

Counter Design procedure The same as finite state machine design procedure to be covered next chapter Draw state transition diagram 2 Derive state transition table 3 Using excitation table of the chosen FF, express FF inputs 4 Find input equations (ex) 3-bit binary up-counter state (transition) diagram 2

23 state transition table with T-FF inputs present state next state FF inputs Excitation table of T-FF Q Q + T 3

4 input equations A BC A BC T A = BC T B = C T C = 4

Counter design with different kinds of FFs (ex) ) T-FF 5

A BC X A BC X A BC X X x X X X X T A = A B + AB T B = AB + A C T C = A + B 6

2) R-S FF or 3) J-K FF excitation table Q Q + S R J K X X X X X X ABC A + B + C + S A R A S B R B S C R C J A K A J B K B J C K C X X X X X --- X X X X X X X X X X X X X X X X X X X X X X X X X --- X X X X X X X X X X X X --- X X X X X X X X X X X X X X X X 7

Using KMs, S A = B R A = C, J A = B K A = C S B = A R B = A C, J B = A K B = A C S C = AC + BC R C = C, J C = A+B K C = 8

4) D-FF D = Q + D A = A + D B = B + D C = C + A BC X A BC X A BC X X x X X X X D A = B D B = A+BC D C = AB +BC Self-starting At power-up, counter s starting state may not be in proper counter sequence (ex) 9

Should design counter so that even invalid states eventually transition to valid state self-starting ABC A + B + C + 2

Random access memory Sequential circuits depend upon the presence of memory. A flip-flop can store one bit of information. A register can store a single word, typically 32-64 bits. Random access memory (RAM) allows us to store even larger amounts of data. RAM provides large quantities of temporary storage in a computer system. Remember the basic capabilities of a memory: It should be able to store a value. You should be able to read the value that was saved. You should be able to change the stored value Read/write memory (RWM) Most RAMs lose their memory when power is removed volatile memory 2

Block diagram of RAM CS (Chip Select), enables or disables the RAM. ADRS specifies the address or location to read from or write to. WR selects between reading () from or writing () to the memory. OUT is the n-bit value stored at ADRS. DATA is the n-bit value to save in memory. 22

2 k x n RAM. There are k address lines, which specifies one of 2 k addresses. Each address contains an n-bit word. Ex: 2 24 x 6 RAM contains 2 24 = 6M words, each 6 bits long. need 24 address lines. The total storage capacity is 2 24 x 6 = 2 28 bits. Memory sizes are usually specified in numbers of bytes (8 bits). 2 28 -bit memory = 2 28 bits/8 bits per byte = 2 25 bytes = 32MB RAM size is measured in base 2 units, while hard drive size is measured in base units 23

Reading RAM Enable the chip by ensuring CS =. Select the read operation, by setting WR =. Send the desired address to the ADRS input. The contents of that address appear on OUT after a little while. Notice that the DATA input is unused for reading Writing RAM Enable the chip by setting CS =. Select the write operation, by setting WR =. Send the desired address to the ADRS input. Send the word to store to the DATA input. The output OUT is not needed for writing k n 2 k x n memory ADRS DATA CS WR OUT n 24

RAM Types Static RAM (SRAM) : once a word is written at a location, it remains stored as long as power is applied Dynamic RAM (DRAM) : stored data must be refreshed periodically by reading it and then writing it back again, or else it disappears -bit Static RAM cell Static memory is modeled using one latch for each bit of storage. 25

Why use latches instead of flip flops? A latch can be made with only two NAND or two NOR gates, but a flip-flop requires at least twice that much hardware. In general, smaller is faster, cheaper, and requires less power. Writing to the RAM cell: When CS = and WR =, the latch control input (C) will be The DATA input is thus saved in the D latch. Reading from the RAM cell and maintaining the current contents: When CS = or when WR =, the latch control input (C) will be, so the latch just maintains its present state. The current latch contents will appear on OUT when CS becomes. 26

4 X 4 RAM 27

We can use small RAMs as building blocks for making larger memories, Ex: put four 64K x 8 chips together to make a 256K x 8 memory. For 256K words, we need 8 address lines. The two most significant address lines go to the decoder, which selects one of the four 64K x 8 RAM chips. The other 6 address lines are shared by the 64K x 8 chips 28

We can also combine smaller chips to make wider memories, with the same number of addresses but more bits per word. Ex: 64K x 6 RAM, created from two 64K x 8 chips. left chip contains the most significant 8 bits of the data. right chip contains the lower 8 bits of the data. 29

Dynamic RAM A cell consists of a single Tr. and a capacitor Info is stored in the capacitor stored charge on the capacitor represents a logical. No charge represents a logic. Capacitors lose their charge after a few milliseconds. Requires constant refreshing to recharge the capacitors. (That s what s dynamic about it.) Dynamic RAMs tend to be physically smaller than static RAMs. A single bit of data can be stored with just one capacitor and one transistor, while static RAM cells typically require 4-6 transistors. This means dynamic RAM is cheaper and denser more bits can be stored in the same physical area. 3

bit DRAM cell Writing word line - H bit line H (), L () Reading word line - H bit line voltage between H and L bit line pulled slightly higher (if ) or slightly lower (if ) sense amplifier detects the small change and recovers a or accordingly read operation discharges the capacitor across the bit line external circuits buffer the value and then write back after reading 3

Capacitor contents decay over time DRAM must be refreshed (ie, update memory cell periodically) 32