ECE 341 Lecture # 3 Instructor: Zeshan Chishti zeshan@ece.pdx.edu October 7, 2013 Portland State University
Lecture Topics Counters Finite State Machines Decoders Multiplexers Reference: Appendix A of the textbook, sections A.8 to A.13.
Announcements Next class (Wednesday, Oct. 9) will start at 5:30PM Homework 1 due next class
Counters Counters are arithmetic circuits used for the purpose of counting Can increment or decrement by 1 each cycle Counters often implemented with T flip-flops Toggle feature naturally suited for counting operation Applications of counters Count occurrences of certain events, for example, no. of add instructions Track elapsed time between events Generate control and timing signals, for example, to produce signals whose frequencies are multiples of original clock frequency
A 3-bit Up-counter Consider a 3-bit counter x 2 x 1 x 0 shown in table. The least significant bit x 0 toggles at every increment of counter x 1 toggles on 1->0 transitions of x 0 (half the rate of toggling of x 0 ) x 2 toggles on 1->0 transitions of x 1 (half the rate of toggling of x 1 ) Counter Value x 2 x 1 x 0 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1
A 3-bit Up-counter
Practice Exercise Design a 3-bit down counter with T flip-flops. How does the down counter circuit differ from the up-counter circuit?
A 3-bit Down-counter The least significant bit x 0 toggles at every decrement of counter x 1 toggles on 0->1 transitions of x 0 x 2 toggles on 0->1 transitions of x 1 Counter Value x 2 x 1 x 0 7 1 1 1 6 1 1 0 5 1 0 1 4 1 0 0 3 0 1 1 2 0 1 0 1 0 0 1 0 0 0 0
Practice Exercise Solution Design a 3-bit down counter with T flip-flops. How does the down counter circuit differ from the upcounter circuit? Solution: Two ways to convert the previous up-counter to a down-counter: 1. Either, replace the +ve edge-triggered T flip-flops with ve edgetriggered T flip-flops 2. Or, connect the Q outputs (instead of NOT(Q) outputs) from previous flip-flops to clock inputs of next flip-flops
Asynchronous Counters The previous counter is an example of asynchronous counters. Also called ripple counters Input clock only connected to one flip flop Clocks for other flip-flops are derived from outputs of previous flip-flops Asynchronous counters are slow because of cascaded clocking The input clock pulse ripples from stage to stage Propagation delay of individual flip-flops limit speed of operation Solution: Synchronous sequential circuits (finite state machines)
Finite State Machines Recall that in a sequential circuit: Outputs depend both on present inputs and the sequence of previous inputs The state of a sequential circuit determines its behavior when various input patterns are applied A finite state machine model formally describes a sequential circuit Inputs Combinational Logic Outputs Present State Next State Delay Elements (Flip-flops)
Synthesis of Finite State Machines Synthesis of FSM involves the following steps: Step 1: Develop a state diagram or state table Depict how state transitions occur in response to input patterns Step 2: Determine # and types of needed flip flops Step 3: Determine state assignment (flip-flop values for each state) Step 4: Determine the state-assigned state table Step 5: Derive the logic expressions for next-state logic and outputs Step 6: Use the derived expressions to implement the circuit
Example: Up/Down Counter with D flip-flops Problem Statement: Design a mod-4 counter which counts up or down depending on an input and has an output of 1 if the count is equal to 2 States: 4 states (S0, S1, S2 and S3) corresponding to 4 count values Input: Variable x. Count up if x=0, down if x=1 Output: Variable z. If present state is S2, then z=1, otherwise z=0;
State Diagram x=0 S0/0 S1/0 x=1 x=0 x=1 x=1 x=0 x=1 S3/0 S2/1 x=0
State Table Present State Next State Output z x = 0 x = 1 S0 S1 S3 0 S1 S2 S0 0 S2 S3 S1 1 S3 S0 S2 0 Need 2 state variables to represent 4 states => use 2 D flip-flops
State-Assigned State Table State variables y 1 and y 2 used to express each state as a 2-bit number y 2 y 1 We choose the following state assignment S0=00, S1=01, S2=10, S3=11 Present State Next State Output z x = 0 x = 1 y 2 y 1 Y 2 Y 1 Y 2 Y 1 00 01 11 0 01 10 00 0 10 11 01 1 11 00 10 0 Logic Expressions Next state Output Y2 y2 y1 x z y2y1 Y1 y1
Logic Circuit Logic Expressions Next state Output Y2 y2 y1 x z y2y1 Y1 y1
Decoder Decoder is used to decode encoded information A decoder has n data inputs and 2 n outputs For any input data combination, a unique output line has logic value 1 and all the other outputs have the value 0 (one-hot encoding) Example: Consider an instruction which performs 8 different functions. A 3-bit field may be used to denote 1 out of the 8 possible functions. A 3- to-8 decoder would decode any instance of the instruction to determine the desired function n inputs n-to-2 n decoder 2 n outputs
2-to-4 Decoder Circuit x 0 y 3 y 2 x 0 x 1 Active Output 0 0 y 0 0 1 y 1 1 0 y 2 1 0 y 3 x 1 y 1 y 0 x y 0 0 y x 1 1 y 2 y 3
BCD to Seven-Segment Display Decoder In typical decoders, only one output line asserted for an input combination There are other special decoders, where multiple lines may be asserted Example: BCD (binary-coded decimal) to seven-segment display decoder Input: a 4-bit BCD digit Output: 7 bits (a through g) corresponding to 7 display segments Any number from 0 to 9 can be displayed by turning some lights on and others off Multiple outputs may be asserted at once E.g., if input is 0100 (digit 4): b, c, f and g are on See Figure A.36 in book for truth table and circuit a f g b e d c
Multiplexer A multiplexer (MUX) circuit has: 2 k data inputs k select inputs One output A MUX passes the signal value on one of its data inputs to the output based on the value of the select signals Can be used for gating of data that may come from many different sources Multiplexer Symbol 2 k data inputs MUX Output k select inputs
A 4-Input Multiplexer x 0 x 1 x 2 x 3 4-input MUX z w 0 w 1 z 0 0 x 0 0 1 x 1 1 0 x 2 1 1 x 3 w 0 w 1 z x0w0w1 x1w 0w1 x2w0w1 x3w0w1 Logic circuit implementation shown in Figure A.37 Example usage: A register can be loaded from one of four distinct sources by using a 4-input MUX
Logic Functions using MUXes MUXes can be used to synthesize logic functions Example: Consider a function f of 3 input variables x 0, x 1 and x 2 defined by following truth table. This function can be synthesized with a 4-input mux x 0 x 1 x 2 f 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 1 x 0 x 1 f 0 0 0 0 1 X 2 1 0 1 1 1 NOT(x 2 ) 1 1 0 1 1 1 1 0
Logic Functions using MUXes MUXes can be used to synthesize logic functions Example: Consider a function f of 3 input variables x 0, x 1 and x 2. This function can be synthesized with a 4-input mux x 0 x 1 x 2 f 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 0 x 2 1 NOT(x 2 ) MUX f 1 0 1 1 1 1 0 1 x 0 x 1 1 1 1 0
Practice Problem Synthesize the function f 1 in the following truth table by using a 4-input mux with y 1 and y 2 as selector inputs. y 0 y 1 y 2 f 1 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1
Solution Transform the truth table to use y1 and y2 as inputs y 0 y 1 y 2 f 1 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 y 1 y 2 f 1 0 0 0 0 1 1 1 0 NOT(y 0 ) 1 1 1 1 1 0 0 1 1 1 1
Solution 4-input MUX with y 1 and y 2 as selector inputs y 0 y 1 y 2 f 1 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 0 0 1 NOT(y 0 ) 1 MUX f 1 1 0 1 1 1 1 0 0 y 1 y 2 1 1 1 1