L4: Sequential Building Blocks (Flip-flops, Latches and Registers) Acknowledgements:., Materials in this lecture are courtesy of the following people and used with permission. - Randy H. Katz (University of California, Berkeley, epartment of Electrical Engineering & Computer Science) - Gaetano Borriello (University of Washington, epartment of Computer Science & Engineering, http://www.cs.washington.edu/370) - Rabaey, A. Chandrakasan, B. Nikolic. igital Integrated Circuits: A esign Perspective. Prentice Hall, 2003. L4: 6.111 Spring 2004 Introductory igital Systems Laboratory 1
Combinational Logic Review in 0 in 1 in N-1 Combinational Circuit in 0 in 1 in M-1 Combinational logic circuits are memoryless No feedback in combinational logic circuits Output assumes the function implemented by the logic network, assuming that the switching transients have settled Outputs can have multiple logical transitions before settling to the correct value L4: 6.111 Spring 2004 Introductory igital Systems Laboratory 2
A Sequential System Sequential circuits have memory (i.e., remember the past) The current state is held in memory and the next state is computed based the current state and the current inputs In a synchronous systems, the clock signal orchestrates the sequence of events L4: 6.111 Spring 2004 Introductory igital Systems Laboratory 3
A Simple Example Adding N inputs (N-1 Adders) in 0 in 1 in2 in N-1 Using a sequential (serial) approach reset in Current_Sum clk L4: 6.111 Spring 2004 Introductory igital Systems Laboratory 4
Implementing State: Bi-stability V o1 =V i2 V o2 =V i1 V i2 = V o1 Point C is Metastable C V o1 V i2 1 G V i1 = V o2 V i2 =V o1 V i1 A V o2 V i2 = V o A Points A and B are stable (represent 0 & 1) C B V i1 =V o2 G B V i1 = V o2 L4: 6.111 Spring 2004 Introductory igital Systems Laboratory 5
NOR-based Set-Reset (SR) Flipflop S S R S R 0 0 1 0 1 0 0 1 0 1 1 1 0 0 SR = 00, 01 SR = 00, 10 SR = 1 0 0 1 1 0 SR = 0 1 SR = 0 1 SR = 1 0 SR = 11 SR = 1 1 SR = 1 1 R Forbidden State SR = 0 0 0 0 SR = 0 0 Reset Hold Set Reset Set R S?? Flip-flop refers to a bi-stable element (edge-triggered registers are also called flip-flops) this circuit is not clocked and outputs change asynchronously with the inputs L4: 6.111 Spring 2004 Introductory igital Systems Laboratory 6
Making a Clocked Memory Element: Positive -Latch S CLK R hold sample hold sample hold R and S G clk clock A Positive -Latch: Passes input to output when CLK is high and holds state when clock is low (i.e., ignores input ) A Latch is level-sensitive: invert clock for a negative latch L4: 6.111 Spring 2004 Introductory igital Systems Laboratory 7
Multiplexor Based Positive & Negative Latch 2:1 multiplexor Positive Latch Negative Latch in 0 0 out in 1 1 0 1 1 0 SEL Out = sel * in 1 + sel * in 0 CLK CLK "data" clk "load" clk "remember" "stored value" L4: 6.111 Spring 2004 Introductory igital Systems Laboratory 8
Building an Edge-Triggered Register Negative latch Positive latch M G G Master-Slave Register Use negative clock phase to latch inputs into first latch Use positive clock to change outputs with second latch View pair as one basic unit master-slave flip-flop twice as much logic L4: 6.111 Spring 2004 Introductory igital Systems Laboratory 10
Latches vs. Edge-Triggered Register Edge triggered device sample inputs on the event edge 7474 Transparent latches sample inputs as long as the clock is asserted Positive edge-triggered register Timing iagram: 7475 C Level-sensitive latch Bubble here for negative edge triggered register 7474 7475 Behavior the same unless input changes while the clock is high L4: 6.111 Spring 2004 Introductory igital Systems Laboratory 11
Important Timing Parameters Clock Input T su T h There is is a timing "window" around the clocking event during which the input must remain stable and unchanged in in order to to be be recognized g Clock: Periodic Event, causes state of memory element to change memory element can be updated on the: rising edge, falling edge, high level, low level Setup Time (T su ) Minimum time before the clocking event by which the input must be stable Hold Time (T h ) Minimum time after the clocking event during which the input must remain stable Propagation elay (T cq for an edge-triggered register and T dq for a latch) elay overhead of the memory element L4: 6.111 Spring 2004 Introductory igital Systems Laboratory 12
The J-K J K Flip-Flop Flop J K S R 100 J K + + 0 0 0 1 0 1 1 0 1 0 J K 1 1 \ Eliminate the forbidden state of the SR Flip-flop Use output feedback to guarantee that R and S are never both one L4: 6.111 Spring 2004 Introductory igital Systems Laboratory 14
J-K K Master-Slave Register Sample inputs while clock high Sample inputs while clock low J S P S K R P R CLK 1's Set Reset Catch Toggle 100 J K Correct Toggle Operation J I K P \ P \ Master outputs Slave outputs Is there a problem with this circuit? L4: 6.111 Spring 2004 Introductory igital Systems Laboratory 15
Pulse Based Edge-Triggered J-K J K Register Input X I Output Schematic I Input X Output t plh J I K S R J I K JK Register Logic Symbol JK Register Schematic L4: 6.111 Spring 2004 Introductory igital Systems Laboratory 16
Flip-Flop Flop vs. Toggle Flip-Flop Flop Flip-Flop 0 N 0 0 1 1 0 1 0 1 1 T T T (Toggle) Flip-Flop 0 N 1 0 1 0 0 N-1 1 N-1 1 L4: 6.111 Spring 2004 Introductory igital Systems Laboratory 17
Realizing different types of memory elements Characteristic Equations : + = E.g., J=K=0, then + = J-K: + = J + K J=1, K=0, then + = 1 J=0, K=1, then + = 0 T: + = T + T J=1, K=1, then + = Implementing One FF in Terms of Another J C K K J C implemented with J-K J-K implemented with L4: 6.111 Spring 2004 Introductory igital Systems Laboratory 18
esign Procedure Excitation Tables: What are the necessary inputs to cause a particular kind of change in state? Implementing FF with a J-K FF: + J K T 0 0 0 X 0 0 0 1 1 X 1 1 1 0 X 1 1 0 1 1 X 0 0 1 1) Start with K-map of + = ƒ(, ) 0 0 1 0 1 2) Create K-maps for J and K with same inputs (, ) 1 0 1 3) Fill in K-maps with appropriate values for J and K + = to cause the same state changes as in the original K-map E.g., = = 0, + = 0 then J = 0, K = X 0 1 0 1 0 0 1 0 X X 1 X X 1 1 0 J = K= L4: 6.111 Spring 2004 Introductory igital Systems Laboratory 19
esign Procedure (cont.) Implementing J-K FF with a FF: 1) K-Map of + = F(J, K, ) 2,3) Revised K-map using 's excitation table its the same! that is why design procedure with FF is simple! JK J 00 01 11 10 0 0 0 1 1 1 1 0 0 1 K + = = J + K Resulting equation is the combinational logic input to to cause same behavior as J-K FF. Of course it is identical to the characteristic equation for a J-K FF. L4: 6.111 Spring 2004 Introductory igital Systems Laboratory 20
System Timing Parameters In Combinational Logic Register Timing Parameters T cq : worst case rising edge clock to q delay T cq, cd : contamination or minimum delay from clock to q T su : setup time T h : hold time Logic Timing Parameters T logic : worst case delay through the combinational logic network T logic,cd : contamination or minimum delay through logic network L4: 6.111 Spring 2004 Introductory igital Systems Laboratory 21
elay in igital Circuits V V R on V out V out C L R on C L (a) Low-to-high (b) High-to-low R v out review v in C t p = ln (2) W = 0.69 RC L4: 6.111 Spring 2004 Introductory igital Systems Laboratory 22
System Timing (I): Minimum Period CLout In Combinational Logic CLK T h T h IN T su T cq T su T cq FF1 T cq,cd T logic T cq,cd CLout T l,cd T su2 T > T cq + T logic + T su L4: 6.111 Spring 2004 Introductory igital Systems Laboratory 23
System Timing (II): Minimum elay CLout In Combinational Logic CLK IN FF1 CLout T su T h T cq,cd T h T l,cd T cq,cd + T logic,cd > T hold L4: 6.111 Spring 2004 Introductory igital Systems Laboratory 24
Shift-Register Typical parameters for Positive edge-triggered Register Tsu 20ns Th 5ns Tsu 20ns Th 5ns CLK Tw 25ns Tplh 25ns 13ns Tphl 40ns 25ns all measurements are made from the clocking event that is, the rising edge of the clock Shift-register IN 0 1 OUT IN 100 0 1 CLK CLK L4: 6.111 Spring 2004 Introductory igital Systems Laboratory 25
Clocks are not perfect: Clock Skew CLout In Combinational Logic Wire delay CLK CLK į>0 T > T + T + T - į cq logic su T cq,cd + T logic,cd > T hold + į L4: 6.111 Spring 2004 Introductory igital Systems Laboratory 26