Flip Chip Reliability

Flip Chip Reliability P e t e r B o r g e s e n, P h. D., S u r face Mount Laboratory, Corporation, Binghamton, New York 13902-0825 Daniel Blass, Sur f a c e M o u n t L a b o r a t o r y, U n i v e r s a l I n s t r u m e n t s C o r p o r a t i o n, Binghamton, New York 13902-0825 K. Srihari, Ph.D., Professor, Department of Systems Science and Industrial Engineering, T.J. Watson School of Engineering and Applied Science, State University of New York, Binghamton, New York 13902 Abstract The attachment of flip chip onto organic substrates, whether in component manufacturing or as part of integrated SMT assemblies, offers a series of widely publicized advantages. It does, however, also offer a variety of challenges, including a number of unique reliability issues. Flip chip reliability has been found to depend on a great many factors, including underfill material and process, moisture, flux, solder mask and solder mask opening design, chip passivation, chip and substrate thickness, gap between chip and substrate, and solder joint layout. At a first glance, the consequences may seem quite confusing. Accelerated test results may, however, invariably be rationalized on the basis of a comprehensive failure analysis and modeling. The consequences for materials selection and process windows are often profound. The present paper draws a comprehensive picture of flip chip reliability, with particular emphasis on the effects of thermal excursions on assembly damage and failure, based on modeling and failure analysis of a large variety of assemblies. Observed trends are found to be in excellent agreement with predictions. Consequences of the competing multitude of potential failure mechanisms are discussed. 1

Introduction Flip chip attachment is potentially attractive for a large variety of microelectronics packaging applications. The technology is, however, not without it s challenges. Although the required placement accuracy is often underestimated because the effects of substrate tolerances on assembly yields are ignored 1, the overall equipment needs are in principle quite readily defined 2. The same cannot be said for the materials, design, and process requirements 3. The issues are here completely dominated by the question of reliability and the need to underfill the assemblies. Decisions on details ranging from chip layout, passivation, backlapping, dicing parameters, substrate technology and design, to materials selection, fluxing, handling, cost, and of course the whole underfill process are all affected by this. To the best of our knowledge, no one has yet convincingly extrapolated accelerated test results to predict the life of an underfilled flip chip assembly in service. In fact, many have (or should have) serious concerns as to the validity of various accelerated tests for the mere ranking of, for example, alternative materials combinations. Certainly, it is almost inevitable that the acceleration factors will differ from those that apply to other parts of an integrated assembly, such as BGAs or QFPs, in the same tests. It would thus be perfectly possible for the flip chip part of such an assembly to suggest superior performance in a standard test while failing much faster than the rest in actual service. The consequences of all this are tremendous. It is, for example, often not clear whether further reliability improvements are in fact needed or requirements can be relaxed to accommodate alternative (cheaper?) materials and processes. This may be seriously limiting the implementation of flip chip technology for a variety of actually feasible applications. Modeling, testing and failure analysis of tens of thousands of flip chip assemblies have now finally helped establish a fundamental understanding of the various damage mechanisms contributing to flip chip solder joint failure due to aging, moisture exposure and thermal excursions. Careful accounting for their individual sensitivities to different parameters allows not only the rationalization of test results but, importantly, the generalization to other cases as well. Notably, it provides the understanding required for the proper optimization of the reliability of individual products. As discussed elsewhere 4 the whole picture also forms the basis for an ongoing program to assess life in service. An underfilled flip chip assembly effectively constitutes an integrated multilayer system with the critical connections (joints and vias) firmly embedded in one of the layers. As such, it is not surprising that the assembly reliability is sensitive to a very large number of mechanical and chemical parameters. Before, during and after cure the underfill will react with, dissolve, or allow the diffusion of, moisture and numerous other chemicals from chip passivation, flux residue, solder mask, laminate, contact pads, etc. The resulting modifications of the local underfill properties may often be quite substantial. This may be more or less critical for the ultimate reliability of the joints depending on the detailed stress distributions, and thus on the assembly parameters and the loading mode (mechanical, thermal, environmental). Figure 1 Although complex and by no means fully understood or controllable the local properties of the matrix enveloping the vias tend to be less sensitive to some of the assembly process parameters. Also, there are some obvious differences between the responses of, say, copper vias and solder joints to the same types of loading. Still, the fundamentals remain the same and there is no reason why the issues of via damage and failure could not be integrated into the same overall model. This is undoubtedly also true for chip (silicon) cracking. Similarly, our picture is relatively readily extendable to alternative technologies such as those involving conductive adhesives. The present paper, however, will concentrate on the reliability of the solder joints in underfilled flip chip assemblies. Furthermore, the 2

emphasis will be on a tutorial presentation and illustration of the complete picture, rather than on the documentation of individual theoretical or experimental results. We shall only briefly allude to the multitude of experimental observations that support the specifics of the picture. Normal Stress 4 2 0-2 o 0.018 FR-4 ------- 0.062 FR-4 Thermal Mismatch Induced Stresses Usually, the primary reason for underfilling a flip chip assembly is the thermal mismatch between chip and substrate. However, the optimum materials choice and configuration depend on the relative importance of this, various types of mechanical loads, and the cost/process issues involved. In the following we shall consider first the various thermal mismatch induced stresses in a typical assembly. Figure 1 shows a sketch of a typical flip chip assembly on an FR-4 substrate. The figure is clearly not to scale, the thickness of the underfill and the dimensions of the solder joints being greatly exaggerated. Even if the substrate is not completely flat during the underfill cure, as implied in the figure, shrinking during the subsequent cool-down usually leads to assembly warpage to a radius of curvature of 30-50" for typical chip and substrate thicknesses. This is accompanied by the establishment of complex stress distributions within the solder joints, within the underfill, and along the various interfaces. The wetting of the underfill to the vertical edges of the chip and the resulting establishment of edge fillets are particular critical to the assembly reliability. Without the fillets the overall system would be mechanically similar to a conventional die bonded assembly. Figure 2 shows the normal stress across the interface between the underfill and the chip passivation for a flip chip assembly without edge fillets on two different FR-4 substrate thicknesses. Actually depicted is a Normal Stress 4 2 0-2 -4 Figure 2 o 0.018 FR-4 ------- 0.062 FR-4 0 40 80 125 Distance to Chip Center (mil) -4 0 40 80 125 Distance to Chip Center (mil) Figure 3 2-D FEM calculation of the normal stress as a function of distance from the chip center axis for a 25 mil thick ¼" chip on 18 ( thin ) and 62 mil ( thick ) FR-4 substrates after cool down from cure. In this case the presence of the solder joints was ignored and the stresses would increase during cooling, decrease during subsequent re-heating. The normal (bending) stress clearly depends on the rigidities of both chip and substrate but invariably reaches a singularity in tension at the chip edge. This would be expected to cause relatively rapid in-plane chip cracking or underfill delamination from there 5. In the presence of an edge fillet (Figure 3), shrinkage of the underfill around the bottom of the chip edge exerts a compressive stress on both vertical and horizontal chip surfaces nearby. If the fillet is strong (thick) enough this may more than compensate for the bending stress, leading to an overall compression across the interface between the underfill and the chip passivation near the edge. This benefit does, however, not come for free. Embedding the sharp bottom edge of the silicon chip in the underfill, as opposed to leaving it as part of an open surface as in Figure 2, invariably leads to a singularity in the calculated shear stress distribution. Figure 4 shows both the normal stress and the shear stress distributions along the interface between the underfill and the chip passivation in the presence of a relatively thick edge fillet. We note, for later purposes, that the figure includes also the distributions through a 5 mil diameter solder joint centered 10 mil from the chip edge. As expected, the presence of the joint only affects the overall stress distributions quite nearby. More importantly, for now, is the expected singularity in the shear stress distribution at the chip edge (125 mil from the center). Whether or not the compression is sufficient to suppress the 3

factor would increase with 6 decreasing temperature and be proportional to the thermal mismatch and the square root of the film thickness, h. In the present case the much more complicated geometry actually leads to a preference for cracking to start from the thinnest part at the top of the vertical chip edge. However, the driving force still increases with fillet thickness. initiation of shear driven delamination depends, among other, on the adhesive strength as well as on the thicknesses of chip, substrate and edge fillet. The edge fillet is also subject to stress concentrations at both ends (Figure 5), leading to driving forces for delamination of the underfill from the solder mask surface or the vertical chip edge starting at the point of contact. In general, the tensile stresses here increase with the thermal mismatch (underfill CTE), contact angle and, of course, with decreasing temperature. The compressive stresses exerted by the underfill on both vertical and horizontal chip surfaces must, of course, also be accompanied by a tensile stress along a plane extending from the bottom of the vertical edge at a downward angle on the order of (but not equal to) 45 (Figure 6). There is thus a driving force for the underfill to crack in this direction as well. So far, we have only considered the assembly in a two dimensional cross section. Switching now to a view of the chip from the top (or back side) instead the edge fillet looks simply like a thin film on a bulk substrate, the varying thickness of the film not evident in this view (Figure 7). Cool down also leads to a tensile fillet stress in the plane of this figure, i.e. there is clearly a driving force for cracking of the fillet perpendicular to the vertical chip edge. For a film of constant thickness the corresponding stress intensity Figure 5 Figure 4 q 0 r r q s Damage and Failure Mechanisms Damage of an underfilled flip chip assembly can be conveniently divided into two distinct categories. The first involves essentially instantaneous failure due to an excessive mechanical load, either mechanical shock (drop) or handling (bending, torque, twist,...). This is quite readily tested for and in principle preventable by the establishment of corresponding specs. The other category is more complex, involving the wearout and failure due to repeated loading. In the following, we shall specifically not consider vibration. This phenomenon is not a problem in most applications, but it is inherently extremely assembly specific. A number of phenomena may severely affect the resistance of the assembly to subsequent loading in service. Mechanical shock or handling may damage the underfill. Aging and moisture may cause serious deterioration of its materials properties. Bridging may occur by the extrusion of solder into voids in the cured Figure 6 underfill during even rather mild thermal excursions. In the absence of bridging, solder extrusion has still been shown to weaken the solder joints significantly. Solder extrusion is, of course, sensitive to the specific size and location of the underfill voids, as well as to the local underfill properties and the stress-temperature history. In the absence of bridging, however, weakening and pre-damage by any of the above mechanisms is primarily of concern in as far as it may 4

Silicon Figure 7 allow much faster failure during subsequent thermal excursions (cycling). While not the only concern, underfill delamination usually plays a major role in the electrical failure of the solder joints. Notably, delamination along the chip passivation from a chip edge or corner tends to cause almost instantaneous failure as soon as it reaches a solder joint. However, although difficult or impossible to measure directly, delamination elsewhere may affect this phenomenon quite strongly or contribute to solder joint failure in other ways. In particular, an apparent correlation between delamination from around individual solder joints and subsequent failure of those joints is easily misinterpreted. Silicon Figure 8 The stress distributions above were all based on the assumption of an undamaged system. However, these alone are insufficient to rationalize the performance of an underfilled flip chip assembly under repeated, or sequences of, loads. For example, cracking of the fillet perpendicular to the vertical chip edge (Figure 7) is quite commonly observed experimentally, and it does indeed increase with fillet thickness. However, this does not by itself affect the solder joints. More critically, as there is little chance of the crack extending into the silicon, the next step may be delamination from the vertical chip edge (Figure 8). The driving force for this also h h increases with the fillet thickness and the thermal mismatch 6, and in fact delamination from the vertical chip edges is primarily of concern for underfill materials with very high CTE, except at the chip corners. The driving force for fillet cracking is clearly enhanced at the sharp corners of the chip (Figure 9), and so is the tendency for this to be followed by delamination from the vertical edges. Indeed, although often very difficult to detect directly the latter appears to be a very common phenomenon for regular underfill materials as well. Silicon Figure 9 Delamination of the underfill from the vertical chip edges is of obvious concern. Complete delamination effectively eliminates the beneficial effects of the fillet, and the remaining bending stresses (Figure 2) usually lead to in-plane chip cracking or rapid delamination from the chip passivation as well. Figure 10 shows an example of a large corner fillet crack and an acoustic microscope image of the resulting delamination from the chip. Recently, detailed failure analysis by Sandia 7 showed the progression of a corner fillet crack, delamination from an adjacent vertical edge and the resulting chip cracking in a particularly convincing support of the present picture. Finally, even if effectively eliminating the fillet were to not cause immediate delamination from the passivation, the bending stresses Figure 10 5

Figure 11 might be expected to greatly enhance the fatigue of solder joints near the edge. An unusually large thermal expansion coefficient or contact angle may also cause vertical chip cracking from defects near the edge, or the edge fillet may start delaminating from the top of the vertical chip edge (Figure 5). In the absence of fillet cracking (and vertical or horizontal chip cracking) such delamination may well be deflected into a crack through the underfill away from the edge, but probably not until the remaining fillet is unable to maintain compression on vertical and horizontal chip surfaces near the bottom. Obviously, the actual path will depend on the relative strengths of adhesion and cohesion, and high adhesion would favor both relatively early crack deflection and a better resistance to delamination from the chip passivation. However, even partial delamination from the vertical edge may be sufficient to cause occasional in-plane cracking of chips with significant dicing defects or to enhance the fatigue of nearby solder joints. Not surprisingly, downward cracking of the underfill from the bottom of the chip edge (Figure 6) is also occasionally observed. In fact, as this is not readily detectable by scanning acoustic microscopy it may often be overlooked. Sometimes even extending through the solder mask and into the substrate this phenomenon also eliminates the effects of the edge fillet. Elimination of the compression exerted by the edge fillet may, of course, also cause in-plane cracking of a chip with particularly large dicing defects. Even in the absence of this and delamination from the chip passivation, however, it raises the out-of-plane load on solder joints near the chip edges and, in particular, the chip corners where the compression was the most effective before. Corner fillet cracking may thus eventually lead to enhanced fatigue and failure of joints near the corner, even without delamination from the passivation. This is likely to be most critical for underfills with large CTE. The thermal mismatch between underfill and substrate is often not very large, and the stress concentrations (Figure 5) thus not particularly critical. Except for in mechanical loading (handling), with underfill materials with very high CTE, or with substrate surfaces that are particularly difficult to bond to, delamination from the substrate is usually not an issue. As alluded to above, there is also a tendency for the underfill to start delaminating from the chip passivation around the individual solder joints and progress from there away from the edge towards the chip center. Figure 11 shows a scanning acoustic microscope image of such a case. In the absence of corner delamination this is eventually accompanied by electrical failure of the joints. There often appears to be a correlation between local delamination and failure for a given underfill, the joints with the largest degree of delamination around them usually failing first. However, comparing different underfill materials such a correlation is no longer evident. In fact, in some cases solder joints have failed before delamination around them became measurable. This is readily explainable on the basis of a combination of modeling and experimental observation. Figure 12 Figure 4 was based on the assumption of adhesion of the underfill everywhere, including to the solder joint surface. In that case, there is seen to be a driving force for shear driven delamination starting from the vertical chip edge. There is, however, no major driving force for delamination from around the joint. In fact, even if such delamination was somehow initiated there would be no reason for it to progress as 6

often observed. Figure 12 shows the normal and shear stress distributions along the chip passivation after onset of underfill delamination from the chip passivation around the solder joint. There is now indeed a singularity in the shear stress at the underfill-passivation interface, but this is counteracted by a singularity in the normal stress. More importantly, any further delamination would be expected to progress towards the chip edge as well as away from it. For a perimeter array this would soon eliminate the compression on the vertical edge, allowing for delamination from there as well and rapidly causing solder joint failure. This is generally not observed. Assuming instead that the underfill delaminates first from the surface of the solder joint itself, the further progression becomes more reasonable. The same is of course true if the underfill never adheres to the joint in the first place. Figure 13 shows the stress distributions with and without adhesion of the underfill to the solder joint surface. Delamination from the joint leads to both tension and shear on the underfill next to it. It is quite credible that this may lead to the onset of delamination from the chip passivation in further cycling. Once this occurs the preferred path of progression is obvious. Figure 14 shows the stress distributions for the case where the Normal Stress 100 50 0-50 underfill Figure 13 solder -100 105 110 115 120 125 Distance to Chip Center (mil) Figure 14 underfill underfill has delaminated from both the solder joint surface and the chip passivation in a 2 mil ring around the joint. There is now a singularity in tension across the underfill-passivation interface on the side of the joint away from the chip edge, but a singularity in compression on the opposite side. Detailed three dimensional modeling would undoubtedly modify these results but the overall trends would remain, i.e. there is now an obvious preference for continued delamination away from the chip edge. As for an apparent correlation between solder joint failure and degree of (local) delamination we return first to Figure 13. Delamination of the underfill from the solder joint surface is seen to greatly enhance the stresses across the chip-solder interface as well. To a first approximation we may thus take this as the onset of significant solder fatigue crack growth. In support of this scenario we note that even in the absence of detectable delamination from the surrounding chip passivation solder fatigue cracks invariably tend to develop and grow near the chip. This is what would be expected if the underfill does not adhere to the solder, while adhesion would have shifted the dominant fatigue crack growth to the substrate side. Finally, we note that delamination of the underfill from the chip passivation has relatively little effect on the fatigue. In fact, the stresses across the chipsolder interface remain quite similar to those in Figure 14 until the delamination finally reaches an outside chip edge. Progression of the delamination from around a joint thus has little effect on the solder fatigue and failure. An apparent correlation is based on the fact that more delamination of a given underfill material usually corresponds to an earlier onset of delamination and thus of solder fatigue. Consequences The present picture has obvious consequences for failure analysis. Correct identification of the failure mechanism(s) is vital for the interpretation and generalization of accelerated test data. An understanding of the competing damage mechanisms is also needed in order to properly define accelerated tests in the first place. Comparisons between alternative options, for example in terms of design or materials 7

combinations, should be conducted under individually optimized conditions. For example, the preferred edge fillet thickness clearly varies with materials combination (underfill, solder mask, flux,...), design (die and substrate thickness) and use environment. In terms of the latter it not only varies with aging and humidity exposure, it also depends on the relative importance of mechanical loading. Thicker fillets are more prone to thermal mismatch induced cracking but more robust in handling. Notably, an understanding of the effects of various parameters on the individual damage and failure mechanisms is critical to optimization and the definition of proper assembly process windows. Rather than optimizing the reliability of the typical assembly we should be uniquely concerned with very early failures which are not discovered in routine testing but may be addressed by appropriate planning. The overall picture should certainly have consequences for further materials developments. Notably, an improved underfill material should have better adhesion to the solder joint surface (in spite of the presence of flux residues), higher fracture toughness (to minimize fillet cracking), better adhesion to the chip edge and passivation (to minimize delamination after fillet cracking) and not be appreciably degraded by the incorporation (reaction or dissolution) of residues or in subsequent moisture exposure. Ideally, it should be compatible with all kinds of materials, residues and contaminants, but a clear identification of compatible materials would be a very good start. Adhesion of the underfill to the substrate (solder mask) surface is usually not very critical, except in handling. Our picture does not allow recommendations in terms of underfill modulus and CTE. A higher modulus would ensure more compression near the edge of the undamaged assembly, but a lower modulus may allow for reduced stress intensification and, often, enhanced fracture toughness. Similarly, a lower CTE (perhaps matched to that of the solder) reduces some of the critical stresses, but a higher CTE often involves fewer filler particles and thus better adhesion, as well as ensuring more compression near the edge of the undamaged assembly. Finally, the present picture forms the basis for an ongoing investigation of the dependencies of the individual damage mechanisms on accelerated testing parameters4. It is anticipated that this will enable the definition of optimized tests as well as the extrapolation of test results to life in service within the next few years. Highly conservative estimates for selected cases are anticipated within less than a year. Summary The present paper considered the reliability of an underfilled flip chip assembly as defined by the failure of the solder joints, with particular emphasis on the effects of thermal mismatch. Mechanical shock, vibration or general handling primarily affect the solder joints to the extent that it contributes to failure of the underfill, usually through fillet cracking and/or delamination from the vertical die edges followed by delamination from the die passivation, or by delamination from the substrate surface. Solder extrusion into adjacent underfill voids may reduce the fatigue resistance of the joints. However, even a perfectly adhering underfill without voids does not completely prevent solder joint fatigue in thermal cycling. Furthermore, indications are that many underfills adhere only weakly, or not at all, to the solder joints. Cycling then eventually leads to underfill delamination along the chip passivation from around the individual joints. The local stress distributions do, however, strongly favor delamination away from the chip edge, leaving the edge fillets intact for a substantial length of time. While the onset of this delamination is accompanied by an increase in fatigue crack growth rate, it is by no means immediately fatal, still allowing for considerable cycling to failure. Delamination from the corner or edge of the chip, on the other hand, leads to almost instantaneous failure as soon as it reaches a solder joint. Such delamination may occur if the edge fillet does not exert sufficient compression on the die surface to effectively counteract the local shear stress and the effects of thermal mismatch induced bending. This depends on chip and substrate thickness, as well as on the strength of the fillet. A thin fillet may not be strong enough to suppress delamination from the edge. A thick fillet, on the other hand, may 8

crack in a variety of ways because of the large stresses near chip edges and corners. A crack growing outward and downward from the bottom edge of the chip, often through the solder mask and into the substrate, eventually eliminates the compression on both the bottom surface of the chip and the vertical edge. Vertical cracking of the edge fillet usually does not appear to lead to delamination under the chip. Cracking at one of the chip corners, however, reduces compression on the vertical edges sufficiently to allow for delamination from these, which then again allows for delamination along the passivation on the bottom surface of the chip. Finally, an unusually large thermal expansion coefficient may cause the edge fillet to start delaminating from the top first. The delamination may branch out into a crack through the underfill away from the edge, but probably not before eliminating much of the beneficial effect of the fillet. Acknowledgements The contributions of Dr. Yan Sha, who carried out the FEM analysis, and a large number of former and current graduate students, who carried out the experiments, are gratefully acknowledged. Without them none of this would have been possible. References 1. P. Borgesen, Flip Chip Assembly Yield Prediction and Optimization, IMAPS, Braselton, GA, March 2000. 2. R. Boulanger, J. Carbin, and D. Viza, Flip Chip Assembly: As Easy as 1, 2, 3, Advanced Packaging, Vol. 8, Number 3, pp. 28, March 1999. 3. P. Borgesen, Flip Chip on Organic Substrates, SMTA Proceedings, pp. 121, San Jose, CA, September 1999 4. P. Borgesen, Flip Chip Reliability Assessment, IMAPS, Braselton, GA, March 2000. 5. C. G. M. van Kessel, S. A. Gee, and J. J. Murphy, The Quality of Die-Attachment and its Relationship to Stresses and Vertical Die- Cracking, Proc. ECC, pp. 237, 1983 6. M. D. Thouless, Cracking and Delamination of Coatings, J. Vac. Sci. Technol. A9(4), pp. 2510, 1991 7. D. W. Peterson, S. N. Burchett, J. N. Sweet, and L. Nguyen, Experiment-Based Computational Investigation of Thermomechanical Stresses in Flip Chip BGA Using the ATC4.2 Test Vehicle, SMTA Proceedings, pp. 167, San Jose, CA, September 1999. 9