Power MOSFET DTW2070 PRODUCT SUMMRY V DS (V) 200 R DS(on) ( ) V GS = 0 V 0.09 Q g (Max.) (nc) 70 Q gs (nc) 3 Q gd (nc) 39 Configuration Single FETURES Halogen-free ccording to IEC 6249-2-2 Definition Surface Mount Low-Profile Through-Hole vailable in Tape and Reel Dynamic dv/dt Rating 0 C Operating Temperature Fast Switching Fully valanche Rated Compliant to RoHS Directive 2002/9/EC I 2 PK (TO-262) D 2 PK (TO-263) D G D G S S N-Channel MOSFET BSOLUTE MXIMUM RTINGS (T C = 2 C, unless otherwise noted) PRMETER SYMBOL LIMIT UNIT Drain-Source Voltage V DS 200 Gate-Source Voltage V GS ± 20 V Continuous Drain Current V GS at 0 V T C = 2 C 20 I D T C = 00 C 3 Pulsed Drain Current a, e I DM 72 Linear Derating Factor.0 W/ C Single Pulse valanche Energy b, e E S 80 mj valanche Current a I R 20 Repetiitive valanche Energy a E R 3 mj Maximum Power Dissipation T C = 2 C 3. P D T = 2 C 30 W Peak Diode Recovery dv/dt c, e dv/dt.0 V/ns Operating Junction and Storage Temperature Range T J, T stg - to 0 Soldering Recommendations (Peak Temperature) for 0 s 300 d C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. ). b. V DD = 0 V, starting T J = 2 C, L = 2.7 mh, R g = 2, I S = 8 (see fig. 2). c. I SD 20, di/dt 0 /μs, V DD V DS, T J 0 C. d..6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply
THERML RESISTNCE RTINGS PRMETER SYMBOL TYP. MX. UNIT Maximum Junction-to-mbient (PCB Mounted, Steady-State) a R thj - 40 C/W Maximum Junction-to-Case (Drain) R thjc -.0 Note a. When mounted on " square PCB (FR-4 or G-0 material). SPECIFICTIONS (T J = 2 C, unless otherwise noted) PRMETER SYMBOL TEST CONDITIONS MIN. TYP. MX. UNIT Static Drain-Source Breakdown Voltage V DS V GS = 0 V, I D = 20 μ 200 - - V V DS Temperature Coefficient V DS /T J Reference to 2 C, I D = m c - 0.29 - V/ C Gate-Source Threshold Voltage V GS(th) V DS = V GS, I D = 20 μ 2.0-4.0 V Gate-Source Leakage I GSS V GS = ± 20 V - - ± 00 n V DS = 200 V, V GS = 0 V - - 2 Zero Gate Voltage Drain Current I DSS V DS = 60 V, V GS = 0 V, T J = 2 C - - 20 Drain-Source On-State Resistance R DS(on) V GS = 0 V I D = b - - 0.09 Forward Transconductance g fs V DS = 0 V, I D = d 6.7 - - S Dynamic Input Capacitance C iss V GS = 0 V, - 300 - Output Capacitance C oss V DS = 2 V, - 430 - Reverse Transfer Capacitance C rss f =.0 MHz, see fig. d - 30 - Total Gate Charge Q g - - 70 Gate-Source Charge Q gs I V GS = 0 V D = 20, V DS = 60 V, see fig. 6 and 3 b, c - - 3 Gate-Drain Charge Q gd - - 39 Turn-On Delay Time t d(on) - 4 - Rise Time t r V DD = 00 V, I D = 20, - - Turn-Off Delay Time t d(off) R g = 9., R D =.4, see fig. 0 b, c - 4 - Fall Time t f - 36 - Drain-Source Body Diode Characteristics MOSFET symbol D Continuous Source-Drain Diode Current I S - - 20 showing the integral reverse Pulsed Diode Forward Current a G I SM p - n junction diode - - 72 Body Diode Voltage V SD T J = 2 C, I S = 20, V GS = 0 V b - - 2.0 V Body Diode Reverse Recovery Time t rr T J = 2 C, I F = 20, di/dt = 00 /μs b, c - 300 60 ns Body Diode Reverse Recovery Charge Q rr - 3.4 7. μc Forward Turn-On Time t on Intrinsic turn-on time is negligible (turn-on is dominated by L S and L D ) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. ). b. Pulse width 300 μs; duty cycle 2 %. c. Uses IRF640/SiHF640 data and test conditions. S μ pf nc ns 2
TYPICL CHRCTERISTICS (2 C, unless otherwise noted) I D, Drain Current () 0 0 0 V GS Top V 0 V 8.0 V 7.0 V 6.0 V. V.0 V Bottom 4. V 4. V I D, Drain Current () 0 0 0 0 C 2 C 20 µs Pulse Width T C = 2 C 0-20 µs Pulse Width V DS = 0 V 0-0 0 0 4 6 7 8 9 0 9037_0 V DS, Drain-to-Source Voltage (V) 9037_03 V GS, Gate-to-Source Voltage (V) Fig. - Typical Output Characteristics, T J = 2 C Fig. 3 - Typical Transfer Characteristics I D, Drain Current () 9037_02 0 0 0 Top Bottom V GS V 0 V 8.0 V 7.0 V 6.0 V. V.0 V 4. V 0-0 0 0 20 µs Pulse Width T C = 0 C V DS, Drain-to-Source Voltage (V) 4. V R DS(on), Drain-to-Source On Resistance (Normalized) 9037_04 3.0 2. 2.0..0 0. I D = 20 V GS = 0 V 0.0-60 - 40-20 0 20 40 60 80 00 20 40 60 T J, Junction Temperature ( C) Fig. 2 - Typical Output Characteristics, T J = 7 C Fig. 4 - Normalized On-Resistance vs. Temperature 3
Capacitance (pf) 9037_0 3000 200 2000 00 000 00 C iss C oss C rss 0 0 0 0 V GS = 0 V, f = MHz C iss = C gs C gd, C ds Shorted C rss = C gd C oss = C ds C gd V DS, Drain-to-Source Voltage (V) I SD, Reverse Drain Current () 9037_07 0 C 2 C 0 0 0 V GS = 0 V 0.0 0.70 0.90.0.30.0 V SD, Source-to-Drain Voltage (V) Fig. - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage V GS, Gate-to-Source Voltage (V) 20 6 2 8 4 I D = 20 V DS = 00 V V DS = 40 V V DS = 60 V For test circuit see figure 3 0 0 30 4 60 7 I D, Drain Current () 0 3 2 0 2 2 0 2 2 0. 0. 2 Operation in this area limited by R DS(on) T C = 2 C T J = 0 C Single Pulse 2 0 2 0 2 0 µs 00 µs ms 0 ms 2 0 3 9037_06 Q G, Total Gate Charge (nc) 9037_08 V DS, Drain-to-Source Voltage (V) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 8 - Maximum Safe Operating rea 4
22 V DS R D I D, Drain Current () 9037_09 8 4 0 0 2 0 7 00 2 0 T C, Case Temperature ( C) R g V GS 0 V Pulse width µs Duty factor 0. % D.U.T. Fig. 0a - Switching Time Test Circuit V DS 90 % - V DD Fig. 9 - Maximum Drain Current vs. Case Temperature 0 % V GS t d(on) t r t d(off) t f Fig. 0b - Switching Time Waveforms 0 Thermal Response (Z thjc ) 9037_ 0. 0-2 0-3 0 0. 0.2 0. 0.0 0.02 0.0 Single Pulse (Thermal Response) 0-0 -4 0-3 0-2 0. 0 t, Rectangular Pulse Duration (s) P DM t t 2 Notes:. Duty Factor, D = t /t 2 2. Peak T j = P DM x Z thjc T C Fig. - Maximum Effective Transient Thermal Impedance, Junction-to-Case
V t p V DS V DS L Driver R g 20 V t p D.U.T. I S 0.0 Ω - V DD I S Fig. 2a - Unclamped Inductive Test Circuit Fig. 2b - Unclamped Inductive Waveforms E S, Single Pulse Energy (mj) 9037_2c 400 200 000 800 600 400 200 Top Bottom I D 8.0.0 20.0 V DD = 0 V 0 2 0 7 00 2 0 Starting T J, Junction Temperature ( C) Fig. 2c - Maximum valanche Energy vs. Drain Current Current regulator Same type as D.U.T. 0 V Q G 2 V 0.2 µf 0 kω 0.3 µf Q GS Q GD D.U.T. V - DS V G V GS Charge Fig. 3a - Basic Gate Charge Waveform 3 m Fig. 3b - Gate Charge Test Circuit I G I D Current sampling resistors 6
Peak Diode Recovery dv/dt Test Circuit D.U.T. - Circuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer - - R g dv/dt controlled by R g Driver same type as D.U.T. I SD controlled by duty factor D D.U.T. - device under test - V DD Driver gate drive P.W. Period D = P.W. Period V GS = 0 V a D.U.T. l SD waveform Reverse recovery current Body diode forward current di/dt D.U.T. V DS waveform Diode recovery dv/dt V DD Re-applied voltage Inductor current Body diode forward drop Ripple % I SD Note a. V GS = V for logic level devices Fig. 4 - For N-Channel 7
TO-263B (HIGH VOLTGE) (Datum ) 3 4 E 4 L 4 D H 2 C 3 C L2 B B Detail c2 B Gauge plane 0 to 8 L3 L L4 Detail Rotated 90 CW scale 8: H B Seating plane 2 x b2 2 x e 2 x b 0.00 M M B Plating b, b3 c ± 0.004 M B Base metal E D 4 (c) c Lead tip (b, b2) Section B - B and C - C Scale: none E View - 4 MILLIMETERS INCHES MILLIMETERS INCHES DIM. MIN. MX. MIN. MX. DIM. MIN. MX. MIN. MX. 4.06 4.83 0.60 0.90 D 6.86-0.270-0.00 0.2 0.000 0.00 E 9.6 0.67 0.380 0.420 b 0. 0.99 0.020 0.039 E 6.22-0.24 - b 0. 0.89 0.020 0.03 e 2.4 BSC 0.00 BSC b2.4.78 0.04 0.070 H 4.6.88 0.7 0.62 b3.4.73 0.04 0.068 L.78 2.79 0.070 0.0 c 0.38 0.74 0.0 0.029 L -.6-0.066 c 0.38 0.8 0.0 0.023 L2 -.78-0.070 c2.4.6 0.04 0.06 L3 0.2 BSC 0.00 BSC D 8.38 9.6 0.330 0.380 L4 4.78.28 0.88 0.208 ECN: S-820-Rev., -Sep-08 DWG: 970 Notes. Dimensioning and tolerancing per SME Y4.M-994. 2. Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.27 mm (0.00") per side. These dimensions are measured at the outmost extremes of the plastic body at datum. 4. Thermal PD contour optional within dimension E, L, D and E.. Dimension b and c apply to base metal only. 6. Datum and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263B.
RECOMMENDED MINIMUM PDS FOR D 2 PK: 3-Lead 0.420 (0.668) 0.63 (6.29) 0.3 (9.07) 0.4 (3.683) 0.3 (3.429) 0.200 (.080) 0.00 (.27) Recommended Minimum Pads Dimensions in Inches/(mm)
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