I. Motivation & Examples Output depends on current input and past history of inputs. State embodies all the information about the past needed to predict current output based on current input. State variables, one or more bits of information. If the current State of the circuit is known at time t, what is the state of the circuit at time (t+1) Answer: the next state depends on current state and input 1
I. Motivation & Examples Describing sequential circuit State table For each current-state, specify next-states as function of inputs For each current-state, specify outputs as function of inputs State diagram Graphical version of state table Example 1: TV channel control Let the channel # represent the state of the circuit Input are up/down on the channel control 2 on u u u u u 1 2 3 4 99 d d d d d u: up d: down
I. Motivation & Examples Example 2: A sequential process that inputs an n-bit binary string and outputs 1 if the string contains an even number of 1 s 01111 SLN 1 (final output) 0111 SLN 0 (final output) What represents the state of the circuit? Case1: State as the number of 1 s read so far (possibly infinite # of states) 3 Case 2: Two states E and O E (even): if the # of 1 s read so far is even O (odd) if the # of 1 s read so far is odd
I. Motivation & Examples Example 2: State Diagram for Case 1 Input Output 0 1/0 1/1 1/0 1/1 1 2 3 4 1/0 1/1 2n 0/1 0/0 0/1 0/0 0/1 0/1 Example 2: State Diagram for Case 2 Input Output 4 E 0/1 1/0 1/1 O 0/0
I. Motivation & Examples Example 2: State Diagram for Case 2 Input Output E 0/1 1/0 1/1 O 0/0 Better design Has less states 5
I. Motivation & Examples Example 3: Discuss sequential n-bits comparator Compare two n-bits numbers X=[Xn-1,, X0], Y=[Yn-1,, Y0] Output 1 if X>Y Use the basic 1-bit comparator designed in class Shift right... Xn-1 Xn-2 Xn-3 X2 X1 X0 Xi Fi-1 1-bit Comparator Yi Ci Operation controlled by a clock to decide:.when to shift input data.when output Fi is stable Yn-1 Yn-2 Yn-3... Y2 Y1 Y0 Shift right Fi 6
I. Motivation & Examples Example 4: Discuss sequential n-bits adder Add two n-bits numbers X=[Xn-1,, X0], Y=[Yn-1,, Y0] Output S=X+Y where [Sn,Sn-1,,S0] Use the basic 1-bit adder with carry in and carry out Shift right... Xn-1 Xn-2 Xn-3 X2 X1 X0 Xi Ci-1 1-bit Full adder Ci Yi Operation controlled by a clock to decide:.when to shift input data.when output are ready 7... Shift right Yn-1 Yn-2 Yn-3 Y2 Y1 Y0 Sn Ci Shift right... Sn-1 Sn-2 S2 S1 S0
II. General Representation Clock signals Sequential circuit are controlled by a clock signal Very important with most sequential circuits State variables change state at clock edge. 8
II. General Representation General diagram of sequential circuit Sequential circuit are controlled by a clock signal Very important with most sequential circuits State variables change state at clock edge. Input Output i0 i1 in Current states SLN Next states o0 o1 om Feedback Memory components 9 State variables: s0,s1, sk
II. General Representation Some important questions How to represent the states of a sequential circuit? How to memorize the (current and next) states? How to determine the next of the circuit? How to determine the outputs as a function F(state) of current state only? as a function F(input,state) of both input and current state? The concept of STATE is very important 10
II. General Representation Memory component How do we represent the states? Memory component are used as state variables Goal: Memorize the current state of the circuit How are memory components implemented? Latch, Flip-flop are 1-bit memory component 11
Bistable element The simplest sequential circuit Two states One state variable, say, Q (QN or Q_L the complement of Q) HIGH LOW LOW HIGH 12
Bistable element The simplest sequential circuit Two states One state variable, say, Q LOW HIGH HIGH LOW 13
Bistable element: Analog analysis Assume pure CMOS thresholds, 5V rail Theoretical threshold center is 2.5 V 14
Bistable element: Analog analysis Assume pure CMOS thresholds, 5V rail Theoretical threshold center is 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 15
Bistable element: Analog analysis Assume pure CMOS thresholds, 5V rail Theoretical threshold center is 2.5 V 4.8 2.51 VV 2.5 2.0 0.0 V 2.5 2.0 0.0 V 4.8 5.0 2.5 V 16
II. General Representation Bistable element: summary 1 2 17 If (Q=0), then input to Not gate 2 is 0 ==> Output of Not gate 2 is 1 (Q_L =1) ==> The input of Not gate 1 is 1, so output of Not gate 1 is 0 ==> Stable output (Q=0) and (Q_L = 1) If (Q=1), then input to Not gate 2 is 1 ==> Output of Not gate 2 is 0 (Q_L =0) ==> The input of Not gate 1 is 0, so output Not gate 1 is ==> Stable output (Q=1) and (Q_L = 0)
S-R Latch. How to control it? Screwdriver Control inputs S-R latch Contradiction!!!! 18
S-R Latch. 19 Set operation: SR 00 ----> 10, set the device output to Q=1 regardless of current value of Q Reset operation: SR 00 ----> 01, set the device output to Q=0 regardless of current value of Q Hold operation: SR 10 ----> 00 or 01 ----> 00, Device output are the same as last output values Only one input value changes Possible input changes: SR: 00 ---> 01 ---> 00 ---> 10 ---> 00. Input SR = 11 is not allowed ( Both NOR gates output 0, i.e Q=Q =0 )
S-R latch operation 20
Propagation delay Minimum pulse width S-R latch timing parameters 21 Progation delay Minimum time to maintain signal at 1
S-R latch symbols 22
S-R latch with enable 23
Sequential network architecture (revisited) Input i1 in... SLN... Output o1 om M1... Components Mi are latches/flip flops 24 Mk Operation rules: Memory components Mi must be in stable state before input changes Only one input of the component Mi can change at a time
Charcteristics equation of S-R latch Definition: The characteristic equation specifies a flip-flop next state as a function of its current state and inputs 25 Notation: Let q represent the current state of the flip-flop and Q its next Characteristics table S R q 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Q 0 1 0 0 1 1 X X Q=q Q=0 Q= 1 Not allowed Hold Reset Set
Charcteristics equation of S-R latch Use the characteristics table to get an excitation map of the flip flop Characteristics table S R q 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Q 0 1 0 0 1 1 X X Q=q Q=0 Q= 1 SR q 0 1 Q 00 01 11 10 X 1 1 X 1 Use K-map method to derive the characteristics equation: 26 Q = S + R q
Excitation table of SR flip flop The excitation table describes the input values of S and R that cause the corresponding transitions (q ---> Q) from current to next state 27 Types of transitions: q --->Q 0 ---> 0 0 ---> 1 1 ---> 0 Excitation table of S R latch 1 ---> 1 0 0 to hold current value OR 1 0 to set Q=1 q ---> Q S R 0 ---> 0 0 X 0 ---> 1 1 0 1 ---> 0 0 1 1 ---> 1 X 0 0 0 to hold current value OR 0 1 to reset Q=0
D latch 28
D-latch operation 29
D-latch timing parameters Propagation delay (from C or D) Setup time (D before C edge) Hold time (D after C edge) 30
Edge-triggered D flip-flop behavior 31
Edge-triggered D flip-flop behavior 32
D flip-flop timing parameters Propagation delay (from CLK) Setup time (D before CLK) Hold time (D after CLK) 33