Thermal aspects of 3D and 2.5D integration

Thermal aspects of 3D and 2.5D integration Herman Oprins Sr. Researcher Thermal Management - imec Co-authors: Vladimir Cherman, Geert Van der Plas, Eric Beyne European 3D Summit 23-25 January 2017 Grenoble, France

Introduction 3D integration is a promising technology for integrated circuit design: Small form factor and shorter interconnect lengths Allows heterogeneous integrations Higher IO density than 2D packaging solutions Thermal issues of 3D integration: Vertical integration of different layers Low thermal conductivity materials Thinned stacked dies Strong thermal coupling between components in 3D stack: components heat up due to power generation in other chips in the die stack Innovative cooling solutions discussed in other presentations of this session H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 2

Introduction This presentation: learnings from test vehicle data on thermal aspects of 3D integration scenarios Comparison 3D stacking vs integration on interposer Memory Logic Logic Memory 3D-SIC package Interposer package Assessing thermal impact of stacking options: die-to-die/die-to-wafer vs wafer-to-wafer bonding 1.8 µm pitch Top Wafer 540 nm 1260 nm Bottom Wafer 2 µm H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 3

Thermal impact of packaging configuration: 3D vs 2.5D integration

PTCQ test vehicle Dedicated CMOS test chip developed for thermal and mechanical analysis of 3D integration aspects Test chip features: 32 x 32 array of temperature sensors full chip map Programmable power dissipation map custom power map Steady state and transient analysis Detailed validation of thermal models 8 mm x 8 mm test chip IMEC 3D 65nm CMOS IC 3D + IMEC Si Interposer Interposer H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 5

Test packages 3D-SIC packages Si interposer packages Die 1: 200µm Die 2: 50µm Die 1 Die 2 14 x 14 mm 2 FCBGA 35 x 35 mm 2 FCBGA PTCQ 200 µm Interposer 100 µm Molded packages Bare die packages Lidded packages Bare die packages H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 6

Measurement environment Different experimental setups to cover range of low power and high power applications Measurement set-up designed to handle high currents (100A) Measurement of actual dissipated power in package Low power applications Socket cover Spacer High power applications BGA Socket 1. Socket without cooling 2. Socket with fan H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 7

Steady state test case Emulation of memory on logic application using 3D package with two thermal test chips: Logic die with 8 cores (1x1.5 mm 2 ); 1W total power dissipation Memory die: no power dissipation in this study Comparison for both low power and high power configurations Memory Logic power density p Logic 3D-SIC package 0 W/cm 2 Logic Memory 10 W/cm 2 Interposer package H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 8

High power applications Measured temperature increase (K/W) in high power socket Bare die interposer package 1.5 Heated die Neighboring die 1 Bare die 3D package 2.2 0.5 Heated bottom die Top die 1.6 0.8 H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 9

Low power applications Measured temperature increase (K/W) in low power socket Lidded die interposer package Heated die Neighboring die 10.5 9.5 Molded die 3D package 10.5 9.5 Heated bottom die 8 Top die 8 17 15.5 H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 10 14

Measured temperature profiles Norm. temp. inecrease (K/W) 18 16 14 12 10 8 Logic Memory 3D-SIC LP 0 2 4 6 8 Distance (mm) Norm. temp. increase (K/W) 18 16 14 12 10 8 Logic Memory Interposer LP 0 2 4 6 8 10 12 14 16 18 20 Distance (mm) 2.5 2.5 Norm. temp. inecrease (K/W) 2 1.5 1 0.5 0 Logic Memory 3D-SIC HP 0 2 4 6 8 Distance (mm) Norm. temp. increase (K/W) 2 1.5 1 0.5 0 Logic Memory Interposer HP 0 2 4 6 8 10 12 14 16 18 20 Distance (mm) H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 11

Steady state analysis The logic temperature is 35% lower in the interposer package The memory temperature is 45% and 65% lower in the interposer package for the low power and power package respectively compared to the 3D package. The memory temperature distribution in the interposer package does not depend on the logic power distribution pattern. Much stronger thermal coupling observed in 3D-package compared to interposer package Temperature profile transferred from heated die to other die in package Higher temperature level in other die Lower overall temperature in interposer package due to larger footprint H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 12

Transient analysis Monitoring of temperature evolution as function of time for heating curve Test case: Power dissipation in 1x1 mm 2 hot spot 3D package in LP socket Interposer in LP socket 16.1ºC/W Temp. increase (ºC/W) Active bottom die Temperature increase (ºC/W) Active die 1 PTCQ power map Passive top die Passive die 2 H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 13

Transient analysis PTCQ package Large thermal capacitance of plastic socket and natural convection boundary condition Long time required for steady state: more than ½ hour Successful measurements of complete time by combining measurements with different time scales: 1s heating time ½ hour heating time Thermal delay in package measured: Within heated chip (center HS vs corner) Between two chips Temperature increase (ºC/W) 35 30 25 20 15 10 5 HS Active - 1s HS-Active - 1800s HS - Passive - Comb. data Corner - Active - Comb. data Corner - Passive - Comb. data Chip level effects Package level and boundary condition effects 0 1E-5 1E-4 1E-3 1E-2 1E-1 1E+0 1E+1 1E+2 1E+3 1E+4 Time (s) H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 14

Benchmarking transient thermal behavior Longer heating time observed for interposer package compared to 3D package Longer thermal delay between active and passive die on interposer package For the same maximum allowed temperature, a longer power pulse with the same power, or a higher power pulse with the same duration can be applied in the interposer package compared the 3D package Temp. increase ( C/W) 35 3D LP, active die 30 3D LP, passive die Interposer, active die 25 Interposer, passive die 20 15 10 5 0 1E-5 1E-4 1E-3 1E-2 1E-1 1E+0 1E+1 1E+2 1E+3 1E+4 Time (s) H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 15

Stacking options: Die-to-die vs wafer-to-wafer

Inter-tier interface impact Large impact of inter-tier thermal resistance on overall thermal resistance in case of multi-tier stack Estimation of contribution for N-die stack: # of die % of total R th 2 17 4 38 8 59 16 76 Comparison of test vehicle data for different interfaces: PTCQ die stack with µbumps and underfill material PTCS wafer pair: hybrid Cu/dielectric bonding H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 17

PTCQ die-die thermal resistance Top die Bottom die Measured temperature difference (K/W) Quasi 1D heat flow in bare die packages in high power socket Temperature difference between bottom and top die at diode location die is an indication for the inter die thermal resistance Pointwise die die thermal resistance R die-die distribution H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 18

PTCQ die-stack interface µbump properties: 40µm pitch 13µm stand off Cu pads 5µm thick Top pad Ø15µm, bottom pad Ø25µm, 3µm CuSn IMC Temperature difference between bottom and top die at diode location die is an indication for the inter die thermal resistance Total die-die thermal resistance: 8.3mm 2 -K/W Extracted thermal resistance of µbump underfill layer after subtraction of BEOL and passivation impact: 4.2 mm 2 -K/W H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 19

Inter die thermal resistance (mm 2 K/W) Extrapolation Reduce thermal resistance of µbump / underfill layer: 14 12 10 8 6 4 2 0 Increase bump fill fraction: add dummy bumps, larger bumps or finer pitch Increase underfill thermal conductivity Decrease stand-off No UF PTCQ measurement 1 W/m.K 0.2 W/m.K 2 W/m.K 0.4 W/m.K BEOL + passivation 0 20 40 60 Stand-off height (µm) Extrapolation using calibrated model for underfill conductivity and stand-off height and bump pitch Trade-off between stand-off height and thermal conductivity Stand-off height reduction shows potential for thermal resistance reduction in die-die interfaces in the stack H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 20

Die die thermal resistance UF conductivity and bump geometry impact Inter die thermal resistance (mm 2.K/W) 40 35 30 25 20 15 10 5 0 FC - 140um µbmp - 10µm µbump - 40µm µbump - 20µm W2W - 0.5µm BEOL-pass. 0 1 2 3 4 5 Underfill conductivity (W/m.K) Same data plotted for specific bump configurations Above certain conductivity value, little additional gain (µm) Pitch Pad Stand-off height FC-140 140 50 80 µb 40 40 25/15 13 µb 20 20 12.5/7.5 13 µb 10 10 6.25/3.75 13 W2W 5 0.540 1 H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 21

Hybrid bonding introduction Wafer to wafer bonding options: Hybrid Cu/dielectric bonding Wafer 1 Wafer 1 Wafer 1 Dielectric bonding Wafer 1 Wafer 2 Wafer 2 Wafer 2 Wafer 2 W2W aligned hybrid bonding Wafer thinning, TSV reveal, and RDL W2W aligned dielectric bonding Wafer thinning, Via-last TSV process, and RDL Vias processed before bonding Considered in this presentation Vias processed after bonding H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 22

Hybrid bonding test vehicle PTCS Passive test vehicle for wafer-to-wafer bonding characterization Test structures designed in BEOL M1 layer of top and bottom 3.6 µm and 1.8 µm pitch 1.3 µm interface thickness Schematic cross-section wafer pair: Top Wafer 3.6 µm pitch 900 nm 2700 nm Top wafer 50 µm P1 TSV M1 Top 2 µm 1.8 µm pitch Top Wafer 540 nm 1260 nm Bottom wafer P1 Bot M1 Bot Bottom Wafer 2 µm H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 23

Thermal test structures Passive test chip (1 metal layer BEOL with test structures for connection yield, electrical tests, RF, electro-migration, thermal characterization, bonding overlay tolerance and reliability Resistive structures in top and bottom wafer 100 x 100 µm heater Thermal structures Heater region 30 x 8.5 µm Sensor 26 x 14 mm 2 test chip H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 24

Thermal resistance map of wafer pair Die-die interface resistance (mm 2 -K/W) -4-3 -2-1 0 1 2 3 4 5 6 0 1.21 1.29 1 1.17 1.28 2 1.15 1.27 1.31 3 1.27 1.22 1.30 4 1.17 1.20 1.29 5 1.20 1.23 6 1.23 1.27 1.22 7 1.15 1.22 1.26 1.29 8 1.21 1.27 9 1.19 1.11 1.20 1.20 1.20 10 1.18 1.22 1.22 1.20 11 1.21 1.20 1.26 12 1.20 1.17 1.21 1.21 1.19 13 1.17 1.24 1.24 1.13 14 1.18 1.26 1.19 1.20 15 1.19 16 1.17 1.21 1.16 17 1.10 1.17 1.18 1.26 18 1.20 1.17 1.17 19 1.17 1.16 1.16 20 1.14 1.26 1.21 ± 0.1 mm 2.K/W H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 25

PTCS inter-tier thermal resistance Low on wafer variability: very consistent measurements for the 65 measured dies Die die interface based on target thickness values: Die-die interface thickness: 1.3 µm Thermal resistance 0.7-0.8 mm 2 -K/W Value for oxide only, no impact of pads Extracted resistance: 1.1-1.3 mm 2 -K/W Difference due to interface contact resistance and thickness variations Impact of additional annealing step to be studied 1.3 µm Cu Cross section Si PMD PMD Si Cu 120nm SiCN 500 nm SiO 2 5/25 nm SiCN/SiCO H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 26

Benchmarking (1) Die-to-die stacking µbumps Wafer-to-wafer hybrid bonding Top Wafer 1.8 µm pitch 540 nm 1260 nm Bottom Wafer 2 µm PTCQ test vehicle 40 µm pitch Cu/Sn µbumps 13 µm stand off PTCS test vehicle 3.6 / 1.8 µm pitch Cu pads 1.3 µm stand off UF/µbump layer R th Dielectric layer R th 4.5 mm 2 -K/W 1.2 mm 2 -K/W 4x reduction of the die die thermal resistance observed for W2W hybrid bonding compared to die stacking H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 27

Benchmarking (2) Cu-Cu direct bonding Wafer-to-wafer hybrid bonding Top Wafer 1.8 µm pitch 540 nm 1260 nm 10um 5um 25um Top tier Bottom tier Cu-Cu bonding Bottom Wafer 2 µm 3D130c test vehicle 10 µm pitch Cu bonds 700 nm thick BCB layer Dielectric layer R th 2.8 mm 2 -K/W PTCS test vehicle 3.6 / 1.8 µm pitch Cu pads 1.3 µm stand off Dielectric layer R th 1.2 mm 2 -K/W Not only impact of thickness, also of thermal conductivity: lower thermal resistance for anorganic material compared to organic H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 28

Benchmarking with literature data Die-die interface µbumps with underfill [1] µ-solder joints with underfill [2] Stand-off height Pitch Die-die thermal resistance Interface properties 50 µm 8.0 mm 2 -K/W Underfill conductivity 0.4 16 µm 71 µm 15.5 mm 2 -K/W W/m-K 100 µm 19.0 mm 2 -K/W 15.6 mm 2 -K/W Capillary underfill 0.4 W/m-K 12.1 mm 60 µm 50 µm 2 Neck-based underfill 0.7 -K/W W/m-K 4.8 mm 2 Percolating underfill 2.8 W/m- -K/W K CuSn µbumps with underfill 13 µm 40 µm 4.2 mm 2 -K/W Cu-Cu bonds with BCB [3] 700 nm 20 µm 2.8 mm 2 -K/W µc4 joints [4] Modeling results 7.5 µm Hybrid Cu / dielectric bonding 1.3 µm No flow underfill with silica particles 0.4 W/m-K Organic adhesive (BCB) 0.29 W/m-K 50 µm 2.88 mm 2 -K/W Modeling results for an 20 µm 2.75 mm 2 -K/W underfill material with thermal 10 µm 2.70 mm 2 -K/W conductivity 0.4 W/m-K 3.6/1.8 µm 1.2 mm 2 -K/W Impact of SiO 2 dielectric (inorganic) material only H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 29

Benchmarking references 1. Colgan, E.G., Andry, P., Dang, B., Magerlein, J.H., Maria, J., Polastre, R.J., and Wakil, J., 2012, Measurement of Microbump Thermal Resistance in 3D Chip Stacks, Proc. IEEE 28 th Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM), pp. 1-7. 2. Brunschwiler, T., Goicochea, J., Matsumoto, K., Wolf, H., Kumin, C., Michel, B. Wunderle, B. and Faust, W., 2011 Formulation of percolating thermal underfill by sequential convective gap filling, Proc. IMAPS 2011, Phoenix, AZ, USA, p. 229-237. 3. Oprins, H., Cherman, V., Vandevelde, B., Torregiani, C., Stucchi, M., Van der Plas, G., Marchal, P., and Beyne, E. 2011, "Characterization of the thermal impact of Cu-Cu bonds achieved using TSVs on hot spot dissipation in 3D stacked ICs," 61 st IEEE Electronic Components and Technology Conference (ECTC), Lake Buena Vista, FL, pp. 861-868. 4. Matsumoto, K. and Taira, Y., 2009, Thermal Characterization of a Three-Dimensional (3D) Chip Stack, Trans JIEP, 2(1),pp. 153-159 H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 30

Summary and conclusions

Impact of packaging configuration: Stackable PTCQ test chip with integrated heaters and sensors presented that allows application of a user-defined power map in both tiers and scanning the temperature of the full chip surface Interposer configuration has superior thermal performance in steady state and transient regime compared to 3D stacked package, at the cost of larger package footprint. Impact of inter-tier interface and stacking options: Hybrid W2W is a promising technique to reduce the inter-tier thermal resistance by reducing the stand-off, and by using an anorganic material 4X improvement compared to 40 µm pitch µbump interface for die-to-die stacking H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 32

Questions? oprins@imec.be H. Oprins Thermal aspects of 3D integration European 3D Summit Jan. 25, 2017 33