Are Carbon Nanotubes the Future of VLSI Interconnections? Kaustav Banerjee and Navin Srivastava University of California, Santa Barbara

Are Carbon Nanotubes the Future of VLSI Interconnections? Kaustav Banerjee and Navin Srivastava University of California, Santa Barbara

Forms of Carbon Carbon atom can form several distinct types of valence bonds.

A bit of history. Edison's original carbon-filament lamp US Patent 223898 1880 Discovery of Fullerenes (Smalley) 1985 Carbon nanotube transistor based logic-performing ICs (IBM) 2001 1978 F/A-18 Hornet The first aircraft with carbon fiber wings 1991 Nanotubes discovered at NEC, by Japanese researcher Dr. Sumio Iijima 2002 Carbon nanotubes in interconnet applications (Kreupl, Infineon) Vias

Outline What is wrong with Copper? What are Carbon Nanotubes? What are the requirements for introducing a new interconnect material? Do s satisfy these requirements? Summary

What is wrong with Cu? Future Interconnect Requirements: 2005 ITRS Red Areas: no known solutions! from 2014 onwards: J max > 1.06 x 10 7 A/cm2

What is wrong with Cu? Size effect on Cu resistivity MFP of Cu ~ 40 nm at room temperature Resistivity [μω-cm] 5 4 3 2 1 Intermediate Tier Wires Barrier Layer Effect At 300 K Surface Scattering Grain Boundary Scattering Background Scattering (ρ o ) Total 0 90 65 45 32 Technology Node [nm] 22 Im et al., IEEE TED, Dec. 2005 Based on analytical models in Steinhogl et al., J. Appl.. Phys.,, 2005. Impact is worse for local wires and vias Increases wire delay: even in local wires

What is wrong with Cu? Thermal Conductivity [W/(m-K)] 1.6 DEM Model (Xerogel) PWSM Model (Xerogel) 1.2 0.8 0.4 0.0 FSG HSQ CDO Polymer MSQ Xerogel 1 2 3 4 Dielectric Constant FEM Simulations 770 K 45 nm 378 K Im et al., IEEE TED, Dec. 2005 Interconnect resistivity Current density ILD thermal conductivity Cu interconnect temperature rises significantly due to self-heating.

What is wrong with Cu? Electromigration Lifetime: strongly reduces with temperature Limits maximum current carrying capacity. 18 16 14 12 10 8 6 4 Max allowed ITRS requirement Duty Ratio = 0.001 Maximum allowed J based on selfconsistent (EM+Self-heating) solutions Significant deficit in current carrying capacity for local vias. 2 0 90nm 65nm 45nm 30nm 22nm Technology Node Increasing via size and/or number will be expensive. Im et al., IEDM 2002; Srivastava et al., VMIC 2004

What are Carbon Nanotubes? Graphene Single-Walled Nanotube (SW) Eg ~1/d: Thick (>5nm) MWs have a vanishing band gap at 300K, hence metallic.. Multi-Walled Nanotube (MW) Courtesy: F. Kreupl, Infineon

What are Carbon Nanotubes? SWs Armchair Nanotube (metallic) Zigzag Nanotube (semi-conducting) Various roll-ups possible depending on chirality Chiral nanotube

Attractive properties of Carbon Nanotubes Length: microns to millimeters Diameter: 0.4-100 nm Tensile strength: 45 TPa! (high strength steel ~ 2TPa) Temperature Stability: up to 2800 0 C in vacuum and up to 700 0 C in air Cu Max current density (A/cm 2 ) >1x10 9 Max current density (A/cm <1x10 7 <1x10 Wei,, et al., APL,, 2001 Thermal conductivity (W/mK mk) 5800 Hone, et al., Phys. Rev. B, B 1999 385 Mean free path (nm) @ room temp >1000 McEuen,, et al., Trans. Nano., 2002 40

What are the requirements for a new interconnect material? Resistance to electromigration High current carrying capacity High mechanical strength New Interconnect Material Reliability Performance High conductance (low resistivity) Process Integration CMOS process compatible Low thermal budget Low diffusivity in dielectrics and Si

Do s satisfy these requirements? need to evaluate: Performance Reliability Process Integration

Interconnect Performance Model R, C and L: Important to understand mesoscopic physics

Resistance: R Q, R C and R S R Q 6.45 KΩ: K Intrinsic nanotube quantum contact resistance - even for very short lengths with no scattering and perfect contacts (lowest( possible R R hence need bundles!) R C : Imperfect metal-nanotube parasitic contact resistance (can( be high up to 100 KΩ) K R S : length dependent scattering resistance (for Length >> mfp =λ) = h 4e h 2 4e S. Datta, Nanotechnology, 2004 = 2 L λ

Bundle Resistance x d x accounts for density of metallic s calculate n in terms of w, h, d and x h N. Srivastava et al., IEDM 2005 R R bundle bundle = = R n R n w isolated isolated = R + R Q n C R Q + RC + R = n Note: higher n S... if... if L >> L < λ Assuming parallel independent currents-- H. Stahl, et al., Phys. Rev. Lett., 2000 λ lower R bundle Hence dense bundle is desirable, i.e., smallest possible d and x

Inductance: L K and L M E f ev E I Additional Kinetic energy stored in the system when a current (I) flows: 1 h ΔE = 2 2 2e v F I 2 Initially For a equal current number (I) to of flow left-moving to the left, (k<0) there and must right-moving be an excess (k>0) of Magnetic electrons k>0 electrons inductance Magnetic energy stored in a current carrying wire over a substrate d y k L K L M 16nH = μ ln 2π / μm Kinetic inductance: for L << mfp (Bockrath, PhD Thesis, Berkeley, 1999) y d

Bundle Inductance L M L M L K LK = LK / 4 L M L K L bundle = L M + L n K L M L M L K L K Large n makes L bundle small delay dominated by RC

Capacitance: C Q and C E Electrostatic capacitance C E Quantum capacitance C = 4C Q C Q C Q C Q C Q Q bundle Quantum capacitance = n C Q bundle 4C Q Electrostatic capacitance 4C Q bundle C E n C Q 2e = hv Energy needed to add an electron at an available quantum state above Fermi level (v F = Fermi velocity) (Datta, Quantum Transport, 2005) 2 F Isolated (4 channels) C E d = y 2πε y ln d C 4C Q 4C Q Bundle of n s C 1 bundle bundle Q = C = C 1 Q bundle Q n + C 1 bundle E N. Srivastava et al., IEDM 2005

Bundle Electrostatic Capacitance C bundle E n 2 2 3(n 2) 5 W H = 2CEn + CEf + CEn Empirically obtained from FastCap simulations n w and n H are number of tubes along Verified for 45, 32, 22 nm the width and height respectively nodes C En : electrostatic capacitance of isolated with separation to ground equal to wire width C Ef : electrostatic capacitance of isolated with separation to ground equal to twice wire width

Interconnect Equivalent Circuit R C 2n + R Q Lbundle Lbundle bundle C Q R C 2n bundle C Q + R Q if L < λ bundle C E bundle C E R C 2n + R Q R n S Lbundle R n bundle C Q S Lbundle R C 2n bundle C Q + R Q if L >> λ bundle C E bundle C E

Interconnect R/C (vs Cu) Dense bundle; Length = 1 um Impact of metal-nanotube contact resistance R C will decrease for long length interconnects Curvature of nanotubes at edge of bundle vs straight edges of Cu interconnect leads to larger capacitance N. Srivastava et al., IEDM 2005

Local Interconnect Delay Ratio τ p () : τ p (Cu) Dense bundle, perfect contacts Sparse bundle, perfect contacts Sparse bundle has lower capacitance, assuming uniform distribution of metallic s N. Srivastava et al., IEDM 2005

Optimally Buffered Global Interconnect Delay Optimal s and l 1.6 Ratio τ p () : τ p (Cu) 1.2 0.8 0.4 Large λ desirable High metallic density desirable Optimal metallic density exists need accurate modeling 10 5 10 6 2 N. Srivastava et al., IEDM 2005

Optimally Buffered Global Interconnect Power Dissipation Optimal s and l Ratio (P/l) τopt () : (P/l) τopt (Cu) Near maximum metallic density desirable N. Srivastava et al., IEDM 2005

Interconnect Reliability and Back-End Thermal Management

Reliability and current carrying capacity of MWs Current density up to 10 10 A/cm 2 without heatsink (not embedded in SiO 2 ) Equivalent Au-, Cu-, Alwires deteriorate at 10 7 A/cm 2 Wei et al. APL 79, 1172 (2001) SWs show similar current carrying capacity [Radosavljevic et al., PRB, 2001]

Back-end Thermal Management with vias 600 500 400 300 200 100 0 22 32 Kth high 45 Technology node (nm) Maximum interconnect temperature rise is significantly smaller when bundles are used as inter-layer vias J. Hone et al., Phys. Rev. B, 1999; App. Phys. Lett., 2000 Srivastava et al., IEDM 2005

Impact of Vias on Cu Interconnect Reliability and Performance 2 orders of magnitude improvement in the lifetime of Cu! Srivastava et al. IEDM 2005 Hybridization of vias with Cu lines can help extend the lifetime of Cu Delay also improves by 30%...

Interconnect Process Integration

interconnect (via) fabrication Catalytic Growth nature does it for you.all you need is 3 ingredients 1. Catalyst nanocluster: Fe, Ni or Co 2. Carbon containing compound (gas): CH4, C2H2, CH3CH2OH. 3. Energy (Temperature): 500-1400 0 C Substrate catalyst interaction is also very important. Courtesy: F. Kreupl, Infineon

Fabrication Techniques & Challenges-I Long throat catalytic deposition (via PVD) in high aspect ratio trenches Duesberg et al., Nanoletters, 2003 nanotube Via definition by resist Via etch Long throat catalyst deposition lift-off Nanotube growth Challenges: i) sidewall deposition causes sidewall growth---via filled but no electrical contact to the bottom! ii) catalyst thickness and nucleation depends strongly on surface condition after etch, results are irreproducible.

Fabrication Techniques & Challenges-III Buried catalyst layer [Graham et. al., Diamond and Related Materials, 2004, Liebau et al., AIP P., Kirchberg, 2004] Etching of via stops on top of 1-31 3 nm thick catalyst layer Via definition by resist Via etch stop on catalyst Resist strip Nanotube growth Challenges: i) etch stop on thin catalyst layer is critical ii) Wafer/chip scale homogeneity not yet demonstrated

Fabrication Techniques & Challenges-III Buried catalyst layer: embedding and top contact Length of nanotube can be adjusted via growth time In dual damascene approach, the top metal can be deposited immediately and proceed as usual. Nanotube growth in Dual Damascene structure Metal deposition CMP Courtesy: F. Kreupl, Infineon

Fabrication Techniques & Challenges-II Overcomes the need for etching high aspect ratio vias needed in future technologies Can reliably grow MW bundles [Li et. al., (NASA) APL, 2003] Challenges: i) quality of s is low and so is electrical conductivity ii) tilt for small diameter tubes is also considerable---subsequent litho step is difficult

Integration Issues Process advantages vis-à-vis copper Diffusivity into Si/dielectric is not a problem--- ---no need for barrier Bottom-up growth processes can eliminate the need for etching high aspect ratio vias Key Issues: Difficult to grow dense metallic SW bundles Most interconnect processes so far employ MWs which have been easier to grow-- --recently it has become possible to grow bundles of SWs also by adding water or oxygen to increase of the growth catalyst High temperatures involved in growth Metal- contact resistance Control over growth mode (substrate-catalyst interaction)

Summary: Vs Cu Local Intermediate Global Via/Contact Performance Comparable to Cu Exceeds Cu Exceeds Cu Comparable to Cu Power --- --- Comparable to Cu --- Reliability Far superior to Cu Far superior to Cu Far superior to Cu Far superior to Cu Process Tech Requirement Sparse bundle; Low contact res. Dense metallic SW bundle Dense metallic SW bundle Dense metallic SW bundle; Low contact res. interconnects look promising. Process development and modeling must happen concurrently..a lot of work still remains!!

Acknowledgements Navin Srivastava (PhD Candidate) Dr. Sungjun Im (Post-doctoral Researcher) Dr. Franz Kreupl (Infineon) Funding agencies: NIST and SRC

Quantum Resistance S. Datta, Nanotechnology, 2004 I e γ γ = h γ [ f ] 1 2 1 2 1 + γ f 2 I Energy level broadens due to coupling with contacts 4e = h 2 Ideal (max.) conductance: γ 1γ 2 γ + γ 1 γ 1 2 V γ + γ 1 = γ 2 2 e 2 V h I : G = = V 2 e h Carbon nanotube has 4 conducting channels: R Q = h 2 4e R ; For L > λ : S ( p. u. l) = h 4e 2 1 λ