Lecture 120 Filters and Charge Pumps (6/9/03) Page 1201 LECTURE 120 FILTERS AND CHARGE PUMPS (READING: [4,6,9,10]) Objective The objective of this presentation is examine the circuits aspects of loop filters and charge pumps suitable for PLLs in more detail. Outline Filters Charge Pumps Summary Lecture 120 Filters and Charge Pumps (6/9/03) Page 1202 Why Does the PLL Need a Filter? Input Signal Oscillator Output Signal Phase Frequency Detector FILTERS Error Signal Voltage Controlled Oscillator Loop Filter Contolling Voltage Fig. 0101 The loop filter is important to the performance of the PLL. 1.) Removes high frequency noise of the detector 2.) Influences the hold and capture ranges 3.) Influences the switching speed of the loop in lock. 4.) Easy way to change the dynamics of the PLL
Lecture 120 Filters and Charge Pumps (6/9/03) Page 1203 Passive Loop Filters 1 1.) F(s) = 1 = s C 1 1 = 1 1 sτ1, τ 1 = C 1 sc 1 R 2 1 sc scr 2 1 2.) F(s) = R 2 1 = sc ( R 2 ) 1 = sc τ 1 = C( R 2 ) and τ 2 = R 2 C 1 sτ 2 1 sτ 1 C 1 Fig. 3.126 C R 2 Advantages: Linear Relatively low noise Unlimited frequency range Disadvantages: Hard to integrate when the values are large (C>100pF and R > 100kΩ) Difficult to get a pole at the origin (increase the order of the type of PLL) Fig. 3.127 Lecture 120 Filters and Charge Pumps (6/9/03) Page 1204 Active Filters 1.) Active lag filteri R 2 1 sc 2 F(s) = 1 = sc 1 = C 1 C 2 C 1 C 2 sr 2 C 2 1 s C 1 1 sτ 2 1 sτ 1 1, τ 1 = C 1 and τ 2 = R 2 C 2 C 1 R 2 C 2 Fig. 3.128 2.) Active lag filter II 1 R 2 sc 2 R 2 1 sc 2 F(s) = 1 = R 1 sc 1 1 sc 1 R 2 s C 1 1 sr 2 C 2 1 = R 2 sτ 1 1 sτ 2 1 C 1 R 2 C 2 Fig. 3.129
Lecture 120 Filters and Charge Pumps (6/9/03) Page 1205 Active Filters Continued 3.) Active PI filter. R 2 1 sc 2 F(s) = = sr 2 C 2 1 s C 2 sτ 2 1 = sτ 1 τ 1 = C 2 and τ 2 = R 2 C 2 Advantages: Can get poles at the origin Can reduce the passive element sizes using transresistance We can show that (eq.) = 2 2 R x Assume = 10kΩ and R x = 10Ω gives (eq.) = 20kΩ 100,000kΩ 10Ω 10MΩ Disadvantages: Noise Power Frequency limitation R 2 C 2 V in i x Fig. 3.130 R 2 C 2 Fig. 3.131 Lecture 120 Filters and Charge Pumps (6/9/03) Page 1206 HigherOrder Active Filters 1.) Cascading firstorder filters (all poles are on the negative real axis) Uses more op amps and dissipates more power. 2.) Extending the laglead filter. V in 2 2 R 2 C 2 V out C 3 Fig. 12002 From the previous slide we can write, sr 1 C 3 Z 1 (s)(eq.) = 4 1 and Z 2(s) = sr 2C 2 1 sc 2 sr 2 C 2 1 V out sc 2 sr 2 C 2 1 sτ 2 1 V in = sr 1 C = 3 sr 1 C = 3 sτ 1 (sτ 3 1) 4 1 sc 2 4 1 where τ 1 = C 2, τ 2 = R 2 C 2, and τ 3 = 0.25 C 3 The additional pole could also be implemented by an RC network at the output. However, now the output resistance is not small any more.
Lecture 120 Filters and Charge Pumps (6/9/03) Page 1207 NonIdealities of Active Filters DC Offsets: Model V IO Example v in R 2 vout v in V R IO 1 R 2 v out I OS I OS What is the input and output offset voltages of this example? Output offset voltage = V OS (out) = V IO R 2 I OS R 2 Fig. 12001 Input offset voltage = V OS (in) = V IO I OS Assume the op amp is a 741 with V IO = 3mV, I OS = 100nA, and = R 2 = 10kΩ. V OS (out) = 3mV 10kΩ 100nA = 4mV V OS (in) = 3mV 10kΩ 100nA = 2mV We have seen previously that these input offset voltages can lead to large spurs in the PLL output. Lecture 120 Filters and Charge Pumps (6/9/03) Page 1208 NonIdealities of Active Filters Continued Inverting and Noninverting Amplifiers: R 2 vout v IN R 2 vout v IN Gain and GB = : V out V in = R 2 Gain, GB = : V out (s) V in (s) = R 1 R 2 Gain, GB : V out (s) V in (s) = R 1 R 2 A vd (0) R 2 1 A vd(0) R 2 GB R 2 s GB R 1 R 2 = R 2 ω H sω H V out V in = R 2 Fig. 9.201 A vd (0) V out (s) V in (s) = R 2 R 1 R 2 1 A vd(0) R 2 GB V out (s) V in (s) = R 2 R 2 s GB R 1 = R 2 ω H sω H R 2
Lecture 120 Filters and Charge Pumps (6/9/03) Page 1209 NonIdealities of Active Filters Continued Example: Assume that the noninverting and inverting voltage amplifiers have been designed for a voltage gain of 10 and 10. If A vd (0) is 1000, find the actual voltage gains for each amplifier. Solution For the noninverting amplifier, the ratio of R 2 / is 9. A vd (0) /( R 2 ) = 1000 19 = 100. V out 100 V in = 10 101 = 9.901 rather than 10. For the inverting amplifier, the ratio of R 2 / is 10. A vd (0) R 2 = 1000 110 = 90.909 V out 90.909 V in = (10) 190.909 = 9.891 rather than 10. Lecture 120 Filters and Charge Pumps (6/9/03) Page 12010 NonIdealities of Active Filters Continued Finite Gainbandwidth: Assume that the noninverting and inverting voltage amplifiers have been designed for a voltage gain of 1 and 1. If the unitygainbandwidth, GB, of the op amps are 2πMrads/sec, find the upper 3dB frequency for each amplifier. Solution In both cases, the upper 3dB frequency is given by ω H = GB R 2 For the noninverting amplifier with an ideal gain of 1, the value of R 2 / is zero. ω H = GB = 2π Mrads/sec (1MHz) For the inverting amplifier with an ideal gain of 1, the value of R 2 / is one. ω H = GB 1 11 = GB 2 = π Mrads/sec (500kHz)
Lecture 120 Filters and Charge Pumps (6/9/03) Page 12011 NonIdealities of Active Filters Continued Integrators Finite Gain and Gainbandwidth: A vd (s) s C 2 s C 2 1 where V out 1 V in = s C 2 A vd (s) = A vd(0)ω a sω a = 1 A vd(s) s C 2 s C 2 1 = GB GB sω a s ω I s A vd (s) (s/ω Ι ) (s/ω Ι ) 1 1 A vd(s) (s/ω Ι ) (s/ω Ι ) 1 Case 1: s 0 A vd (s) = A vd (0) V out V in A vd (0) Case 2: s A vd (s) = GB s Case 3: 0 < s < A vd (s) = V out (jω)/vin(jω) A vd (0) db 0 db Eq. (1) ω x1 = ω I A vd (0) ω I Eq. (3) Eq. (2) ω x2 = V out GB log10 ω GB V in V out V ω I in s Arg[V out (jω)/v in (jω)] 180 135 90 45 0 ω I s s ω I 10A vd (0) 10ωI A vd (0) GB 10 10GB ω I A vd (0) GB log 10 ω Lecture 120 Filters and Charge Pumps (6/9/03) Page 12012 CHARGE PUMPS The use of the PFD permits the use of a charge pump in place of the conventional PD and low pass filter. The advantages of the PFD and charge pump include: The capture range is only limited by the VCO output frequency range The static phase error is zero if the mismatches and offsets are negligible. A I 1 B A B PFD I 1 =I 2 =I Q A Q B X Y I 2 V out C p Q A Q B V out Fig. 12.42N t Q A high deposits charge on C p (A leads B). Q B high removes charge from C p (B leads A). Q A and Q B low V out remains constant. We have seen that a resistor in series with C p is necessary for stability. (QB is high for a short time due to reset delay but the difference between average values between QA and QB still accurately represents the input phase or frequency difference.)
Lecture 120 Filters and Charge Pumps (6/9/03) Page 12013 Types of Charge Pumps Conventional TriStage Low power consumption, moderate speed, moderate clock skew Low power frequency synthesizers, digital clock generators Current Steering Static current consumption, high speed, moderate clock skew High speed PLL (>100MHz), translation loop, digital clock generators Differential input with SingleEnded output Medium power, moderate speed, low clock skew Lowskew digital clock generators, frequency synthesizers Fully Differential Static current consumption, high speed (>100MHz) Digital clock generators, translation loop, frequency synthesizer (with onchip filter) Advantages of charge pumps Consume less power than active filters Have less noise than active filters Do not have the offset voltage of op amps Provide a pole at the origin More compatible with the objective of putting the filter on chip Lecture 120 Filters and Charge Pumps (6/9/03) Page 12014 Nonidealities in Charge Pumps Leakage current: Small currents that flow when the switch is off. Mismatches in the Charge Pump: The up and down (charge and discharge) currents are unequal. Timing Mismatch in PFD: Any mismatch in the time at which the PFD provides the up and down outputs. Charge Sharing: The presence of parasitic capacitors will cause the charge on the desired capacitor to be shared with the parasitic capacitors. Woogeun Rhee, Design of HighPerformance CMOS Charge Pumps in PhaseLocked Loops, Proc. of 1999 ISCAS, Page II545II548, May 1999.
Lecture 120 Filters and Charge Pumps (6/9/03) Page 12015 Charge Pumps The low pass filter in the PLL can be implemented by: 1.) Active filters which require an op amp 2.) Passive filters and a charge pump. The advantages of a charge pump are: Reduced noise Reduced power consumption No offset voltage Passive Filter Fig. 12.422 V c MP5 MN5 1 I N1 MP3 MP4 2 I N2 MN3 MN4 MP2 MP1 I out MN1 MN2 Lecture 120 Filters and Charge Pumps (6/9/03) Page 12016 DiscriminatorAided PFD/Charge Pump This circuit reduces the pullin time, T P, and enhances the switching speed of the PLL while maintaining the same noise bandwidth and avoiding modulation damping. Technique: Increase the gain of the phase detector for increasing values of phase error. i P i P θ e θ AD θ AD θ e Characteristic of a Conventional PD Characteristic of a Nonlinear PD Fig. 3.132 The gain of the phase detector is increased when θ e becomes larger than θ AD or smaller than θ AD. During the time the phase detector gain has increased by k, the loop filter bandwidth is also increased by k. CY Yang and SI Liu, FastSwitching Frequency Synthesizer with a DiscriminatorAided Phase Detector, IEEE J. of SolidState Circuits, Vol. 35, No. 10, Oct. 2000, pp. 14451452.
Lecture 120 Filters and Charge Pumps (6/9/03) Page 12017 DiscriminatorAided Phase Detector (DAPD) Continued Schematic of a phase detector with DAPD and chargepump filter: I p0 (k 2 1)I p0 If the absolute value of the delay between V i and V osc is greater than τ AD, the output signal of the DAPD is high and increases the charge pump current by k 2 and adjusts the loop filter bandwidth. V i V osc Delay τ AD Delay τ AD R U PD V D R U PD V D R U PD V D Low Pass Filter Low Pass U AD Filter DiscriminatorAided Phase Detector 0.35µm CMOS: Switching time for a 448 MHz to 462 MHz step is reduced from 90µs to 15µs (k = 3). I p0 (k 2 1)I p0 D AD R AD FLD C z Fig. 3.133 R z C p V c Lecture 120 Filters and Charge Pumps (6/9/03) Page 12018 A TypeI Charge Pump This PLL uses an onchip, passive discretetime loop filter with a single state, chargepump to implement the loop filter. The stabilization zero is created in the discretetime domain rather than using RC time constants. Block diagram of the TypeI, charge pump PLL frequency synthesizer: (Test chip) Sampling pulse generation Clock buffer Vref Two state PFD Vdiv b Charge Pump Vcp Clk Clkb Reset Discretetime domain loop filter Vh RC low pass filter (optional) Programmable divider VCO Vtune Fig. 12003 B. Zhang, P.E. Allen and J.M. Huard, A Fast Switching PLL Frequency Synthesizer With an OnChip Passive DiscreteTime Loop Filter in 0.25µm CMOS, IEEE J. of SolidState Circuits, vol. 38, no. 6, June 2003, pp. 855865.
Lecture 120 Filters and Charge Pumps (6/9/03) Page 12019 TypeI Charge Pump Continued Comparison of a conventional 3state PFD and a 2state PFD: V dd V ref V div D Q Clk Qb Rst Rst Clk Qb D Q NAND V dd V ref V div D Q Clk Qb Rst Rst Clk Qb D Q NAND b Conventional 3state PFD Dual polarity and single polarity charge pumps: 2state PFD Fig. 12004 I D I D Vcp Vcp I D C load Dual Polarity Single Polarity Fig. 12005 Lecture 120 Filters and Charge Pumps (6/9/03) Page 12020 Single Polarity Charge Pump I Bias M4 M5 M6 M7 R V cp b M8 M9 M12 M10 No matching problems. Fig. 12007
Lecture 120 Filters and Charge Pumps (6/9/03) Page 12021 TypeI Charge Pump Continued The discretetime loop filter: V cp S1 Vch S2 C s Ch Fig12006 F 1 (s) (1z 1 ) k lff 1 (s) s where z = e st s, T s is the sampling period (S1), k lf is a gain constant, and f 1 (s) accounts for the loading effect of the low pass filter. The openloop transfer function of this system is given as, T(s) = (1z 1 ) K dk o k lf f 1 (s) s 2 N T(s) = (st s ) K dk o k lf f 1 (s) s 2 N = T sk d K o k lf f 1 (s) sn which is a Type I system if ω <<2π/T s. Lecture 120 Filters and Charge Pumps (6/9/03) Page 12022 TypeI Charge Pump Continued Clock generator and clock waveforms: Discretetime loop filter: 2 Enable 3 V s 4 PRE 5 D O 6 CLK O CLR 1 M4 M8 M17 M18 M19 M23 M20 M24 V cp M35 Reset M28 C s Clk M30 M31 M34 M29 M33 M32 V h C h M6 M7 M25 M26 M27 Clkb M16 M12 M10 M15 M11 M9 Fig. 12007
Lecture 120 Filters and Charge Pumps (6/9/03) Page 12023 TypeI Charge Pump Continued Comparison of the frequency response of the conventional and single state architectures: Conventional architecture Singlestate architecture Results: Conventional Architecture TypeI Architecture Reference spur 53dBc 62dBc Switching time 140µs 30µs Loop filter size Offchip filter Integrated (70pF) Lecture 120 Filters and Charge Pumps (6/9/03) Page 12024 Use of Active Filters with Charge Pumps SecondOrder PLL: Vcp C 1 Vcp PLL Crossover Frequency: K 2 τ 2 K 4 τ 4 4 K 4 ω c2 = 2 where K = K v NC 1 PLL Settling Time for a Frequency step of ω: 4 t s2 ω 2 1 1 K 4 τ 4 c2 2 ln C 1 ω αn 1 τ K where α = 2 2 Fig. 12009 θ(t s2 ) θ( )
Lecture 120 Filters and Charge Pumps (6/9/03) Page 12025 Charge Pump with a ThirdOrder Filter The additional pole of a thirdorder PLL provides more spurious suppression. However, the phase lag associated with the pole introduces a stability issue. Circuit: The impedance of the loop filter is, b sτ 1 C 1 Z(s) = b1 s 2 sτ C 1 where τ = C 1 and b = b1 1 C 2 The loop gain for this PLL is LG(s) = K o b sτ 1 2πN b1 s 2 sτ C 1 b1 1 The phase margin of the loop is, PM = tan 1 (τω c3 ) tan 1 τω c3 b1 where ω c3 is the crossover frequency C 1 Vcp C 2 C 1 C 2 Vcp Fig. 12010 Lecture 120 Filters and Charge Pumps (6/9/03) Page 12026 Charge Pump with a ThirdOrder Filter Continued Differentiating with respect to ω c3, shows that max. phase margin occurs when ω c3 = b1 /τ PM(max) = tan 1 ( b1 ) tan 1 1 b1 Maximum phase margin as a function of b = C 1 /C 2. Phase Margin (Degrees) 80 70 60 50 40 30 20 10 0 0 20 40 60 80 100 b = C 1 /C 2 Fig. 12011 Note that for b 1, the phase margin is less than 20.
Lecture 120 Filters and Charge Pumps (6/9/03) Page 12027 Charge Pump with a ThirdOrder Filter Continued An analytical expression for settling time is difficult to calculate for the thirdorder filter. The following figure shows the simulated settling time to 10ppm accuracy as a function of phase margin when ω/n = 0.04 (ω i = ω ref ). t s3 /T i = ts3/t ref Phase Margin Degrees For ω/n < 0.04 and 20 <PM<79, we may estimate the settling time to 10ppm accuracy as t s3 2π ω c3 [0.0067 PM 2 0.6303 PM 16.78] Lecture 120 Filters and Charge Pumps (6/9/03) Page 12028 Charge Pump with a ThirdOrder Filter Continued A loop filter design recipe: 1.) Find K v for the VCO. 2.) Choose a desired PM and find b from the max. PM equation. 3.) Choose the crossover frequency, ω c3, and find τ from ω c3 = b1 /τ. 4.) Select C 1 and such that they satisfy K v b 2πN b1 = C 1 τ 2 b1 5.) Calculate the noise contribution of 2. If the calculated noise is negligible the design is complete. If not, then go back to step 4.) and increase C 1. Example: Let K v = 10 7 rads/sec., N = 1000, PM = 50 and f c3 = 10kHz. Now, 50 = tan 1 ( b1 ) tan 1 1 b 6.65 (by iteration) b1 b1 τ = 2π f c3 = 6.651 2π 1000 = 0.44 msec If = 200µA, then C 1 = K v b τ 2 2πN b1 b1 = 19.34 nf = τ C 1 = 22.72kΩ Noise = 4kTR = 4(1.38x10 23 )(300)(22.72kΩ) = 3.76x1016 V 2 /Hz
Lecture 120 Filters and Charge Pumps (6/9/03) Page 12029 Charge Pump with a FourthOrder Filter To further reduce the spurs with out decreasing the crossover frequency and thereby increasing the settling time, an additional pole needs to be added to the loop. Circuit: C 2 C 1 R 3 C 2 Vcp C 3 C 1 R 3 Vcp C 3 Fig. 12012 The impedance of the passive filter is given as, sτ 1 Z(s) = sc 1 1 C 2 C C 3 1 C 1 B(sτ) 2 Asτ 1 where 1b τ 2 τ 1 C 2 C 1 A = 1b, B = b τ 2C 2 C 1 1b τc 1, τ = C 1, τ 3 = R 3 C 3 and b = C 2 C 3 Lecture 120 Filters and Charge Pumps (6/9/03) Page 12030 Charge Pump with a FourthOrder Filter Continued Phase margin: PM = tan 1 (τω c4 ) tan 1 A(τω c4 ) 1B(τω c4 ) 2 where ω c4 = crossover frequency The maximum phase margin is obtained when the derivative of the above equation with respect to ω c4 is set to zero. The results are: ω c4 = 1 1 τ 2 2BABAA 2 2BABAA 2 2 4(1A) B(BA) B(BA) B(BA) For ω c4 to be the crossover frequency, it must satisfy the following equation, K v 1(τω c4 ) 2 1b 2πN (Aτω c4 ) 2 [1B(τω c4 ) 2 ] 2 = C 1 b ω c4 2 Practical simplifications: A positive phase margin Zero lower than the two high frequency poles C 2 C < 1 1 For the fourth pole not to decrease the phase margin it has to be more than a decade away from the zero, therefore, b τ 2 τ << 1. With these conditions we find that B << A.
Lecture 120 Filters and Charge Pumps (6/9/03) Page 12031 Charge Pump with a FourthOrder Filter Continued If B << A, then the previous relationships become, A 1 1b, ω 1 c4 τ A 1b τ and K v b 2πN 1b C 1 τ 2 1b The maximum phase margin also simplifies to, PM(max) tan 1 ( 1b) tan 1 1 1b Exact phase margin: Lecture 120 Filters and Charge Pumps (6/9/03) Page 12032 Charge Pump with a FourthOrder Filter Continued Simulation is used to estimate the settling time of the fourthorder loop to 10 ppm accuracy when ω/n < 0.04: t 4 /T i = t s4 /T ref Phase Margin Degrees Note that the settling time at a given phase margin is independent of τ 2 /τ and is the same as that of a thirdorder loop.
Lecture 120 Filters and Charge Pumps (6/9/03) Page 12033 Charge Pump with a FourthOrder Filter Continued Spur suppression of the fourthorder filter. Lecture 120 Filters and Charge Pumps (6/9/03) Page 12034 Charge Pump with a FourthOrder Filter Continued Loop filter design procedure: 1.) Find K v for the VCO. 2.) Choose a desired phase margin and find b. (If PM = 50, then b = 6.5) 3.) Choose the crossover frequency ω c4 and find τ. (τ 2.7/ω c4 if b = 6.5) 4.) Choose the desired spur attenuation and find τ 2 /τ from the previous page. 5.) Select C 1 and such that they satisfy K v b 2πN 1b C 1 τ 2 1b. 6.) Calculate the noise contribution of and R 3. Example: Let K v = 10 7 rads/sec., N = 1000, PM = 50, f c4 = 1kHz and f ref = 100kHz. Since PM = 50, b = 6.5 τ 2.7/ω c4 = 2.7/(2π 1000) = 430µsec. Let us choose τ 2 /τ as 0.1 which corresponds to about 90dB of suppression. If = 200µA, then C 1 = K v b τ 2 2πN b1 b1 = 18.63 nf = τ C 1 = 23.09kΩ τ 2 = 0.1τ = 43µsec If C 3 = 1nF, then R 3 = τ 2 /C 3 = 43µsec/1nF = 43kΩ Noise: v 2 R1 = 4kT = 3.823 x10 16 V 2 /Hz and v 2 R3 = 4kTR 3 = 7.12 x10 16 V 2 /Hz
Lecture 120 Filters and Charge Pumps (6/9/03) Page 12035 Charge Pump with a FourthOrder Filter Continued Open loop transfer function for a typical fourthorder PLL: PSPICE File: Fourthorder, chargepump PLL loop gain.param N=1000, KVCO=1E7, T=0.43E3, T2=43E6, KD=1, E=10.PARAM A=0.2287 B=0.00868 *VCO Noise Transfer Function VIN 1 0 AC 1.0 RIN 1 0 10K EDPLL1 2 0 LAPLACE {V(1)}= {KD*KVCO*46.52E6*(S*T1)/(SE)/(SE)/(B*T*T*S*SA*T*S1)} RDPLL1 2 0 10K *Steady state AC analysis.ac DEC 20 10 100MEG.PRINT AC VDB(2) VP(2).PROBE.END db or Degrees 250 200 150 100 50 0 50 Magnitude Phase Margin 90 Phase Shift 100 10 100 1000 10 4 10 5 10 6 10 7 10 8 Frequency (Hz) Fig. 12013 Lecture 120 Filters and Charge Pumps (6/9/03) Page 12036 SUMMARY Filters Determines the dynamic performance of the PLL Active and passive filters Order of the filter higher the order, the more noise and spur suppression Nonidealities of active filters DC offsets Finite op amp gain Finite gainbandwidth Noise Charge Pumps Avoid the use of the op amp to achieve a pole at the origin (TypeII systems) Nonidealities in charge pumps Leakage current Mismatches in the up and down currents Timing mismatches Charge sharing