Thermal Management at Nanoscale: Problems and Opportunities Alexander A. Balandin Nano-Device Laboratory Department of Electrical Engineering and Materials Science and Engineering Program University of California Riverside APEC, Palm Springs, February 2010
City of Riverside UCR Botanic Gardens UCR Bell Tower Joshua Tree Park, California UCR Engineering Building 2
Nano-Device Laboratory (NDL) Department of Electrical Engineering University of California Riverside Profile: experimental and theoretical research in nano materials and devices PI: Alexander A. Balandin Thermal and Electrical Characterization Research & Applications Nanoscale Characterization Device Design and Characterization Direct Energy Conversion Optoelectronics Bio- Nanotech Electronic Devices and Circuits Theory and Modeling Raman, Fluorescence and PL Spectroscopy Research at NDL is funded by NSF, ONR, SRC, DARPA, NASA, ARO, AFOSR, CRDF, as well as industry, including IBM, Raytheon, TRW, etc.
Outline Motivations Downscaling and the thermal issues High-power density electronics and heat removal New approaches for thermal management High-heat-flux method and hot-spot spreading Thermal Conductivity of Graphene New non-contact measurement technique Graphene vs carbon nanotubes New possibilities Conclusions Trench Graphene 4
The Thermal Show Stopper for Electronics IEEE Spectrum illustration of the thermal issues in the feature article A.A. Balandin, Chill Out: New Materials and Designs Can Keep Chips Cool (October 2009) The old industry approach does not work No BIG fan solutions!
Trends: Increase in Thermal Design Power Thermal design power is the maximum sustained power dissipated by the microprocessors TDP was increasing with increasing performance complicating thermal management. Data is after R. Mahajan et al., Proceed. IEEE (2006) The problem of hot spots: The switch to multi-core designs Non-uniform power densities Power densities above 500 W/cm 2 6
ITRS: Thermal Management Issues IC performance is now limited by the power, which can be dissipated without exceeding the maximum T set by the reliability requirements. ITRS: power consumption, both dynamic and static, related to unavoidable leakage currents, is an urgent challenge. In the next five years up to 80% of microprocessor power will be consumed by the interconnect wiring (compare to 51% at 130 nm node). Power dissipation in the interconnect structure will increase dramatically due to higher clock frequencies and increase in the number of metal layers and interfaces. Joule heating in the interconnects may result in significantly higher temperature rise as compared to power dissipated in active devices. 7
New Aspects of Thermal Transport in Nanoscale Devices and Circuits Technology Trends: Increasing number of interconnects Increasing power density Increased leakage current High switching frequencies Increased thermal resistance of the chip Thermal boundary resistance Materials with low thermal conductivity New Phenomena at Nanoscale: Acoustic phonon MFP in bulk crystalline Si at T=300K (Debye model): ~ 50 nm Comparison: electron MFP in Si: 7.6 nm Dominant phonon wavelength in Si 1.4 nm at T=300 K or 4 mm at T=0.1 K Device Feature Sizes CMOS gate length < 50 nm CMOS gate-oxide thickness ~ 1.2 nm Superlattice period: ~ 1.5 nm modified from IBM picture Nanostructured materials do not conduct heat as well as bulk materials 8
Thermal Issues in High-Power Density Electronics: GaN FETs Strategy: Incorporation of the thermal management constrains early at the device design stage 200 nm n GaN Active Layer 3 μm SI GaN Buffer R bd 100-300 μm Substrate 120 100 80 60 40 20 Transconductance (ms/mm) 140 V ds =6V 25C 50C 100C 150C 200C 250C W.L. Liu, V.O. Turin, A.A. Balandin, Y.L. Chen and K.L. Wang, MRS J. of Nitride Semi Research, 9, 7 (2004). 0-4 -3-2 -1 0 1 2 3 4 Gate-Source Voltage (V)
The Nano-Problem : Thermal Conductivity Degradation at Nanoscale Thermal conductivity definition: Q& / A= K T RT thermal conductivity values for important materials: Si: 145 W/mK SiO 2 : 1-13 W/mK GaN: 150-300 W/mK Diamond: 1000 2200 W/mK Graphite: 200 2000 W/mK CNTs: 3000 3500 W/mK THERMAL CONDUCTIVITY (W/m-K) 160 140 120 100 80 60 40 20 Si Bulk J. Zou and A.A. Balandin, J. Appl. Phys., 89, 2932 (2001). Si Nanowire: A Si Nanowire: B Diffuse Scattering (p=0) 0 300 400 500 600 700 800 TEMPERATURE (K) Phonon - boundary scattering Phonon spectrum changes
Composite Substrates: Diamond Materials For Hot Spot Spreading New Developments: Micro-crystalline diamond on Si Si wafers become thinner (consider the effects on the Si cost of the rapid developments in solar cells) Progress in synthetic diamond deposition and growth Diamond heat spreaders will be closer to heat generation areas in thinned Si wafers Issues: Compatibility with Si CMOS Cost Finding an optimum combination of material properties: grain size vs thermal conductivity vs. interface quality vs. temperature of deposition Nano-crystalline diamond on Si
Finding the Optimum Synthetic Diamond - Si Combination Thermal Conductivity (W/cmK) Nanocrystalline diamond offers smoother interface but lower thermal conductivity 10 2 10 1 10 0 10-1 10-2 10-3 Bulk Diamond: Callaway Model Hopping Model (2μm, t=0.9) Hopping Model (22nm, t=0.32) Hopping Model (26nm, t=0.2) 200 400 Temperature (K) Poly NCD_25 NCD_0 Minimum K for Carbon Thermal Conductivity, K (W/mK) 94 93 92 91 90 89 88 87 86 Ultra-nano-crystalline diamond on silicon substrate 85 10 20 30 40 50 60 70 80 90 100 Temperature ( 0 C) Minimization of the thermal boundary resistance (TBR)
New Unique Material Option: Graphene Individual atomic layers of sp 2 -hybridized carbon bound in two-dimensions. Crystalline graphite is composed of graphene layers. Unrolled Carbon Nanotube Graphene Revolution brought about by K.S. Novoselov and A.K. Geim (Manchester, UK and Chernogolovka, Russia) with the help of bulk graphite and something similar to a Scotch tape. [Novoselov, et al., Science (2004)].
Practical Applications of Graphene: Transistors and Interconnects Normalized Current Noise Density (Hz -1 ) 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 Double-Gate Graphene Transistor V DS =0.05 V G. Liu, et al., Appl. Phys. Lett., 95, 033103 (2009). Q. Shao, et al., IEEE Electron Device Lett., 30, 288 (2009). 1/f V G =0 V V G =10 V V G =20 V V G =30 V V G =40 V 1 10 100 1000 10000 Frequency (Hz)
Prospects of the High-Heat Flux Thermal Management with Graphene Concept change: from the post-chip making level to the device and materials level consideration at nanoscale Passive high-heat flux thermal management at the device/chip level Issues: Insulator vs conductor Anisotropy Thermal expansion Temperature stability Large-area Possible Material Systems: Synthetic diamond Carbon nanotubes Graphene 15
Conventional Measurement Techniques Do Not Work for Graphene 3-ω Thermal Conductivity Setup Transient Plane Source Technique Cr/Au heaterthermometer sensors patterned on top of the samples by photolithography. TEMPERATURE RISE ( o C) 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 SILICON REFERENCE SAMPLE Dissipated Power Sample: 0.05 W Si Wafer: 0.5 W Measurement Time: 5 s 0.0 0 1 2 3 4 5 TIME (s) Laser Flash Technique Thermal conductivity and heat capacity extraction from the T(t) dependence. 16
Micro-Raman Spectroscopy of Graphene Optical visualization on magic substrates Disorder D band: ~ 1350 cm -1 : in-plane A 1g (LA) zone-edge G peak: double degenerate zone center E 2g mode AFM inspection Alternatives: low-temperature transport study cross-sectional TEM A.C. Ferrari et al., Phys. Rev. Lett. 97, 187401 (2006). I. Calizo, A.A. Balandin et al., Nano Letter 7, 2645 (2007) 17
Raman Nanometrology of Graphene Layers Deconvolution of 2D band Double-resonance model 24000 20000 Graphene @ 300K λ exc = 488 nm 5 layers Intensity (arb. units) 16000 12000 8000 4 layers 3 layers 4000 2 layers I. Calizo, et al., Appl. Phys. Lett., 91, 201904 (2007). I. Calizo, et al., Appl. Phys. Lett., 91, 071913 (2007). 1 layer 0 2300 2400 2500 2600 2700 2800 2900 3000 Raman Shift (cm -1 ) 2D-band features of graphene on a standard Si/SiO 2 (300nm) substrate are highly reproducible and, together with the G-peak position, can be used to count the number of graphene layers. 18
UCR Experiment: Heating Up Graphene IEEE Spectrum illustration of the first measurements of thermal conductivity of graphene carried out at UCR. See details in A.A. Balandin et al., Nano Letters, 8, 902 (2008). SEM image of the suspended graphene flake connected to heat sinks
Experimental Approach and Suspended Graphene Layers Graphene flakes suspended across trenches in Si/SiO 2 wafers Trench substrate FLG SLG Trench FLG 20
Extraction of the Thermal Conductivity Data: Raman Spectrometer as a Thermometer Excitation laser acts as a heater: ΔP G Raman spectrometer acts as a thermometer: ΔT G =Δω/χ G Thermal conductivity: K=(L/2a G W)(ΔP G /ΔT G ) K = L a W Δ ΔP 1 ( / 2 G ) χ G ( ω / G ). 4 SUSPENDED GRAPHENE G Peak Position (cm) -1 1590 1588 1586 1584 1582 1580 1578 Single Layer Graphene G Peak Position Linear Fit of Data Intensity (arb. units) slope = -0.016 cm -1 / C 7,500 6,000 4,500 3,000 Single Layer Graphene λexc=488 nm G Peak 1582 cm -1 1500 1550 1600 1650 Raman Shift (cm -1 ) G PEAK POSITION SHIFT (cm -1 ) 2 0-2 -4-6 SLOPE: -1.292 cm -1 /mw EXPERIMENTAL POINTS LINEAR FITTING 1576-200 -150-100 -50 0 50 100 Temperature () 0 1 2 3 4 POWER CHANGE (mw)
Graphene Heat Spreaders Designs for Active Devices and Interconnects SiO 2 (100 nm) Heat Sink Graphene Silicon Substrate (500μm) Heat Sink Heat Sink S. Subrina, D. Kotchetkov and A.A. Balandin, IEEE Electron Device Letters, 30, 1281 (2009).
Nanoscale Phonon Engineering: New Possibilities for Improved Heat Removal Theory: V.A. Fonoberov and A.A. Balandin, Nano Letters, 6, 2442 (2006).
Other 2D Crystals with Wan der Waals Gaps : Thermoelectric Applications (a) Overlapping Regions 1 μm Quintuple thickness: ~1 nm Identification: AFM, SEM, TEM 1 μm
Active On-Spot Cooling of Nano-Devices COVER IMAGE: Applied Physics Letters, February 1, 2010
The Route to Three-Dimensional Electronics Is Carbon the Answer? IEEE Spectrum artistic rendering of the future 3D electronic chips with graphene transistors, graphene interconnects and heat spreaders, CNT electrical and thermal vias. After A.A. Balandin, Chill Out: New Materials and Designs Can Keep Chips Cool (October, 2009).
Conclusions Heat dissipation is a crucial problem for nanometer scale devices and ULSI chips Thermal conductivity of most materials deteriorates when they are structured at nanometer scale There are some materials, which maintain or even improve heat conduction property at nanoscale: graphene Graphene can be used for hot-spot spreading in the active devices and interconnects Possibility for the high-power electronics: better thermal interface materials Concept change for thermal management: from post-chip design effort to materials/device level effort 27
Acknowledgements Balandin group in front of the Nano-Device Laboratory (NDL), 2008